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/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "nvram.h" |
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#include "pc.h" |
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#include "fdc.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "isa.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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#include "ppc.h" |
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#include "boards.h" |
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#include "qemu-log.h" |
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#include "ide.h" |
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#include "loader.h" |
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#include "mc146818rtc.h" |
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#include "blockdev.h" |
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#include "arch_init.h" |
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#include "exec-memory.h" |
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//#define HARD_DEBUG_PPC_IO
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//#define DEBUG_PPC_IO
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1 |
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#define MAX_IDE_BUS 2 |
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#define BIOS_SIZE (1024 * 1024) |
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#define BIOS_FILENAME "ppc_rom.bin" |
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#define KERNEL_LOAD_ADDR 0x01000000 |
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#define INITRD_LOAD_ADDR 0x01800000 |
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#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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#define DEBUG_PPC_IO
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#endif
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#if defined (HARD_DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, ...) \
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do { \
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if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
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qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
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} else { \
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printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
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} \ |
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} while (0) |
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#elif defined (DEBUG_PPC_IO)
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#define PPC_IO_DPRINTF(fmt, ...) \
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qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__) |
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#else
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#define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
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#endif
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/* Constants for devices init */
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static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
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static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
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static const int ide_irq[2] = { 13, 13 }; |
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#define NE2000_NB_MAX 6 |
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static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
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static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
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/* ISA IO ports bridge */
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#define PPC_IO_BASE 0x80000000 |
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/* PowerPC control and status registers */
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#if 0 // Not used
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static struct {
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/* IDs */
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uint32_t veni_devi;
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uint32_t revi;
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/* Control and status */
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uint32_t gcsr;
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uint32_t xcfr;
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uint32_t ct32;
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uint32_t mcsr;
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/* General purpose registers */
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uint32_t gprg[6];
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/* Exceptions */
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uint32_t feen;
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uint32_t fest;
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uint32_t fema;
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uint32_t fecl;
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uint32_t eeen;
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uint32_t eest;
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uint32_t eecl;
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uint32_t eeint;
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uint32_t eemck0;
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uint32_t eemck1;
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/* Error diagnostic */
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} XCSR;
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static void PPC_XCSR_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static void PPC_XCSR_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
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value);
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}
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static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t retval = 0;
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printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
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retval);
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return retval;
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}
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static const MemoryRegionOps PPC_XCSR_ops = {
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.old_mmio = {
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.read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
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.write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#endif
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t { |
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qemu_irq reset_irq; |
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M48t59State *nvram; |
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uint8_t state; |
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uint8_t syscontrol; |
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uint8_t fake_io[2];
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int contiguous_map;
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int endian;
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} sysctrl_t; |
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enum {
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STATE_HARDFILE = 0x01,
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}; |
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static sysctrl_t *sysctrl;
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static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
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val); |
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sysctrl->fake_io[addr - 0x0398] = val;
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} |
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static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
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sysctrl->fake_io[addr - 0x0398]);
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return sysctrl->fake_io[addr - 0x0398]; |
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} |
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static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
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addr - PPC_IO_BASE, val); |
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switch (addr) {
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case 0x0092: |
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/* Special port 92 */
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/* Check soft reset asked */
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if (val & 0x01) { |
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qemu_irq_raise(sysctrl->reset_irq); |
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} else {
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qemu_irq_lower(sysctrl->reset_irq); |
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} |
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/* Check LE mode */
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if (val & 0x02) { |
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sysctrl->endian = 1;
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} else {
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sysctrl->endian = 0;
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} |
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break;
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case 0x0800: |
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/* Motorola CPU configuration register : read-only */
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break;
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case 0x0802: |
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/* Motorola base module feature register : read-only */
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break;
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case 0x0803: |
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/* Motorola base module status register : read-only */
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break;
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case 0x0808: |
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/* Hardfile light register */
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if (val & 1) |
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sysctrl->state |= STATE_HARDFILE; |
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else
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sysctrl->state &= ~STATE_HARDFILE; |
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break;
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case 0x0810: |
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL) |
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m48t59_toggle_lock(sysctrl->nvram, 1);
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break;
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case 0x0812: |
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL) |
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m48t59_toggle_lock(sysctrl->nvram, 2);
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break;
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case 0x0814: |
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/* L2 invalidate register */
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// tlb_flush(first_cpu, 1);
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break;
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case 0x081C: |
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/* system control register */
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sysctrl->syscontrol = val & 0x0F;
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break;
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case 0x0850: |
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/* I/O map type register */
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sysctrl->contiguous_map = val & 0x01;
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break;
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default:
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printf("ERROR: unaffected IO port write: %04" PRIx32
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" => %02" PRIx32"\n", addr, val); |
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break;
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} |
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} |
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static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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uint32_t retval = 0xFF;
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switch (addr) {
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case 0x0092: |
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/* Special port 92 */
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retval = 0x00;
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break;
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case 0x0800: |
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/* Motorola CPU configuration register */
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retval = 0xEF; /* MPC750 */ |
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break;
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case 0x0802: |
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/* Motorola Base module feature register */
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retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
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break;
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case 0x0803: |
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/* Motorola base module status register */
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retval = 0xE0; /* Standard MPC750 */ |
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break;
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case 0x080C: |
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/* Equipment present register:
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* no L2 cache
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* no upgrade processor
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* no cards in PCI slots
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* SCSI fuse is bad
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*/
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retval = 0x3C;
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break;
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case 0x0810: |
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/* Motorola base module extended feature register */
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retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
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break;
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case 0x0814: |
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/* L2 invalidate: don't care */
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break;
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case 0x0818: |
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/* Keylock */
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retval = 0x00;
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break;
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case 0x081C: |
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/* system control register
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* 7 - 6 / 1 - 0: L2 cache enable
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*/
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retval = sysctrl->syscontrol; |
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break;
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case 0x0823: |
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/* */
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retval = 0x03; /* no L2 cache */ |
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break;
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case 0x0850: |
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/* I/O map type register */
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retval = sysctrl->contiguous_map; |
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break;
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default:
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printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
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break;
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} |
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PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
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addr - PPC_IO_BASE, retval); |
341 |
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return retval;
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} |
344 |
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static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl, |
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target_phys_addr_t addr) |
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{ |
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if (sysctrl->contiguous_map == 0) { |
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/* 64 KB contiguous space for IOs */
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addr &= 0xFFFF;
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} else {
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/* 8 MB non-contiguous space for IOs */
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addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
354 |
} |
355 |
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return addr;
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} |
358 |
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static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
360 |
uint32_t value) |
361 |
{ |
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sysctrl_t *sysctrl = opaque; |
363 |
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addr = prep_IO_address(sysctrl, addr); |
365 |
cpu_outb(addr, value); |
366 |
} |
367 |
|
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static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
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{ |
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sysctrl_t *sysctrl = opaque; |
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uint32_t ret; |
372 |
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addr = prep_IO_address(sysctrl, addr); |
374 |
ret = cpu_inb(addr); |
375 |
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return ret;
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} |
378 |
|
379 |
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
380 |
uint32_t value) |
381 |
{ |
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sysctrl_t *sysctrl = opaque; |
383 |
|
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addr = prep_IO_address(sysctrl, addr); |
385 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
386 |
cpu_outw(addr, value); |
387 |
} |
388 |
|
389 |
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
390 |
{ |
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sysctrl_t *sysctrl = opaque; |
392 |
uint32_t ret; |
393 |
|
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addr = prep_IO_address(sysctrl, addr); |
395 |
ret = cpu_inw(addr); |
396 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
397 |
|
398 |
return ret;
|
399 |
} |
400 |
|
401 |
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
402 |
uint32_t value) |
403 |
{ |
404 |
sysctrl_t *sysctrl = opaque; |
405 |
|
406 |
addr = prep_IO_address(sysctrl, addr); |
407 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); |
408 |
cpu_outl(addr, value); |
409 |
} |
410 |
|
411 |
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
412 |
{ |
413 |
sysctrl_t *sysctrl = opaque; |
414 |
uint32_t ret; |
415 |
|
416 |
addr = prep_IO_address(sysctrl, addr); |
417 |
ret = cpu_inl(addr); |
418 |
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); |
419 |
|
420 |
return ret;
|
421 |
} |
422 |
|
423 |
static const MemoryRegionOps PPC_prep_io_ops = { |
424 |
.old_mmio = { |
425 |
.read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, |
426 |
.write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, |
427 |
}, |
428 |
.endianness = DEVICE_LITTLE_ENDIAN, |
429 |
}; |
430 |
|
431 |
#define NVRAM_SIZE 0x2000 |
432 |
|
433 |
static void cpu_request_exit(void *opaque, int irq, int level) |
434 |
{ |
435 |
CPUPPCState *env = cpu_single_env; |
436 |
|
437 |
if (env && level) {
|
438 |
cpu_exit(env); |
439 |
} |
440 |
} |
441 |
|
442 |
static void ppc_prep_reset(void *opaque) |
443 |
{ |
444 |
PowerPCCPU *cpu = opaque; |
445 |
|
446 |
cpu_reset(CPU(cpu)); |
447 |
} |
448 |
|
449 |
/* PowerPC PREP hardware initialisation */
|
450 |
static void ppc_prep_init (ram_addr_t ram_size, |
451 |
const char *boot_device, |
452 |
const char *kernel_filename, |
453 |
const char *kernel_cmdline, |
454 |
const char *initrd_filename, |
455 |
const char *cpu_model) |
456 |
{ |
457 |
MemoryRegion *sysmem = get_system_memory(); |
458 |
PowerPCCPU *cpu = NULL;
|
459 |
CPUPPCState *env = NULL;
|
460 |
char *filename;
|
461 |
nvram_t nvram; |
462 |
M48t59State *m48t59; |
463 |
MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
|
464 |
#if 0
|
465 |
MemoryRegion *xcsr = g_new(MemoryRegion, 1);
|
466 |
#endif
|
467 |
int linux_boot, i, nb_nics1, bios_size;
|
468 |
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
469 |
MemoryRegion *bios = g_new(MemoryRegion, 1);
|
470 |
uint32_t kernel_base, initrd_base; |
471 |
long kernel_size, initrd_size;
|
472 |
DeviceState *dev; |
473 |
SysBusDevice *sys; |
474 |
PCIHostState *pcihost; |
475 |
PCIBus *pci_bus; |
476 |
PCIDevice *pci; |
477 |
ISABus *isa_bus; |
478 |
qemu_irq *cpu_exit_irq; |
479 |
int ppc_boot_device;
|
480 |
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
481 |
DriveInfo *fd[MAX_FD]; |
482 |
|
483 |
sysctrl = g_malloc0(sizeof(sysctrl_t));
|
484 |
|
485 |
linux_boot = (kernel_filename != NULL);
|
486 |
|
487 |
/* init CPUs */
|
488 |
if (cpu_model == NULL) |
489 |
cpu_model = "602";
|
490 |
for (i = 0; i < smp_cpus; i++) { |
491 |
cpu = cpu_ppc_init(cpu_model); |
492 |
if (cpu == NULL) { |
493 |
fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
494 |
exit(1);
|
495 |
} |
496 |
env = &cpu->env; |
497 |
|
498 |
if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
499 |
/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
500 |
cpu_ppc_tb_init(env, 7812500UL);
|
501 |
} else {
|
502 |
/* Set time-base frequency to 100 Mhz */
|
503 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
504 |
} |
505 |
qemu_register_reset(ppc_prep_reset, cpu); |
506 |
} |
507 |
|
508 |
/* allocate RAM */
|
509 |
memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
|
510 |
vmstate_register_ram_global(ram); |
511 |
memory_region_add_subregion(sysmem, 0, ram);
|
512 |
|
513 |
/* allocate and load BIOS */
|
514 |
memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
|
515 |
memory_region_set_readonly(bios, true);
|
516 |
memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios); |
517 |
vmstate_register_ram_global(bios); |
518 |
if (bios_name == NULL) |
519 |
bios_name = BIOS_FILENAME; |
520 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
521 |
if (filename) {
|
522 |
bios_size = get_image_size(filename); |
523 |
} else {
|
524 |
bios_size = -1;
|
525 |
} |
526 |
if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
527 |
target_phys_addr_t bios_addr; |
528 |
bios_size = (bios_size + 0xfff) & ~0xfff; |
529 |
bios_addr = (uint32_t)(-bios_size); |
530 |
bios_size = load_image_targphys(filename, bios_addr, bios_size); |
531 |
} |
532 |
if (bios_size < 0 || bios_size > BIOS_SIZE) { |
533 |
hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
|
534 |
} |
535 |
if (filename) {
|
536 |
g_free(filename); |
537 |
} |
538 |
|
539 |
if (linux_boot) {
|
540 |
kernel_base = KERNEL_LOAD_ADDR; |
541 |
/* now we can load the kernel */
|
542 |
kernel_size = load_image_targphys(kernel_filename, kernel_base, |
543 |
ram_size - kernel_base); |
544 |
if (kernel_size < 0) { |
545 |
hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
|
546 |
exit(1);
|
547 |
} |
548 |
/* load initrd */
|
549 |
if (initrd_filename) {
|
550 |
initrd_base = INITRD_LOAD_ADDR; |
551 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
552 |
ram_size - initrd_base); |
553 |
if (initrd_size < 0) { |
554 |
hw_error("qemu: could not load initial ram disk '%s'\n",
|
555 |
initrd_filename); |
556 |
} |
557 |
} else {
|
558 |
initrd_base = 0;
|
559 |
initrd_size = 0;
|
560 |
} |
561 |
ppc_boot_device = 'm';
|
562 |
} else {
|
563 |
kernel_base = 0;
|
564 |
kernel_size = 0;
|
565 |
initrd_base = 0;
|
566 |
initrd_size = 0;
|
567 |
ppc_boot_device = '\0';
|
568 |
/* For now, OHW cannot boot from the network. */
|
569 |
for (i = 0; boot_device[i] != '\0'; i++) { |
570 |
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
571 |
ppc_boot_device = boot_device[i]; |
572 |
break;
|
573 |
} |
574 |
} |
575 |
if (ppc_boot_device == '\0') { |
576 |
fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
577 |
exit(1);
|
578 |
} |
579 |
} |
580 |
|
581 |
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
582 |
hw_error("Only 6xx bus is supported on PREP machine\n");
|
583 |
} |
584 |
|
585 |
dev = qdev_create(NULL, "raven-pcihost"); |
586 |
sys = sysbus_from_qdev(dev); |
587 |
pcihost = DO_UPCAST(PCIHostState, busdev, sys); |
588 |
pcihost->address_space = get_system_memory(); |
589 |
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); |
590 |
qdev_init_nofail(dev); |
591 |
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
592 |
if (pci_bus == NULL) { |
593 |
fprintf(stderr, "Couldn't create PCI host controller.\n");
|
594 |
exit(1);
|
595 |
} |
596 |
|
597 |
/* PCI -> ISA bridge */
|
598 |
pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); |
599 |
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
600 |
qdev_connect_gpio_out(&pci->qdev, 0,
|
601 |
first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
602 |
qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
|
603 |
sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); |
604 |
sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); |
605 |
sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); |
606 |
sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); |
607 |
isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
|
608 |
|
609 |
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
610 |
memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, |
611 |
"ppc-io", 0x00800000); |
612 |
memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
|
613 |
|
614 |
/* init basic PC hardware */
|
615 |
pci_vga_init(pci_bus); |
616 |
|
617 |
if (serial_hds[0]) |
618 |
serial_isa_init(isa_bus, 0, serial_hds[0]); |
619 |
nb_nics1 = nb_nics; |
620 |
if (nb_nics1 > NE2000_NB_MAX)
|
621 |
nb_nics1 = NE2000_NB_MAX; |
622 |
for(i = 0; i < nb_nics1; i++) { |
623 |
if (nd_table[i].model == NULL) { |
624 |
nd_table[i].model = g_strdup("ne2k_isa");
|
625 |
} |
626 |
if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
627 |
isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], |
628 |
&nd_table[i]); |
629 |
} else {
|
630 |
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
631 |
} |
632 |
} |
633 |
|
634 |
ide_drive_get(hd, MAX_IDE_BUS); |
635 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
636 |
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], |
637 |
hd[2 * i],
|
638 |
hd[2 * i + 1]); |
639 |
} |
640 |
isa_create_simple(isa_bus, "i8042");
|
641 |
|
642 |
// SB16_init();
|
643 |
|
644 |
for(i = 0; i < MAX_FD; i++) { |
645 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
646 |
} |
647 |
fdctrl_init_isa(isa_bus, fd); |
648 |
|
649 |
/* Register fake IO ports for PREP */
|
650 |
sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
651 |
register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
652 |
register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
653 |
/* System control ports */
|
654 |
register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
655 |
register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
656 |
register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
657 |
register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
658 |
/* PowerPC control and status register group */
|
659 |
#if 0
|
660 |
memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
|
661 |
memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
|
662 |
#endif
|
663 |
|
664 |
if (usb_enabled) {
|
665 |
pci_create_simple(pci_bus, -1, "pci-ohci"); |
666 |
} |
667 |
|
668 |
m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
669 |
if (m48t59 == NULL) |
670 |
return;
|
671 |
sysctrl->nvram = m48t59; |
672 |
|
673 |
/* Initialise NVRAM */
|
674 |
nvram.opaque = m48t59; |
675 |
nvram.read_fn = &m48t59_read; |
676 |
nvram.write_fn = &m48t59_write; |
677 |
PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
678 |
kernel_base, kernel_size, |
679 |
kernel_cmdline, |
680 |
initrd_base, initrd_size, |
681 |
/* XXX: need an option to load a NVRAM image */
|
682 |
0,
|
683 |
graphic_width, graphic_height, graphic_depth); |
684 |
|
685 |
/* Special port to get debug messages from Open-Firmware */
|
686 |
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
687 |
|
688 |
/* Initialize audio subsystem */
|
689 |
audio_init(isa_bus, pci_bus); |
690 |
} |
691 |
|
692 |
static QEMUMachine prep_machine = {
|
693 |
.name = "prep",
|
694 |
.desc = "PowerPC PREP platform",
|
695 |
.init = ppc_prep_init, |
696 |
.max_cpus = MAX_CPUS, |
697 |
}; |
698 |
|
699 |
static void prep_machine_init(void) |
700 |
{ |
701 |
qemu_register_machine(&prep_machine); |
702 |
} |
703 |
|
704 |
machine_init(prep_machine_init); |