root / tcg / tcg-op.h @ 0cf767d6
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "tcg.h" |
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/* legacy dyngen operations */
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#include "gen-op.h" |
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int gen_new_label(void); |
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static inline void tcg_gen_op1(int opc, TCGv arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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} |
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static inline void tcg_gen_op1i(int opc, TCGArg arg1) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = arg1; |
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} |
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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} |
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = arg2; |
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} |
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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} |
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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} |
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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} |
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, |
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TCGArg arg4) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = arg3; |
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*gen_opparam_ptr++ = arg4; |
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} |
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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} |
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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} |
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGv arg5, TCGv arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = GET_TCGV(arg5); |
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*gen_opparam_ptr++ = GET_TCGV(arg6); |
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} |
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4, |
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TCGArg arg5, TCGArg arg6) |
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{ |
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*gen_opc_ptr++ = opc; |
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*gen_opparam_ptr++ = GET_TCGV(arg1); |
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*gen_opparam_ptr++ = GET_TCGV(arg2); |
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*gen_opparam_ptr++ = GET_TCGV(arg3); |
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*gen_opparam_ptr++ = GET_TCGV(arg4); |
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*gen_opparam_ptr++ = arg5; |
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*gen_opparam_ptr++ = arg6; |
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} |
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static inline void gen_set_label(int n) |
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{ |
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tcg_gen_op1i(INDEX_op_set_label, n); |
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} |
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg) |
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{ |
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tcg_gen_op2(INDEX_op_mov_i32, ret, arg); |
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} |
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg) |
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{ |
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tcg_gen_op2i(INDEX_op_movi_i32, ret, arg); |
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} |
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0 |
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static inline void tcg_gen_helper_0_0(void *func) |
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{ |
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 0, NULL); |
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} |
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg) |
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{ |
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 1, &arg); |
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} |
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2) |
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{ |
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TCGv args[2];
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args[0] = arg1;
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args[1] = arg2;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 2, args); |
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} |
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2, |
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TCGv arg3, TCGv arg4) |
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{ |
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TCGv args[4];
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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args[3] = arg4;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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0, NULL, 4, args); |
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} |
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret) |
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{ |
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 0, NULL); |
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} |
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1) |
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{ |
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 1, &arg1); |
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} |
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2) |
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{ |
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TCGv args[2];
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args[0] = arg1;
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args[1] = arg2;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 2, args); |
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} |
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret, |
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TCGv arg1, TCGv arg2, TCGv arg3, |
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TCGv arg4) |
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{ |
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TCGv args[4];
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args[0] = arg1;
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args[1] = arg2;
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args[2] = arg3;
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args[3] = arg4;
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tcg_gen_call(&tcg_ctx, |
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tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS, |
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1, &ret, 4, args); |
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} |
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset); |
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} |
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset) |
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{ |
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tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset); |
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} |
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_movi_i32(ret, 0);
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} else if (arg2 == 0xffffffff) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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/* some cases can be optimized here */
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if (arg2 == 0xffffffff) { |
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tcg_gen_movi_i32(ret, 0xffffffff);
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} else if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
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static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2); |
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} |
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static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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/* some cases can be optimized here */
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if (arg2 == 0) { |
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tcg_gen_mov_i32(ret, arg1); |
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} else {
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tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
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} |
367 |
|
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static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2); |
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} |
372 |
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static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
377 |
|
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static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2); |
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} |
382 |
|
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static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2)); |
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} |
387 |
|
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static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2); |
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} |
392 |
|
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static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2) |
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{ |
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tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2)); |
396 |
} |
397 |
|
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static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, |
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int label_index)
|
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{ |
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tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index); |
402 |
} |
403 |
|
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static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2); |
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} |
408 |
|
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#ifdef TCG_TARGET_HAS_div_i32
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static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2); |
413 |
} |
414 |
|
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static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2); |
418 |
} |
419 |
|
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static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
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{ |
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tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2); |
423 |
} |
424 |
|
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static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
426 |
{ |
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tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2); |
428 |
} |
429 |
#else
|
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static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2) |
431 |
{ |
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TCGv t0; |
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t0 = tcg_temp_new(TCG_TYPE_I32); |
434 |
tcg_gen_sari_i32(t0, arg1, 31);
|
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tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2); |
436 |
} |
437 |
|
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static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2) |
439 |
{ |
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TCGv t0; |
441 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
442 |
tcg_gen_sari_i32(t0, arg1, 31);
|
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tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2); |
444 |
} |
445 |
|
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static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
447 |
{ |
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TCGv t0; |
449 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
450 |
tcg_gen_movi_i32(t0, 0);
|
451 |
tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); |
452 |
} |
453 |
|
454 |
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2) |
455 |
{ |
456 |
TCGv t0; |
457 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
458 |
tcg_gen_movi_i32(t0, 0);
|
459 |
tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); |
460 |
} |
461 |
#endif
|
462 |
|
463 |
#if TCG_TARGET_REG_BITS == 32 |
464 |
|
465 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
466 |
{ |
467 |
tcg_gen_mov_i32(ret, arg); |
468 |
tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg)); |
469 |
} |
470 |
|
471 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
472 |
{ |
473 |
tcg_gen_movi_i32(ret, arg); |
474 |
tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
|
475 |
} |
476 |
|
477 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
478 |
{ |
479 |
tcg_gen_ld8u_i32(ret, arg2, offset); |
480 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
481 |
} |
482 |
|
483 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
484 |
{ |
485 |
tcg_gen_ld8s_i32(ret, arg2, offset); |
486 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
487 |
} |
488 |
|
489 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
490 |
{ |
491 |
tcg_gen_ld16u_i32(ret, arg2, offset); |
492 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
493 |
} |
494 |
|
495 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
496 |
{ |
497 |
tcg_gen_ld16s_i32(ret, arg2, offset); |
498 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
499 |
} |
500 |
|
501 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
502 |
{ |
503 |
tcg_gen_ld_i32(ret, arg2, offset); |
504 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
505 |
} |
506 |
|
507 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
508 |
{ |
509 |
tcg_gen_ld_i32(ret, arg2, offset); |
510 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
511 |
} |
512 |
|
513 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
514 |
{ |
515 |
/* since arg2 and ret have different types, they cannot be the
|
516 |
same temporary */
|
517 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
518 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset); |
519 |
tcg_gen_ld_i32(ret, arg2, offset + 4);
|
520 |
#else
|
521 |
tcg_gen_ld_i32(ret, arg2, offset); |
522 |
tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
|
523 |
#endif
|
524 |
} |
525 |
|
526 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
527 |
{ |
528 |
tcg_gen_st8_i32(arg1, arg2, offset); |
529 |
} |
530 |
|
531 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
532 |
{ |
533 |
tcg_gen_st16_i32(arg1, arg2, offset); |
534 |
} |
535 |
|
536 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
537 |
{ |
538 |
tcg_gen_st_i32(arg1, arg2, offset); |
539 |
} |
540 |
|
541 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
542 |
{ |
543 |
#ifdef TCG_TARGET_WORDS_BIGENDIAN
|
544 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset); |
545 |
tcg_gen_st_i32(arg1, arg2, offset + 4);
|
546 |
#else
|
547 |
tcg_gen_st_i32(arg1, arg2, offset); |
548 |
tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
|
549 |
#endif
|
550 |
} |
551 |
|
552 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
553 |
{ |
554 |
tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), |
555 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
556 |
} |
557 |
|
558 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
559 |
{ |
560 |
tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
561 |
} |
562 |
|
563 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
564 |
{ |
565 |
tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), |
566 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2)); |
567 |
} |
568 |
|
569 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
570 |
{ |
571 |
tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
572 |
} |
573 |
|
574 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
575 |
{ |
576 |
tcg_gen_and_i32(ret, arg1, arg2); |
577 |
tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
578 |
} |
579 |
|
580 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
581 |
{ |
582 |
tcg_gen_andi_i32(ret, arg1, arg2); |
583 |
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
584 |
} |
585 |
|
586 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
587 |
{ |
588 |
tcg_gen_or_i32(ret, arg1, arg2); |
589 |
tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
590 |
} |
591 |
|
592 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
593 |
{ |
594 |
tcg_gen_ori_i32(ret, arg1, arg2); |
595 |
tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
596 |
} |
597 |
|
598 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
599 |
{ |
600 |
tcg_gen_xor_i32(ret, arg1, arg2); |
601 |
tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2)); |
602 |
} |
603 |
|
604 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
605 |
{ |
606 |
tcg_gen_xori_i32(ret, arg1, arg2); |
607 |
tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
|
608 |
} |
609 |
|
610 |
/* XXX: use generic code when basic block handling is OK or CPU
|
611 |
specific code (x86) */
|
612 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
613 |
{ |
614 |
tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2); |
615 |
} |
616 |
|
617 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
618 |
{ |
619 |
tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0); |
620 |
} |
621 |
|
622 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
623 |
{ |
624 |
tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2); |
625 |
} |
626 |
|
627 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
628 |
{ |
629 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0); |
630 |
} |
631 |
|
632 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
633 |
{ |
634 |
tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2); |
635 |
} |
636 |
|
637 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
638 |
{ |
639 |
tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1); |
640 |
} |
641 |
|
642 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
643 |
int label_index)
|
644 |
{ |
645 |
tcg_gen_op6ii(INDEX_op_brcond2_i32, |
646 |
arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2), |
647 |
cond, label_index); |
648 |
} |
649 |
|
650 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
651 |
{ |
652 |
TCGv t0, t1; |
653 |
|
654 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
655 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
656 |
|
657 |
tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2); |
658 |
|
659 |
tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2)); |
660 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
661 |
tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2); |
662 |
tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1); |
663 |
|
664 |
tcg_gen_mov_i64(ret, t0); |
665 |
} |
666 |
|
667 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
668 |
{ |
669 |
tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2); |
670 |
} |
671 |
|
672 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
673 |
{ |
674 |
tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2); |
675 |
} |
676 |
|
677 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
678 |
{ |
679 |
tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2); |
680 |
} |
681 |
|
682 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
683 |
{ |
684 |
tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2); |
685 |
} |
686 |
|
687 |
#else
|
688 |
|
689 |
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg) |
690 |
{ |
691 |
tcg_gen_op2(INDEX_op_mov_i64, ret, arg); |
692 |
} |
693 |
|
694 |
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg) |
695 |
{ |
696 |
tcg_gen_op2i(INDEX_op_movi_i64, ret, arg); |
697 |
} |
698 |
|
699 |
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, |
700 |
tcg_target_long offset) |
701 |
{ |
702 |
tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset); |
703 |
} |
704 |
|
705 |
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, |
706 |
tcg_target_long offset) |
707 |
{ |
708 |
tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset); |
709 |
} |
710 |
|
711 |
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, |
712 |
tcg_target_long offset) |
713 |
{ |
714 |
tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset); |
715 |
} |
716 |
|
717 |
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, |
718 |
tcg_target_long offset) |
719 |
{ |
720 |
tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset); |
721 |
} |
722 |
|
723 |
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, |
724 |
tcg_target_long offset) |
725 |
{ |
726 |
tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset); |
727 |
} |
728 |
|
729 |
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, |
730 |
tcg_target_long offset) |
731 |
{ |
732 |
tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset); |
733 |
} |
734 |
|
735 |
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset) |
736 |
{ |
737 |
tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset); |
738 |
} |
739 |
|
740 |
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, |
741 |
tcg_target_long offset) |
742 |
{ |
743 |
tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset); |
744 |
} |
745 |
|
746 |
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, |
747 |
tcg_target_long offset) |
748 |
{ |
749 |
tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset); |
750 |
} |
751 |
|
752 |
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, |
753 |
tcg_target_long offset) |
754 |
{ |
755 |
tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset); |
756 |
} |
757 |
|
758 |
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset) |
759 |
{ |
760 |
tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset); |
761 |
} |
762 |
|
763 |
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2) |
764 |
{ |
765 |
tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2); |
766 |
} |
767 |
|
768 |
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
769 |
{ |
770 |
tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2)); |
771 |
} |
772 |
|
773 |
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2) |
774 |
{ |
775 |
tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2); |
776 |
} |
777 |
|
778 |
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
779 |
{ |
780 |
tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2)); |
781 |
} |
782 |
|
783 |
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2) |
784 |
{ |
785 |
tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2); |
786 |
} |
787 |
|
788 |
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2) |
789 |
{ |
790 |
tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2)); |
791 |
} |
792 |
|
793 |
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2) |
794 |
{ |
795 |
tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2); |
796 |
} |
797 |
|
798 |
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
799 |
{ |
800 |
tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2)); |
801 |
} |
802 |
|
803 |
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2) |
804 |
{ |
805 |
tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2); |
806 |
} |
807 |
|
808 |
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2) |
809 |
{ |
810 |
tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2)); |
811 |
} |
812 |
|
813 |
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2) |
814 |
{ |
815 |
tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2); |
816 |
} |
817 |
|
818 |
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2) |
819 |
{ |
820 |
tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2)); |
821 |
} |
822 |
|
823 |
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2) |
824 |
{ |
825 |
tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2); |
826 |
} |
827 |
|
828 |
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2) |
829 |
{ |
830 |
tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2)); |
831 |
} |
832 |
|
833 |
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2) |
834 |
{ |
835 |
tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2); |
836 |
} |
837 |
|
838 |
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2) |
839 |
{ |
840 |
tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2)); |
841 |
} |
842 |
|
843 |
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, |
844 |
int label_index)
|
845 |
{ |
846 |
tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index); |
847 |
} |
848 |
|
849 |
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2) |
850 |
{ |
851 |
tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2); |
852 |
} |
853 |
|
854 |
#ifdef TCG_TARGET_HAS_div_i64
|
855 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
856 |
{ |
857 |
tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2); |
858 |
} |
859 |
|
860 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
861 |
{ |
862 |
tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2); |
863 |
} |
864 |
|
865 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
866 |
{ |
867 |
tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2); |
868 |
} |
869 |
|
870 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
871 |
{ |
872 |
tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2); |
873 |
} |
874 |
#else
|
875 |
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2) |
876 |
{ |
877 |
TCGv t0; |
878 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
879 |
tcg_gen_sari_i64(t0, arg1, 63);
|
880 |
tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2); |
881 |
} |
882 |
|
883 |
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2) |
884 |
{ |
885 |
TCGv t0; |
886 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
887 |
tcg_gen_sari_i64(t0, arg1, 63);
|
888 |
tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2); |
889 |
} |
890 |
|
891 |
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
892 |
{ |
893 |
TCGv t0; |
894 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
895 |
tcg_gen_movi_i64(t0, 0);
|
896 |
tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); |
897 |
} |
898 |
|
899 |
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2) |
900 |
{ |
901 |
TCGv t0; |
902 |
t0 = tcg_temp_new(TCG_TYPE_I64); |
903 |
tcg_gen_movi_i64(t0, 0);
|
904 |
tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); |
905 |
} |
906 |
#endif
|
907 |
|
908 |
#endif
|
909 |
|
910 |
/***************************************/
|
911 |
/* optional operations */
|
912 |
|
913 |
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg) |
914 |
{ |
915 |
#ifdef TCG_TARGET_HAS_ext8s_i32
|
916 |
tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg); |
917 |
#else
|
918 |
tcg_gen_shli_i32(ret, arg, 24);
|
919 |
tcg_gen_sari_i32(ret, ret, 24);
|
920 |
#endif
|
921 |
} |
922 |
|
923 |
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg) |
924 |
{ |
925 |
#ifdef TCG_TARGET_HAS_ext16s_i32
|
926 |
tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg); |
927 |
#else
|
928 |
tcg_gen_shli_i32(ret, arg, 16);
|
929 |
tcg_gen_sari_i32(ret, ret, 16);
|
930 |
#endif
|
931 |
} |
932 |
|
933 |
/* Note: we assume the two high bytes are set to zero */
|
934 |
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg) |
935 |
{ |
936 |
#ifdef TCG_TARGET_HAS_bswap16_i32
|
937 |
tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg); |
938 |
#else
|
939 |
TCGv t0, t1; |
940 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
941 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
942 |
|
943 |
tcg_gen_shri_i32(t0, arg, 8);
|
944 |
tcg_gen_andi_i32(t1, arg, 0x000000ff);
|
945 |
tcg_gen_shli_i32(t1, t1, 8);
|
946 |
tcg_gen_or_i32(ret, t0, t1); |
947 |
#endif
|
948 |
} |
949 |
|
950 |
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg) |
951 |
{ |
952 |
#ifdef TCG_TARGET_HAS_bswap_i32
|
953 |
tcg_gen_op2(INDEX_op_bswap_i32, ret, arg); |
954 |
#else
|
955 |
TCGv t0, t1; |
956 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
957 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
958 |
|
959 |
tcg_gen_shli_i32(t0, arg, 24);
|
960 |
|
961 |
tcg_gen_andi_i32(t1, arg, 0x0000ff00);
|
962 |
tcg_gen_shli_i32(t1, t1, 8);
|
963 |
tcg_gen_or_i32(t0, t0, t1); |
964 |
|
965 |
tcg_gen_shri_i32(t1, arg, 8);
|
966 |
tcg_gen_andi_i32(t1, t1, 0x0000ff00);
|
967 |
tcg_gen_or_i32(t0, t0, t1); |
968 |
|
969 |
tcg_gen_shri_i32(t1, arg, 24);
|
970 |
tcg_gen_or_i32(ret, t0, t1); |
971 |
#endif
|
972 |
} |
973 |
|
974 |
#if TCG_TARGET_REG_BITS == 32 |
975 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
976 |
{ |
977 |
tcg_gen_ext8s_i32(ret, arg); |
978 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
979 |
} |
980 |
|
981 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
982 |
{ |
983 |
tcg_gen_ext16s_i32(ret, arg); |
984 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
985 |
} |
986 |
|
987 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
988 |
{ |
989 |
tcg_gen_mov_i32(ret, arg); |
990 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
991 |
} |
992 |
|
993 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
994 |
{ |
995 |
tcg_gen_mov_i32(ret, arg); |
996 |
} |
997 |
|
998 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
999 |
{ |
1000 |
tcg_gen_mov_i32(ret, arg); |
1001 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1002 |
} |
1003 |
|
1004 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
1005 |
{ |
1006 |
tcg_gen_mov_i32(ret, arg); |
1007 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1008 |
} |
1009 |
|
1010 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
1011 |
{ |
1012 |
TCGv t0, t1; |
1013 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
1014 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
1015 |
|
1016 |
tcg_gen_bswap_i32(t0, arg); |
1017 |
tcg_gen_bswap_i32(t1, TCGV_HIGH(arg)); |
1018 |
tcg_gen_mov_i32(ret, t1); |
1019 |
tcg_gen_mov_i32(TCGV_HIGH(ret), t0); |
1020 |
} |
1021 |
#else
|
1022 |
|
1023 |
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg) |
1024 |
{ |
1025 |
#ifdef TCG_TARGET_HAS_ext8s_i64
|
1026 |
tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg); |
1027 |
#else
|
1028 |
tcg_gen_shli_i64(ret, arg, 56);
|
1029 |
tcg_gen_sari_i64(ret, ret, 56);
|
1030 |
#endif
|
1031 |
} |
1032 |
|
1033 |
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg) |
1034 |
{ |
1035 |
#ifdef TCG_TARGET_HAS_ext16s_i64
|
1036 |
tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg); |
1037 |
#else
|
1038 |
tcg_gen_shli_i64(ret, arg, 48);
|
1039 |
tcg_gen_sari_i64(ret, ret, 48);
|
1040 |
#endif
|
1041 |
} |
1042 |
|
1043 |
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) |
1044 |
{ |
1045 |
#ifdef TCG_TARGET_HAS_ext32s_i64
|
1046 |
tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg); |
1047 |
#else
|
1048 |
tcg_gen_shli_i64(ret, arg, 32);
|
1049 |
tcg_gen_sari_i64(ret, ret, 32);
|
1050 |
#endif
|
1051 |
} |
1052 |
|
1053 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1054 |
registers. This will probably break MIPS64 targets. */
|
1055 |
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) |
1056 |
{ |
1057 |
tcg_gen_mov_i32(ret, arg); |
1058 |
} |
1059 |
|
1060 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1061 |
registers */
|
1062 |
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) |
1063 |
{ |
1064 |
tcg_gen_andi_i64(ret, arg, 0xffffffff);
|
1065 |
} |
1066 |
|
1067 |
/* Note: we assume the target supports move between 32 and 64 bit
|
1068 |
registers */
|
1069 |
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg) |
1070 |
{ |
1071 |
tcg_gen_ext32s_i64(ret, arg); |
1072 |
} |
1073 |
|
1074 |
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg) |
1075 |
{ |
1076 |
#ifdef TCG_TARGET_HAS_bswap_i64
|
1077 |
tcg_gen_op2(INDEX_op_bswap_i64, ret, arg); |
1078 |
#else
|
1079 |
TCGv t0, t1; |
1080 |
t0 = tcg_temp_new(TCG_TYPE_I32); |
1081 |
t1 = tcg_temp_new(TCG_TYPE_I32); |
1082 |
|
1083 |
tcg_gen_shli_i64(t0, arg, 56);
|
1084 |
|
1085 |
tcg_gen_andi_i64(t1, arg, 0x0000ff00);
|
1086 |
tcg_gen_shli_i64(t1, t1, 40);
|
1087 |
tcg_gen_or_i64(t0, t0, t1); |
1088 |
|
1089 |
tcg_gen_andi_i64(t1, arg, 0x00ff0000);
|
1090 |
tcg_gen_shli_i64(t1, t1, 24);
|
1091 |
tcg_gen_or_i64(t0, t0, t1); |
1092 |
|
1093 |
tcg_gen_andi_i64(t1, arg, 0xff000000);
|
1094 |
tcg_gen_shli_i64(t1, t1, 8);
|
1095 |
tcg_gen_or_i64(t0, t0, t1); |
1096 |
|
1097 |
tcg_gen_shri_i64(t1, arg, 8);
|
1098 |
tcg_gen_andi_i64(t1, t1, 0xff000000);
|
1099 |
tcg_gen_or_i64(t0, t0, t1); |
1100 |
|
1101 |
tcg_gen_shri_i64(t1, arg, 24);
|
1102 |
tcg_gen_andi_i64(t1, t1, 0x00ff0000);
|
1103 |
tcg_gen_or_i64(t0, t0, t1); |
1104 |
|
1105 |
tcg_gen_shri_i64(t1, arg, 40);
|
1106 |
tcg_gen_andi_i64(t1, t1, 0x0000ff00);
|
1107 |
tcg_gen_or_i64(t0, t0, t1); |
1108 |
|
1109 |
tcg_gen_shri_i64(t1, arg, 56);
|
1110 |
tcg_gen_or_i64(ret, t0, t1); |
1111 |
#endif
|
1112 |
} |
1113 |
|
1114 |
#endif
|
1115 |
|
1116 |
|
1117 |
static inline void tcg_gen_discard_i32(TCGv arg) |
1118 |
{ |
1119 |
tcg_gen_op1(INDEX_op_discard, arg); |
1120 |
} |
1121 |
|
1122 |
#if TCG_TARGET_REG_BITS == 32 |
1123 |
static inline void tcg_gen_discard_i64(TCGv arg) |
1124 |
{ |
1125 |
tcg_gen_discard_i32(arg); |
1126 |
tcg_gen_discard_i32(TCGV_HIGH(arg)); |
1127 |
} |
1128 |
#else
|
1129 |
static inline void tcg_gen_discard_i64(TCGv arg) |
1130 |
{ |
1131 |
tcg_gen_op1(INDEX_op_discard, arg); |
1132 |
} |
1133 |
#endif
|
1134 |
|
1135 |
/***************************************/
|
1136 |
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id) |
1137 |
{ |
1138 |
tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id); |
1139 |
} |
1140 |
|
1141 |
/***************************************/
|
1142 |
/* QEMU specific operations. Their type depend on the QEMU CPU
|
1143 |
type. */
|
1144 |
#ifndef TARGET_LONG_BITS
|
1145 |
#error must include QEMU headers
|
1146 |
#endif
|
1147 |
|
1148 |
static inline void tcg_gen_exit_tb(tcg_target_long val) |
1149 |
{ |
1150 |
tcg_gen_op1i(INDEX_op_exit_tb, val); |
1151 |
} |
1152 |
|
1153 |
static inline void tcg_gen_goto_tb(int idx) |
1154 |
{ |
1155 |
tcg_gen_op1i(INDEX_op_goto_tb, idx); |
1156 |
} |
1157 |
|
1158 |
#if TCG_TARGET_REG_BITS == 32 |
1159 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
1160 |
{ |
1161 |
#if TARGET_LONG_BITS == 32 |
1162 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1163 |
#else
|
1164 |
tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index); |
1165 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1166 |
#endif
|
1167 |
} |
1168 |
|
1169 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
1170 |
{ |
1171 |
#if TARGET_LONG_BITS == 32 |
1172 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1173 |
#else
|
1174 |
tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index); |
1175 |
tcg_gen_ext8s_i32(TCGV_HIGH(ret), ret); |
1176 |
#endif
|
1177 |
} |
1178 |
|
1179 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
1180 |
{ |
1181 |
#if TARGET_LONG_BITS == 32 |
1182 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1183 |
#else
|
1184 |
tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index); |
1185 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1186 |
#endif
|
1187 |
} |
1188 |
|
1189 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
1190 |
{ |
1191 |
#if TARGET_LONG_BITS == 32 |
1192 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1193 |
#else
|
1194 |
tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index); |
1195 |
tcg_gen_ext16s_i32(TCGV_HIGH(ret), ret); |
1196 |
#endif
|
1197 |
} |
1198 |
|
1199 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
1200 |
{ |
1201 |
#if TARGET_LONG_BITS == 32 |
1202 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1203 |
#else
|
1204 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
1205 |
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
|
1206 |
#endif
|
1207 |
} |
1208 |
|
1209 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
1210 |
{ |
1211 |
#if TARGET_LONG_BITS == 32 |
1212 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1213 |
#else
|
1214 |
tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index); |
1215 |
tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
|
1216 |
#endif
|
1217 |
} |
1218 |
|
1219 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
1220 |
{ |
1221 |
#if TARGET_LONG_BITS == 32 |
1222 |
tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index); |
1223 |
#else
|
1224 |
tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), |
1225 |
addr, TCGV_HIGH(addr), mem_index); |
1226 |
#endif
|
1227 |
} |
1228 |
|
1229 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
1230 |
{ |
1231 |
#if TARGET_LONG_BITS == 32 |
1232 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
1233 |
#else
|
1234 |
tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index); |
1235 |
#endif
|
1236 |
} |
1237 |
|
1238 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
1239 |
{ |
1240 |
#if TARGET_LONG_BITS == 32 |
1241 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
1242 |
#else
|
1243 |
tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index); |
1244 |
#endif
|
1245 |
} |
1246 |
|
1247 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
1248 |
{ |
1249 |
#if TARGET_LONG_BITS == 32 |
1250 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
1251 |
#else
|
1252 |
tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index); |
1253 |
#endif
|
1254 |
} |
1255 |
|
1256 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
1257 |
{ |
1258 |
#if TARGET_LONG_BITS == 32 |
1259 |
tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index); |
1260 |
#else
|
1261 |
tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), |
1262 |
addr, TCGV_HIGH(addr), mem_index); |
1263 |
#endif
|
1264 |
} |
1265 |
|
1266 |
#define tcg_gen_ld_ptr tcg_gen_ld_i32
|
1267 |
|
1268 |
#else /* TCG_TARGET_REG_BITS == 32 */ |
1269 |
|
1270 |
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
1271 |
{ |
1272 |
tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index); |
1273 |
} |
1274 |
|
1275 |
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
1276 |
{ |
1277 |
tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index); |
1278 |
} |
1279 |
|
1280 |
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
1281 |
{ |
1282 |
tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index); |
1283 |
} |
1284 |
|
1285 |
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
1286 |
{ |
1287 |
tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index); |
1288 |
} |
1289 |
|
1290 |
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
1291 |
{ |
1292 |
tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index); |
1293 |
} |
1294 |
|
1295 |
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
1296 |
{ |
1297 |
tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index); |
1298 |
} |
1299 |
|
1300 |
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index) |
1301 |
{ |
1302 |
tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index); |
1303 |
} |
1304 |
|
1305 |
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
1306 |
{ |
1307 |
tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index); |
1308 |
} |
1309 |
|
1310 |
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
1311 |
{ |
1312 |
tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index); |
1313 |
} |
1314 |
|
1315 |
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
1316 |
{ |
1317 |
tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index); |
1318 |
} |
1319 |
|
1320 |
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index) |
1321 |
{ |
1322 |
tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index); |
1323 |
} |
1324 |
|
1325 |
#define tcg_gen_ld_ptr tcg_gen_ld_i64
|
1326 |
|
1327 |
#endif /* TCG_TARGET_REG_BITS != 32 */ |
1328 |
|
1329 |
#if TARGET_LONG_BITS == 64 |
1330 |
#define TCG_TYPE_TL TCG_TYPE_I64
|
1331 |
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
1332 |
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
1333 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
|
1334 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
|
1335 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
|
1336 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
|
1337 |
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
|
1338 |
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
|
1339 |
#define tcg_gen_ld_tl tcg_gen_ld_i64
|
1340 |
#define tcg_gen_st8_tl tcg_gen_st8_i64
|
1341 |
#define tcg_gen_st16_tl tcg_gen_st16_i64
|
1342 |
#define tcg_gen_st32_tl tcg_gen_st32_i64
|
1343 |
#define tcg_gen_st_tl tcg_gen_st_i64
|
1344 |
#define tcg_gen_add_tl tcg_gen_add_i64
|
1345 |
#define tcg_gen_addi_tl tcg_gen_addi_i64
|
1346 |
#define tcg_gen_sub_tl tcg_gen_sub_i64
|
1347 |
#define tcg_gen_subi_tl tcg_gen_subi_i64
|
1348 |
#define tcg_gen_and_tl tcg_gen_and_i64
|
1349 |
#define tcg_gen_andi_tl tcg_gen_andi_i64
|
1350 |
#define tcg_gen_or_tl tcg_gen_or_i64
|
1351 |
#define tcg_gen_ori_tl tcg_gen_ori_i64
|
1352 |
#define tcg_gen_xor_tl tcg_gen_xor_i64
|
1353 |
#define tcg_gen_xori_tl tcg_gen_xori_i64
|
1354 |
#define tcg_gen_shl_tl tcg_gen_shl_i64
|
1355 |
#define tcg_gen_shli_tl tcg_gen_shli_i64
|
1356 |
#define tcg_gen_shr_tl tcg_gen_shr_i64
|
1357 |
#define tcg_gen_shri_tl tcg_gen_shri_i64
|
1358 |
#define tcg_gen_sar_tl tcg_gen_sar_i64
|
1359 |
#define tcg_gen_sari_tl tcg_gen_sari_i64
|
1360 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
|
1361 |
#else
|
1362 |
#define TCG_TYPE_TL TCG_TYPE_I32
|
1363 |
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
1364 |
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
1365 |
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
|
1366 |
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
|
1367 |
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
|
1368 |
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
|
1369 |
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
|
1370 |
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
|
1371 |
#define tcg_gen_ld_tl tcg_gen_ld_i32
|
1372 |
#define tcg_gen_st8_tl tcg_gen_st8_i32
|
1373 |
#define tcg_gen_st16_tl tcg_gen_st16_i32
|
1374 |
#define tcg_gen_st32_tl tcg_gen_st_i32
|
1375 |
#define tcg_gen_st_tl tcg_gen_st_i32
|
1376 |
#define tcg_gen_add_tl tcg_gen_add_i32
|
1377 |
#define tcg_gen_addi_tl tcg_gen_addi_i32
|
1378 |
#define tcg_gen_sub_tl tcg_gen_sub_i32
|
1379 |
#define tcg_gen_subi_tl tcg_gen_subi_i32
|
1380 |
#define tcg_gen_and_tl tcg_gen_and_i32
|
1381 |
#define tcg_gen_andi_tl tcg_gen_andi_i32
|
1382 |
#define tcg_gen_or_tl tcg_gen_or_i32
|
1383 |
#define tcg_gen_ori_tl tcg_gen_ori_i32
|
1384 |
#define tcg_gen_xor_tl tcg_gen_xor_i32
|
1385 |
#define tcg_gen_xori_tl tcg_gen_xori_i32
|
1386 |
#define tcg_gen_shl_tl tcg_gen_shl_i32
|
1387 |
#define tcg_gen_shli_tl tcg_gen_shli_i32
|
1388 |
#define tcg_gen_shr_tl tcg_gen_shr_i32
|
1389 |
#define tcg_gen_shri_tl tcg_gen_shri_i32
|
1390 |
#define tcg_gen_sar_tl tcg_gen_sar_i32
|
1391 |
#define tcg_gen_sari_tl tcg_gen_sari_i32
|
1392 |
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
|
1393 |
#endif
|