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1 | c3d2689d | balrog | /*
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2 | c3d2689d | balrog | * Texas Instruments OMAP processors.
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3 | c3d2689d | balrog | *
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4 | b4e3104b | balrog | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
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5 | c3d2689d | balrog | *
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6 | c3d2689d | balrog | * This program is free software; you can redistribute it and/or
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7 | c3d2689d | balrog | * modify it under the terms of the GNU General Public License as
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8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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10 | c3d2689d | balrog | *
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11 | c3d2689d | balrog | * This program is distributed in the hope that it will be useful,
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12 | c3d2689d | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | c3d2689d | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | c3d2689d | balrog | * GNU General Public License for more details.
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15 | c3d2689d | balrog | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | c3d2689d | balrog | */
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19 | c3d2689d | balrog | #ifndef hw_omap_h
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20 | 64066a8f | Avi Kivity | #include "memory.h" |
21 | c3d2689d | balrog | # define hw_omap_h "omap.h" |
22 | c3d2689d | balrog | |
23 | c3d2689d | balrog | # define OMAP_EMIFS_BASE 0x00000000 |
24 | 827df9f3 | balrog | # define OMAP2_Q0_BASE 0x00000000 |
25 | c3d2689d | balrog | # define OMAP_CS0_BASE 0x00000000 |
26 | c3d2689d | balrog | # define OMAP_CS1_BASE 0x04000000 |
27 | c3d2689d | balrog | # define OMAP_CS2_BASE 0x08000000 |
28 | c3d2689d | balrog | # define OMAP_CS3_BASE 0x0c000000 |
29 | c3d2689d | balrog | # define OMAP_EMIFF_BASE 0x10000000 |
30 | c3d2689d | balrog | # define OMAP_IMIF_BASE 0x20000000 |
31 | c3d2689d | balrog | # define OMAP_LOCALBUS_BASE 0x30000000 |
32 | 827df9f3 | balrog | # define OMAP2_Q1_BASE 0x40000000 |
33 | 827df9f3 | balrog | # define OMAP2_L4_BASE 0x48000000 |
34 | 827df9f3 | balrog | # define OMAP2_SRAM_BASE 0x40200000 |
35 | 827df9f3 | balrog | # define OMAP2_L3_BASE 0x68000000 |
36 | 827df9f3 | balrog | # define OMAP2_Q2_BASE 0x80000000 |
37 | 827df9f3 | balrog | # define OMAP2_Q3_BASE 0xc0000000 |
38 | c3d2689d | balrog | # define OMAP_MPUI_BASE 0xe1000000 |
39 | c3d2689d | balrog | |
40 | c3d2689d | balrog | # define OMAP730_SRAM_SIZE 0x00032000 |
41 | c3d2689d | balrog | # define OMAP15XX_SRAM_SIZE 0x00030000 |
42 | c3d2689d | balrog | # define OMAP16XX_SRAM_SIZE 0x00004000 |
43 | c3d2689d | balrog | # define OMAP1611_SRAM_SIZE 0x0003e800 |
44 | 827df9f3 | balrog | # define OMAP242X_SRAM_SIZE 0x000a0000 |
45 | 827df9f3 | balrog | # define OMAP243X_SRAM_SIZE 0x00010000 |
46 | c3d2689d | balrog | # define OMAP_CS0_SIZE 0x04000000 |
47 | c3d2689d | balrog | # define OMAP_CS1_SIZE 0x04000000 |
48 | c3d2689d | balrog | # define OMAP_CS2_SIZE 0x04000000 |
49 | c3d2689d | balrog | # define OMAP_CS3_SIZE 0x04000000 |
50 | c3d2689d | balrog | |
51 | 827df9f3 | balrog | /* omap_clk.c */
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52 | c3d2689d | balrog | struct omap_mpu_state_s;
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53 | c3d2689d | balrog | typedef struct clk *omap_clk; |
54 | c3d2689d | balrog | omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
55 | c3d2689d | balrog | void omap_clk_init(struct omap_mpu_state_s *mpu); |
56 | c3d2689d | balrog | void omap_clk_adduser(struct clk *clk, qemu_irq user); |
57 | c3d2689d | balrog | void omap_clk_get(omap_clk clk);
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58 | c3d2689d | balrog | void omap_clk_put(omap_clk clk);
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59 | c3d2689d | balrog | void omap_clk_onoff(omap_clk clk, int on); |
60 | c3d2689d | balrog | void omap_clk_canidle(omap_clk clk, int can); |
61 | c3d2689d | balrog | void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
62 | c3d2689d | balrog | int64_t omap_clk_getrate(omap_clk clk); |
63 | c3d2689d | balrog | void omap_clk_reparent(omap_clk clk, omap_clk parent);
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64 | c3d2689d | balrog | |
65 | 2c1d9ecb | cmchao | /* OMAP2 l4 Interconnect */
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66 | 827df9f3 | balrog | struct omap_l4_s;
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67 | 2c1d9ecb | cmchao | struct omap_l4_region_s {
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68 | 2c1d9ecb | cmchao | target_phys_addr_t offset; |
69 | 2c1d9ecb | cmchao | size_t size; |
70 | 2c1d9ecb | cmchao | int access;
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71 | 2c1d9ecb | cmchao | }; |
72 | 2c1d9ecb | cmchao | struct omap_l4_agent_info_s {
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73 | 2c1d9ecb | cmchao | int ta;
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74 | 2c1d9ecb | cmchao | int region;
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75 | 2c1d9ecb | cmchao | int regions;
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76 | 2c1d9ecb | cmchao | int ta_region;
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77 | 2c1d9ecb | cmchao | }; |
78 | 2c1d9ecb | cmchao | struct omap_target_agent_s {
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79 | 2c1d9ecb | cmchao | struct omap_l4_s *bus;
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80 | 2c1d9ecb | cmchao | int regions;
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81 | 2c1d9ecb | cmchao | const struct omap_l4_region_s *start; |
82 | 2c1d9ecb | cmchao | target_phys_addr_t base; |
83 | 2c1d9ecb | cmchao | uint32_t component; |
84 | 2c1d9ecb | cmchao | uint32_t control; |
85 | 2c1d9ecb | cmchao | uint32_t status; |
86 | 2c1d9ecb | cmchao | }; |
87 | c227f099 | Anthony Liguori | struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); |
88 | 827df9f3 | balrog | |
89 | 827df9f3 | balrog | struct omap_target_agent_s;
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90 | 2c1d9ecb | cmchao | struct omap_target_agent_s *omap_l4ta_get(
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91 | 2c1d9ecb | cmchao | struct omap_l4_s *bus,
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92 | 2c1d9ecb | cmchao | const struct omap_l4_region_s *regions, |
93 | 2c1d9ecb | cmchao | const struct omap_l4_agent_info_s *agents, |
94 | 2c1d9ecb | cmchao | int cs);
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95 | c227f099 | Anthony Liguori | target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
96 | 827df9f3 | balrog | int iotype);
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97 | f9049203 | Juha Riihimäki | target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
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98 | f9049203 | Juha Riihimäki | int region);
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99 | 2c1d9ecb | cmchao | int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
100 | 2c1d9ecb | cmchao | CPUWriteMemoryFunc * const *mem_write, void *opaque); |
101 | 827df9f3 | balrog | |
102 | 7f132a21 | cmchao | /* OMAP interrupt controller */
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103 | c3d2689d | balrog | struct omap_intr_handler_s;
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104 | c227f099 | Anthony Liguori | struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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105 | 827df9f3 | balrog | unsigned long size, unsigned char nbanks, qemu_irq **pins, |
106 | 106627d0 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
107 | c227f099 | Anthony Liguori | struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
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108 | 827df9f3 | balrog | int size, int nbanks, qemu_irq **pins, |
109 | 827df9f3 | balrog | qemu_irq parent_irq, qemu_irq parent_fiq, |
110 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk); |
111 | 827df9f3 | balrog | void omap_inth_reset(struct omap_intr_handler_s *s); |
112 | 7f132a21 | cmchao | qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n); |
113 | 827df9f3 | balrog | |
114 | 0bf43016 | cmchao | /* OMAP2 SDRAM controller */
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115 | 827df9f3 | balrog | struct omap_sdrc_s;
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116 | c227f099 | Anthony Liguori | struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
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117 | 0bf43016 | cmchao | void omap_sdrc_reset(struct omap_sdrc_s *s); |
118 | 827df9f3 | balrog | |
119 | f3354b0e | cmchao | /* OMAP2 general purpose memory controller */
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120 | 827df9f3 | balrog | struct omap_gpmc_s;
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121 | c227f099 | Anthony Liguori | struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
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122 | f3354b0e | cmchao | void omap_gpmc_reset(struct omap_gpmc_s *s); |
123 | 64066a8f | Avi Kivity | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem, |
124 | c227f099 | Anthony Liguori | void (*base_upd)(void *opaque, target_phys_addr_t new), |
125 | 827df9f3 | balrog | void (*unmap)(void *opaque), void *opaque); |
126 | 29885477 | balrog | |
127 | c3d2689d | balrog | /*
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128 | c3d2689d | balrog | * Common IRQ numbers for level 1 interrupt handler
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129 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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130 | c3d2689d | balrog | */
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131 | c3d2689d | balrog | # define OMAP_INT_CAMERA 1 |
132 | c3d2689d | balrog | # define OMAP_INT_FIQ 3 |
133 | c3d2689d | balrog | # define OMAP_INT_RTDX 6 |
134 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU_ABORT 7 |
135 | c3d2689d | balrog | # define OMAP_INT_HOST 8 |
136 | c3d2689d | balrog | # define OMAP_INT_ABORT 9 |
137 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PRIV 13 |
138 | c3d2689d | balrog | # define OMAP_INT_GPIO_BANK1 14 |
139 | c3d2689d | balrog | # define OMAP_INT_UART3 15 |
140 | c3d2689d | balrog | # define OMAP_INT_TIMER3 16 |
141 | c3d2689d | balrog | # define OMAP_INT_DMA_CH0_6 19 |
142 | c3d2689d | balrog | # define OMAP_INT_DMA_CH1_7 20 |
143 | c3d2689d | balrog | # define OMAP_INT_DMA_CH2_8 21 |
144 | c3d2689d | balrog | # define OMAP_INT_DMA_CH3 22 |
145 | c3d2689d | balrog | # define OMAP_INT_DMA_CH4 23 |
146 | c3d2689d | balrog | # define OMAP_INT_DMA_CH5 24 |
147 | c3d2689d | balrog | # define OMAP_INT_DMA_LCD 25 |
148 | c3d2689d | balrog | # define OMAP_INT_TIMER1 26 |
149 | c3d2689d | balrog | # define OMAP_INT_WD_TIMER 27 |
150 | c3d2689d | balrog | # define OMAP_INT_BRIDGE_PUB 28 |
151 | c3d2689d | balrog | # define OMAP_INT_TIMER2 30 |
152 | c3d2689d | balrog | # define OMAP_INT_LCD_CTRL 31 |
153 | c3d2689d | balrog | |
154 | c3d2689d | balrog | /*
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155 | c3d2689d | balrog | * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
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156 | c3d2689d | balrog | */
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157 | c3d2689d | balrog | # define OMAP_INT_15XX_IH2_IRQ 0 |
158 | c3d2689d | balrog | # define OMAP_INT_15XX_LB_MMU 17 |
159 | c3d2689d | balrog | # define OMAP_INT_15XX_LOCAL_BUS 29 |
160 | c3d2689d | balrog | |
161 | c3d2689d | balrog | /*
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162 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
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163 | c3d2689d | balrog | */
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164 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_TX 4 |
165 | c3d2689d | balrog | # define OMAP_INT_1510_SPI_RX 5 |
166 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX1 10 |
167 | c3d2689d | balrog | # define OMAP_INT_1510_DSP_MAILBOX2 11 |
168 | c3d2689d | balrog | |
169 | c3d2689d | balrog | /*
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170 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 1 interrupt handler
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171 | c3d2689d | balrog | */
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172 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_TX 4 |
173 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2_RX 5 |
174 | c3d2689d | balrog | # define OMAP_INT_310_HSB_MAILBOX1 12 |
175 | c3d2689d | balrog | # define OMAP_INT_310_HSAB_MMU 18 |
176 | c3d2689d | balrog | |
177 | c3d2689d | balrog | /*
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178 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
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179 | c3d2689d | balrog | */
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180 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_IRQ 0 |
181 | c3d2689d | balrog | # define OMAP_INT_1610_IH2_FIQ 2 |
182 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_TX 4 |
183 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2_RX 5 |
184 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX1 10 |
185 | c3d2689d | balrog | # define OMAP_INT_1610_DSP_MAILBOX2 11 |
186 | c3d2689d | balrog | # define OMAP_INT_1610_LCD_LINE 12 |
187 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER1 17 |
188 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER2 18 |
189 | c3d2689d | balrog | # define OMAP_INT_1610_SSR_FIFO_0 29 |
190 | c3d2689d | balrog | |
191 | c3d2689d | balrog | /*
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192 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 1 interrupt handler
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193 | c3d2689d | balrog | */
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194 | c3d2689d | balrog | # define OMAP_INT_730_IH2_FIQ 0 |
195 | c3d2689d | balrog | # define OMAP_INT_730_IH2_IRQ 1 |
196 | c3d2689d | balrog | # define OMAP_INT_730_USB_NON_ISO 2 |
197 | c3d2689d | balrog | # define OMAP_INT_730_USB_ISO 3 |
198 | c3d2689d | balrog | # define OMAP_INT_730_ICR 4 |
199 | c3d2689d | balrog | # define OMAP_INT_730_EAC 5 |
200 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK1 6 |
201 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK2 7 |
202 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK3 8 |
203 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2TX 10 |
204 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX 11 |
205 | c3d2689d | balrog | # define OMAP_INT_730_McBSP2RX_OVF 12 |
206 | c3d2689d | balrog | # define OMAP_INT_730_LCD_LINE 14 |
207 | c3d2689d | balrog | # define OMAP_INT_730_GSM_PROTECT 15 |
208 | c3d2689d | balrog | # define OMAP_INT_730_TIMER3 16 |
209 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK5 17 |
210 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK6 18 |
211 | c3d2689d | balrog | # define OMAP_INT_730_SPGIO_WR 29 |
212 | c3d2689d | balrog | |
213 | c3d2689d | balrog | /*
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214 | c3d2689d | balrog | * Common IRQ numbers for level 2 interrupt handler
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215 | c3d2689d | balrog | */
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216 | c3d2689d | balrog | # define OMAP_INT_KEYBOARD 1 |
217 | c3d2689d | balrog | # define OMAP_INT_uWireTX 2 |
218 | c3d2689d | balrog | # define OMAP_INT_uWireRX 3 |
219 | c3d2689d | balrog | # define OMAP_INT_I2C 4 |
220 | c3d2689d | balrog | # define OMAP_INT_MPUIO 5 |
221 | c3d2689d | balrog | # define OMAP_INT_USB_HHC_1 6 |
222 | c3d2689d | balrog | # define OMAP_INT_McBSP3TX 10 |
223 | c3d2689d | balrog | # define OMAP_INT_McBSP3RX 11 |
224 | c3d2689d | balrog | # define OMAP_INT_McBSP1TX 12 |
225 | c3d2689d | balrog | # define OMAP_INT_McBSP1RX 13 |
226 | c3d2689d | balrog | # define OMAP_INT_UART1 14 |
227 | c3d2689d | balrog | # define OMAP_INT_UART2 15 |
228 | c3d2689d | balrog | # define OMAP_INT_USB_W2FC 20 |
229 | c3d2689d | balrog | # define OMAP_INT_1WIRE 21 |
230 | c3d2689d | balrog | # define OMAP_INT_OS_TIMER 22 |
231 | b30bb3a2 | balrog | # define OMAP_INT_OQN 23 |
232 | c3d2689d | balrog | # define OMAP_INT_GAUGE_32K 24 |
233 | c3d2689d | balrog | # define OMAP_INT_RTC_TIMER 25 |
234 | c3d2689d | balrog | # define OMAP_INT_RTC_ALARM 26 |
235 | c3d2689d | balrog | # define OMAP_INT_DSP_MMU 28 |
236 | c3d2689d | balrog | |
237 | c3d2689d | balrog | /*
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238 | c3d2689d | balrog | * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
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239 | c3d2689d | balrog | */
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240 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1TX 16 |
241 | c3d2689d | balrog | # define OMAP_INT_1510_BT_MCSI1RX 17 |
242 | c3d2689d | balrog | # define OMAP_INT_1510_SoSSI_MATCH 19 |
243 | c3d2689d | balrog | # define OMAP_INT_1510_MEM_STICK 27 |
244 | c3d2689d | balrog | # define OMAP_INT_1510_COM_SPI_RO 31 |
245 | c3d2689d | balrog | |
246 | c3d2689d | balrog | /*
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247 | c3d2689d | balrog | * OMAP-310 specific IRQ numbers for level 2 interrupt handler
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248 | c3d2689d | balrog | */
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249 | c3d2689d | balrog | # define OMAP_INT_310_FAC 0 |
250 | c3d2689d | balrog | # define OMAP_INT_310_USB_HHC_2 7 |
251 | c3d2689d | balrog | # define OMAP_INT_310_MCSI1_FE 16 |
252 | c3d2689d | balrog | # define OMAP_INT_310_MCSI2_FE 17 |
253 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_ISO 29 |
254 | c3d2689d | balrog | # define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
255 | c3d2689d | balrog | # define OMAP_INT_310_McBSP2RX_OF 31 |
256 | c3d2689d | balrog | |
257 | c3d2689d | balrog | /*
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258 | c3d2689d | balrog | * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
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259 | c3d2689d | balrog | */
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260 | c3d2689d | balrog | # define OMAP_INT_1610_FAC 0 |
261 | c3d2689d | balrog | # define OMAP_INT_1610_USB_HHC_2 7 |
262 | c3d2689d | balrog | # define OMAP_INT_1610_USB_OTG 8 |
263 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI 9 |
264 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1TX 16 |
265 | c3d2689d | balrog | # define OMAP_INT_1610_BT_MCSI1RX 17 |
266 | c3d2689d | balrog | # define OMAP_INT_1610_SoSSI_MATCH 19 |
267 | c3d2689d | balrog | # define OMAP_INT_1610_MEM_STICK 27 |
268 | c3d2689d | balrog | # define OMAP_INT_1610_McBSP2RX_OF 31 |
269 | c3d2689d | balrog | # define OMAP_INT_1610_STI 32 |
270 | c3d2689d | balrog | # define OMAP_INT_1610_STI_WAKEUP 33 |
271 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER3 34 |
272 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER4 35 |
273 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER5 36 |
274 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER6 37 |
275 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER7 38 |
276 | c3d2689d | balrog | # define OMAP_INT_1610_GPTIMER8 39 |
277 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK2 40 |
278 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK3 41 |
279 | c3d2689d | balrog | # define OMAP_INT_1610_MMC2 42 |
280 | c3d2689d | balrog | # define OMAP_INT_1610_CF 43 |
281 | c3d2689d | balrog | # define OMAP_INT_1610_WAKE_UP_REQ 46 |
282 | c3d2689d | balrog | # define OMAP_INT_1610_GPIO_BANK4 48 |
283 | c3d2689d | balrog | # define OMAP_INT_1610_SPI 49 |
284 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH6 53 |
285 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH7 54 |
286 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH8 55 |
287 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH9 56 |
288 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH10 57 |
289 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH11 58 |
290 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH12 59 |
291 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH13 60 |
292 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH14 61 |
293 | c3d2689d | balrog | # define OMAP_INT_1610_DMA_CH15 62 |
294 | c3d2689d | balrog | # define OMAP_INT_1610_NAND 63 |
295 | c3d2689d | balrog | |
296 | c3d2689d | balrog | /*
|
297 | c3d2689d | balrog | * OMAP-730 specific IRQ numbers for level 2 interrupt handler
|
298 | c3d2689d | balrog | */
|
299 | c3d2689d | balrog | # define OMAP_INT_730_HW_ERRORS 0 |
300 | c3d2689d | balrog | # define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
301 | c3d2689d | balrog | # define OMAP_INT_730_CFCD 2 |
302 | c3d2689d | balrog | # define OMAP_INT_730_CFIREQ 3 |
303 | c3d2689d | balrog | # define OMAP_INT_730_I2C 4 |
304 | c3d2689d | balrog | # define OMAP_INT_730_PCC 5 |
305 | c3d2689d | balrog | # define OMAP_INT_730_MPU_EXT_NIRQ 6 |
306 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_1 7 |
307 | c3d2689d | balrog | # define OMAP_INT_730_SYREN_SPI 8 |
308 | c3d2689d | balrog | # define OMAP_INT_730_VLYNQ 9 |
309 | c3d2689d | balrog | # define OMAP_INT_730_GPIO_BANK4 10 |
310 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1TX 11 |
311 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX 12 |
312 | c3d2689d | balrog | # define OMAP_INT_730_McBSP1RX_OF 13 |
313 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
314 | c3d2689d | balrog | # define OMAP_INT_730_UART_MODEM_1 15 |
315 | c3d2689d | balrog | # define OMAP_INT_730_MCSI 16 |
316 | c3d2689d | balrog | # define OMAP_INT_730_uWireTX 17 |
317 | c3d2689d | balrog | # define OMAP_INT_730_uWireRX 18 |
318 | c3d2689d | balrog | # define OMAP_INT_730_SMC_CD 19 |
319 | c3d2689d | balrog | # define OMAP_INT_730_SMC_IREQ 20 |
320 | c3d2689d | balrog | # define OMAP_INT_730_HDQ_1WIRE 21 |
321 | c3d2689d | balrog | # define OMAP_INT_730_TIMER32K 22 |
322 | c3d2689d | balrog | # define OMAP_INT_730_MMC_SDIO 23 |
323 | c3d2689d | balrog | # define OMAP_INT_730_UPLD 24 |
324 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_1 27 |
325 | c3d2689d | balrog | # define OMAP_INT_730_USB_HHC_2 28 |
326 | c3d2689d | balrog | # define OMAP_INT_730_USB_GENI 29 |
327 | c3d2689d | balrog | # define OMAP_INT_730_USB_OTG 30 |
328 | c3d2689d | balrog | # define OMAP_INT_730_CAMERA_IF 31 |
329 | c3d2689d | balrog | # define OMAP_INT_730_RNG 32 |
330 | c3d2689d | balrog | # define OMAP_INT_730_DUAL_MODE_TIMER 33 |
331 | c3d2689d | balrog | # define OMAP_INT_730_DBB_RF_EN 34 |
332 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO_KEYPAD 35 |
333 | c3d2689d | balrog | # define OMAP_INT_730_SHA1_MD5 36 |
334 | c3d2689d | balrog | # define OMAP_INT_730_SPI_100K_2 37 |
335 | c3d2689d | balrog | # define OMAP_INT_730_RNG_IDLE 38 |
336 | c3d2689d | balrog | # define OMAP_INT_730_MPUIO 39 |
337 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
338 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_FALLING 41 |
339 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_OE_RISING 42 |
340 | c3d2689d | balrog | # define OMAP_INT_730_LLPC_VSYNC 43 |
341 | c3d2689d | balrog | # define OMAP_INT_730_WAKE_UP_REQ 46 |
342 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH6 53 |
343 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH7 54 |
344 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH8 55 |
345 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH9 56 |
346 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH10 57 |
347 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH11 58 |
348 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH12 59 |
349 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH13 60 |
350 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH14 61 |
351 | c3d2689d | balrog | # define OMAP_INT_730_DMA_CH15 62 |
352 | c3d2689d | balrog | # define OMAP_INT_730_NAND 63 |
353 | c3d2689d | balrog | |
354 | c3d2689d | balrog | /*
|
355 | c3d2689d | balrog | * OMAP-24xx common IRQ numbers
|
356 | c3d2689d | balrog | */
|
357 | 54585ffe | balrog | # define OMAP_INT_24XX_STI 4 |
358 | c3d2689d | balrog | # define OMAP_INT_24XX_SYS_NIRQ 7 |
359 | 827df9f3 | balrog | # define OMAP_INT_24XX_L3_IRQ 10 |
360 | 827df9f3 | balrog | # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
361 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ0 12 |
362 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ1 13 |
363 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ2 14 |
364 | c3d2689d | balrog | # define OMAP_INT_24XX_SDMA_IRQ3 15 |
365 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP2_IRQ 16 |
366 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP3_IRQ 17 |
367 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP4_IRQ 18 |
368 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP5_IRQ 19 |
369 | 827df9f3 | balrog | # define OMAP_INT_24XX_GPMC_IRQ 20 |
370 | 827df9f3 | balrog | # define OMAP_INT_24XX_GUFFAW_IRQ 21 |
371 | 827df9f3 | balrog | # define OMAP_INT_24XX_IVA_IRQ 22 |
372 | 827df9f3 | balrog | # define OMAP_INT_24XX_EAC_IRQ 23 |
373 | c3d2689d | balrog | # define OMAP_INT_24XX_CAM_IRQ 24 |
374 | c3d2689d | balrog | # define OMAP_INT_24XX_DSS_IRQ 25 |
375 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U0_MPU 26 |
376 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_UMA 27 |
377 | c3d2689d | balrog | # define OMAP_INT_24XX_DSP_MMU 28 |
378 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK1 29 |
379 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK2 30 |
380 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK3 31 |
381 | c3d2689d | balrog | # define OMAP_INT_24XX_GPIO_BANK4 32 |
382 | 827df9f3 | balrog | # define OMAP_INT_243X_GPIO_BANK5 33 |
383 | c3d2689d | balrog | # define OMAP_INT_24XX_MAIL_U3_MPU 34 |
384 | 827df9f3 | balrog | # define OMAP_INT_24XX_WDT3 35 |
385 | 827df9f3 | balrog | # define OMAP_INT_24XX_WDT4 36 |
386 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER1 37 |
387 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER2 38 |
388 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER3 39 |
389 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER4 40 |
390 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER5 41 |
391 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER6 42 |
392 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER7 43 |
393 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER8 44 |
394 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER9 45 |
395 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER10 46 |
396 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER11 47 |
397 | c3d2689d | balrog | # define OMAP_INT_24XX_GPTIMER12 48 |
398 | 827df9f3 | balrog | # define OMAP_INT_24XX_PKA_IRQ 50 |
399 | 827df9f3 | balrog | # define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
400 | 827df9f3 | balrog | # define OMAP_INT_24XX_RNG_IRQ 52 |
401 | 827df9f3 | balrog | # define OMAP_INT_24XX_MG_IRQ 53 |
402 | 827df9f3 | balrog | # define OMAP_INT_24XX_I2C1_IRQ 56 |
403 | 827df9f3 | balrog | # define OMAP_INT_24XX_I2C2_IRQ 57 |
404 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
405 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
406 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
407 | c3d2689d | balrog | # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
408 | 827df9f3 | balrog | # define OMAP_INT_243X_MCBSP1_IRQ 64 |
409 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI1_IRQ 65 |
410 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI2_IRQ 66 |
411 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI1_IRQ0 67 |
412 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI1_IRQ1 68 |
413 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI2_IRQ0 69 |
414 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI2_IRQ1 70 |
415 | 827df9f3 | balrog | # define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
416 | c3d2689d | balrog | # define OMAP_INT_24XX_UART1_IRQ 72 |
417 | c3d2689d | balrog | # define OMAP_INT_24XX_UART2_IRQ 73 |
418 | c3d2689d | balrog | # define OMAP_INT_24XX_UART3_IRQ 74 |
419 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_GEN 75 |
420 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_NISO 76 |
421 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_ISO 77 |
422 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
423 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
424 | c3d2689d | balrog | # define OMAP_INT_24XX_USB_IRQ_OTG 80 |
425 | 827df9f3 | balrog | # define OMAP_INT_24XX_VLYNQ_IRQ 81 |
426 | c3d2689d | balrog | # define OMAP_INT_24XX_MMC_IRQ 83 |
427 | 827df9f3 | balrog | # define OMAP_INT_24XX_MS_IRQ 84 |
428 | 827df9f3 | balrog | # define OMAP_INT_24XX_FAC_IRQ 85 |
429 | 827df9f3 | balrog | # define OMAP_INT_24XX_MCSPI3_IRQ 91 |
430 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_MC 92 |
431 | c3d2689d | balrog | # define OMAP_INT_243X_HS_USB_DMA 93 |
432 | c3d2689d | balrog | # define OMAP_INT_243X_CARKIT 94 |
433 | 827df9f3 | balrog | # define OMAP_INT_34XX_GPTIMER12 95 |
434 | c3d2689d | balrog | |
435 | b4e3104b | balrog | /* omap_dma.c */
|
436 | 089b7c0a | balrog | enum omap_dma_model {
|
437 | b4e3104b | balrog | omap_dma_3_0, |
438 | b4e3104b | balrog | omap_dma_3_1, |
439 | b4e3104b | balrog | omap_dma_3_2, |
440 | b4e3104b | balrog | omap_dma_4, |
441 | 089b7c0a | balrog | }; |
442 | 089b7c0a | balrog | |
443 | afbb5194 | balrog | struct soc_dma_s;
|
444 | c227f099 | Anthony Liguori | struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
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445 | 089b7c0a | balrog | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
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446 | 089b7c0a | balrog | enum omap_dma_model model);
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447 | c227f099 | Anthony Liguori | struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
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448 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, int fifo, |
449 | 827df9f3 | balrog | int chans, omap_clk iclk, omap_clk fclk);
|
450 | afbb5194 | balrog | void omap_dma_reset(struct soc_dma_s *s); |
451 | c3d2689d | balrog | |
452 | b4e3104b | balrog | struct dma_irq_map {
|
453 | b4e3104b | balrog | int ih;
|
454 | b4e3104b | balrog | int intr;
|
455 | b4e3104b | balrog | }; |
456 | b4e3104b | balrog | |
457 | b4e3104b | balrog | /* Only used in OMAP DMA 3.x gigacells */
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458 | c3d2689d | balrog | enum omap_dma_port {
|
459 | c3d2689d | balrog | emiff = 0,
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460 | c3d2689d | balrog | emifs, |
461 | 089b7c0a | balrog | imif, /* omap16xx: ocp_t1 */
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462 | c3d2689d | balrog | tipb, |
463 | 089b7c0a | balrog | local, /* omap16xx: ocp_t2 */
|
464 | c3d2689d | balrog | tipb_mpui, |
465 | 827df9f3 | balrog | __omap_dma_port_last, |
466 | c3d2689d | balrog | }; |
467 | c3d2689d | balrog | |
468 | 089b7c0a | balrog | typedef enum { |
469 | 089b7c0a | balrog | constant = 0,
|
470 | 089b7c0a | balrog | post_incremented, |
471 | 089b7c0a | balrog | single_index, |
472 | 089b7c0a | balrog | double_index, |
473 | c227f099 | Anthony Liguori | } omap_dma_addressing_t; |
474 | 089b7c0a | balrog | |
475 | b4e3104b | balrog | /* Only used in OMAP DMA 3.x gigacells */
|
476 | c3d2689d | balrog | struct omap_dma_lcd_channel_s {
|
477 | c3d2689d | balrog | enum omap_dma_port src;
|
478 | c227f099 | Anthony Liguori | target_phys_addr_t src_f1_top; |
479 | c227f099 | Anthony Liguori | target_phys_addr_t src_f1_bottom; |
480 | c227f099 | Anthony Liguori | target_phys_addr_t src_f2_top; |
481 | c227f099 | Anthony Liguori | target_phys_addr_t src_f2_bottom; |
482 | 089b7c0a | balrog | |
483 | 089b7c0a | balrog | /* Used in OMAP DMA 3.2 gigacell */
|
484 | 089b7c0a | balrog | unsigned char brust_f1; |
485 | 089b7c0a | balrog | unsigned char pack_f1; |
486 | 089b7c0a | balrog | unsigned char data_type_f1; |
487 | 089b7c0a | balrog | unsigned char brust_f2; |
488 | 089b7c0a | balrog | unsigned char pack_f2; |
489 | 089b7c0a | balrog | unsigned char data_type_f2; |
490 | 089b7c0a | balrog | unsigned char end_prog; |
491 | 089b7c0a | balrog | unsigned char repeat; |
492 | 089b7c0a | balrog | unsigned char auto_init; |
493 | 089b7c0a | balrog | unsigned char priority; |
494 | 089b7c0a | balrog | unsigned char fs; |
495 | 089b7c0a | balrog | unsigned char running; |
496 | 089b7c0a | balrog | unsigned char bs; |
497 | 089b7c0a | balrog | unsigned char omap_3_1_compatible_disable; |
498 | 089b7c0a | balrog | unsigned char dst; |
499 | 089b7c0a | balrog | unsigned char lch_type; |
500 | 089b7c0a | balrog | int16_t element_index_f1; |
501 | 089b7c0a | balrog | int16_t element_index_f2; |
502 | 089b7c0a | balrog | int32_t frame_index_f1; |
503 | 089b7c0a | balrog | int32_t frame_index_f2; |
504 | 089b7c0a | balrog | uint16_t elements_f1; |
505 | 089b7c0a | balrog | uint16_t frames_f1; |
506 | 089b7c0a | balrog | uint16_t elements_f2; |
507 | 089b7c0a | balrog | uint16_t frames_f2; |
508 | c227f099 | Anthony Liguori | omap_dma_addressing_t mode_f1; |
509 | c227f099 | Anthony Liguori | omap_dma_addressing_t mode_f2; |
510 | 089b7c0a | balrog | |
511 | c3d2689d | balrog | /* Destination port is fixed. */
|
512 | c3d2689d | balrog | int interrupts;
|
513 | c3d2689d | balrog | int condition;
|
514 | c3d2689d | balrog | int dual;
|
515 | c3d2689d | balrog | |
516 | c3d2689d | balrog | int current_frame;
|
517 | c227f099 | Anthony Liguori | target_phys_addr_t phys_framebuffer[2];
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518 | c3d2689d | balrog | qemu_irq irq; |
519 | c3d2689d | balrog | struct omap_mpu_state_s *mpu;
|
520 | afbb5194 | balrog | } *omap_dma_get_lcdch(struct soc_dma_s *s);
|
521 | c3d2689d | balrog | |
522 | c3d2689d | balrog | /*
|
523 | c3d2689d | balrog | * DMA request numbers for OMAP1
|
524 | c3d2689d | balrog | * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
|
525 | c3d2689d | balrog | */
|
526 | c3d2689d | balrog | # define OMAP_DMA_NO_DEVICE 0 |
527 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_TX 1 |
528 | c3d2689d | balrog | # define OMAP_DMA_MCSI1_RX 2 |
529 | c3d2689d | balrog | # define OMAP_DMA_I2C_RX 3 |
530 | c3d2689d | balrog | # define OMAP_DMA_I2C_TX 4 |
531 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ0 5 |
532 | c3d2689d | balrog | # define OMAP_DMA_EXT_NDMA_REQ1 6 |
533 | c3d2689d | balrog | # define OMAP_DMA_UWIRE_TX 7 |
534 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_TX 8 |
535 | c3d2689d | balrog | # define OMAP_DMA_MCBSP1_RX 9 |
536 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_TX 10 |
537 | c3d2689d | balrog | # define OMAP_DMA_MCBSP3_RX 11 |
538 | c3d2689d | balrog | # define OMAP_DMA_UART1_TX 12 |
539 | c3d2689d | balrog | # define OMAP_DMA_UART1_RX 13 |
540 | c3d2689d | balrog | # define OMAP_DMA_UART2_TX 14 |
541 | c3d2689d | balrog | # define OMAP_DMA_UART2_RX 15 |
542 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_TX 16 |
543 | c3d2689d | balrog | # define OMAP_DMA_MCBSP2_RX 17 |
544 | c3d2689d | balrog | # define OMAP_DMA_UART3_TX 18 |
545 | c3d2689d | balrog | # define OMAP_DMA_UART3_RX 19 |
546 | c3d2689d | balrog | # define OMAP_DMA_CAMERA_IF_RX 20 |
547 | c3d2689d | balrog | # define OMAP_DMA_MMC_TX 21 |
548 | c3d2689d | balrog | # define OMAP_DMA_MMC_RX 22 |
549 | c3d2689d | balrog | # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
550 | c3d2689d | balrog | # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
551 | c3d2689d | balrog | # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
552 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX0 26 |
553 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX1 27 |
554 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_RX2 28 |
555 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX0 29 |
556 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX1 30 |
557 | c3d2689d | balrog | # define OMAP_DMA_USB_W2FC_TX2 31 |
558 | c3d2689d | balrog | |
559 | c3d2689d | balrog | /* These are only for 1610 */
|
560 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_IN 32 |
561 | c3d2689d | balrog | # define OMAP_DMA_SPI_TX 33 |
562 | c3d2689d | balrog | # define OMAP_DMA_SPI_RX 34 |
563 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_HASH 35 |
564 | c3d2689d | balrog | # define OMAP_DMA_CCP_ATTN 36 |
565 | c3d2689d | balrog | # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
566 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
567 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
568 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
569 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
570 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
571 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
572 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
573 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
574 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
575 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
576 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
577 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
578 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
579 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
580 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
581 | c3d2689d | balrog | # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
582 | c3d2689d | balrog | # define OMAP_DMA_MMC2_TX 54 |
583 | c3d2689d | balrog | # define OMAP_DMA_MMC2_RX 55 |
584 | c3d2689d | balrog | # define OMAP_DMA_CRYPTO_DES_OUT 56 |
585 | c3d2689d | balrog | |
586 | 827df9f3 | balrog | /*
|
587 | 827df9f3 | balrog | * DMA request numbers for the OMAP2
|
588 | 827df9f3 | balrog | */
|
589 | 827df9f3 | balrog | # define OMAP24XX_DMA_NO_DEVICE 0 |
590 | 827df9f3 | balrog | # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
591 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ0 2 |
592 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ1 3 |
593 | 827df9f3 | balrog | # define OMAP24XX_DMA_GPMC 4 |
594 | 827df9f3 | balrog | # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
595 | 827df9f3 | balrog | # define OMAP24XX_DMA_DSS 6 |
596 | 827df9f3 | balrog | # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
597 | 827df9f3 | balrog | # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
598 | 827df9f3 | balrog | # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
599 | 827df9f3 | balrog | # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
600 | 827df9f3 | balrog | # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
601 | 827df9f3 | balrog | # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
602 | 827df9f3 | balrog | # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
603 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ2 14 |
604 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ3 15 |
605 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ4 16 |
606 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_AC_RD 17 |
607 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_AC_WR 18 |
608 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
609 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
610 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
611 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
612 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
613 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
614 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
615 | 827df9f3 | balrog | # define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
616 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C1_TX 27 |
617 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C1_RX 28 |
618 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C2_TX 29 |
619 | 827df9f3 | balrog | # define OMAP24XX_DMA_I2C2_RX 30 |
620 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP1_TX 31 |
621 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP1_RX 32 |
622 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP2_TX 33 |
623 | 827df9f3 | balrog | # define OMAP24XX_DMA_MCBSP2_RX 34 |
624 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX0 35 |
625 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX0 36 |
626 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX1 37 |
627 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX1 38 |
628 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX2 39 |
629 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX2 40 |
630 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_TX3 41 |
631 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI1_RX3 42 |
632 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_TX0 43 |
633 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_RX0 44 |
634 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_TX1 45 |
635 | 827df9f3 | balrog | # define OMAP24XX_DMA_SPI2_RX1 46 |
636 | 827df9f3 | balrog | |
637 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART1_TX 49 |
638 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART1_RX 50 |
639 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART2_TX 51 |
640 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART2_RX 52 |
641 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART3_TX 53 |
642 | 827df9f3 | balrog | # define OMAP24XX_DMA_UART3_RX 54 |
643 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX0 55 |
644 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX0 56 |
645 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX1 57 |
646 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX1 58 |
647 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_TX2 59 |
648 | 827df9f3 | balrog | # define OMAP24XX_DMA_USB_W2FC_RX2 60 |
649 | 827df9f3 | balrog | # define OMAP24XX_DMA_MMC1_TX 61 |
650 | 827df9f3 | balrog | # define OMAP24XX_DMA_MMC1_RX 62 |
651 | 827df9f3 | balrog | # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
652 | 827df9f3 | balrog | # define OMAP24XX_DMA_EXT_DMAREQ5 64 |
653 | 827df9f3 | balrog | |
654 | b4e3104b | balrog | /* omap[123].c */
|
655 | c58d37cf | cmchao | /* OMAP2 gp timer */
|
656 | 827df9f3 | balrog | struct omap_gp_timer_s;
|
657 | 827df9f3 | balrog | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
658 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk); |
659 | c58d37cf | cmchao | void omap_gp_timer_reset(struct omap_gp_timer_s *s); |
660 | 827df9f3 | balrog | |
661 | 011d87d0 | cmchao | /* OMAP2 sysctimer */
|
662 | 011d87d0 | cmchao | struct omap_synctimer_s;
|
663 | 011d87d0 | cmchao | struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, |
664 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
|
665 | 011d87d0 | cmchao | void omap_synctimer_reset(struct omap_synctimer_s *s); |
666 | 827df9f3 | balrog | |
667 | c3d2689d | balrog | struct omap_uart_s;
|
668 | c227f099 | Anthony Liguori | struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
|
669 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
670 | 6a8aabd3 | Stefan Weil | qemu_irq txdma, qemu_irq rxdma, |
671 | 6a8aabd3 | Stefan Weil | const char *label, CharDriverState *chr); |
672 | 827df9f3 | balrog | struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
673 | 827df9f3 | balrog | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
674 | 6a8aabd3 | Stefan Weil | qemu_irq txdma, qemu_irq rxdma, |
675 | 6a8aabd3 | Stefan Weil | const char *label, CharDriverState *chr); |
676 | 827df9f3 | balrog | void omap_uart_reset(struct omap_uart_s *s); |
677 | 75554a3c | balrog | void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); |
678 | c3d2689d | balrog | |
679 | fe71e81a | balrog | struct omap_mpuio_s;
|
680 | c227f099 | Anthony Liguori | struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
|
681 | fe71e81a | balrog | qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
682 | fe71e81a | balrog | omap_clk clk); |
683 | fe71e81a | balrog | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
|
684 | fe71e81a | balrog | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
685 | fe71e81a | balrog | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
686 | fe71e81a | balrog | |
687 | bc24a225 | Paul Brook | struct uWireSlave {
|
688 | d951f6ff | balrog | uint16_t (*receive)(void *opaque);
|
689 | d951f6ff | balrog | void (*send)(void *opaque, uint16_t data); |
690 | d951f6ff | balrog | void *opaque;
|
691 | d951f6ff | balrog | }; |
692 | d951f6ff | balrog | struct omap_uwire_s;
|
693 | c227f099 | Anthony Liguori | struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
|
694 | d951f6ff | balrog | qemu_irq *irq, qemu_irq dma, omap_clk clk); |
695 | d951f6ff | balrog | void omap_uwire_attach(struct omap_uwire_s *s, |
696 | bc24a225 | Paul Brook | uWireSlave *slave, int chipselect);
|
697 | d951f6ff | balrog | |
698 | 2d08cc7c | cmchao | /* OMAP2 spi */
|
699 | 827df9f3 | balrog | struct omap_mcspi_s;
|
700 | 827df9f3 | balrog | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
701 | 827df9f3 | balrog | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
702 | 827df9f3 | balrog | void omap_mcspi_attach(struct omap_mcspi_s *s, |
703 | e927bb00 | balrog | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
704 | 827df9f3 | balrog | int chipselect);
|
705 | 2d08cc7c | cmchao | void omap_mcspi_reset(struct omap_mcspi_s *s); |
706 | 827df9f3 | balrog | |
707 | bc24a225 | Paul Brook | struct I2SCodec {
|
708 | d8f699cb | balrog | void *opaque;
|
709 | d8f699cb | balrog | |
710 | d8f699cb | balrog | /* The CPU can call this if it is generating the clock signal on the
|
711 | d8f699cb | balrog | * i2s port. The CODEC can ignore it if it is set up as a clock
|
712 | d8f699cb | balrog | * master and generates its own clock. */
|
713 | d8f699cb | balrog | void (*set_rate)(void *opaque, int in, int out); |
714 | d8f699cb | balrog | |
715 | d8f699cb | balrog | void (*tx_swallow)(void *opaque); |
716 | d8f699cb | balrog | qemu_irq rx_swallow; |
717 | d8f699cb | balrog | qemu_irq tx_start; |
718 | d8f699cb | balrog | |
719 | 73560bc8 | balrog | int tx_rate;
|
720 | 73560bc8 | balrog | int cts;
|
721 | 73560bc8 | balrog | int rx_rate;
|
722 | 73560bc8 | balrog | int rts;
|
723 | 73560bc8 | balrog | |
724 | d8f699cb | balrog | struct i2s_fifo_s {
|
725 | d8f699cb | balrog | uint8_t *fifo; |
726 | d8f699cb | balrog | int len;
|
727 | d8f699cb | balrog | int start;
|
728 | d8f699cb | balrog | int size;
|
729 | d8f699cb | balrog | } in, out; |
730 | d8f699cb | balrog | }; |
731 | d8f699cb | balrog | struct omap_mcbsp_s;
|
732 | c227f099 | Anthony Liguori | struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
|
733 | d8f699cb | balrog | qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
734 | bc24a225 | Paul Brook | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); |
735 | d8f699cb | balrog | |
736 | 827df9f3 | balrog | void omap_tap_init(struct omap_target_agent_s *ta, |
737 | 827df9f3 | balrog | struct omap_mpu_state_s *mpu);
|
738 | 827df9f3 | balrog | |
739 | c3d2689d | balrog | /* omap_lcdc.c */
|
740 | c3d2689d | balrog | struct omap_lcd_panel_s;
|
741 | c3d2689d | balrog | void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
742 | c227f099 | Anthony Liguori | struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
|
743 | 3023f332 | aliguori | struct omap_dma_lcd_channel_s *dma,
|
744 | c227f099 | Anthony Liguori | ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
745 | c3d2689d | balrog | |
746 | 827df9f3 | balrog | /* omap_dss.c */
|
747 | 827df9f3 | balrog | struct rfbi_chip_s {
|
748 | 827df9f3 | balrog | void *opaque;
|
749 | 827df9f3 | balrog | void (*write)(void *opaque, int dc, uint16_t value); |
750 | 827df9f3 | balrog | void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
751 | 827df9f3 | balrog | uint16_t (*read)(void *opaque, int dc); |
752 | 827df9f3 | balrog | }; |
753 | 827df9f3 | balrog | struct omap_dss_s;
|
754 | 827df9f3 | balrog | void omap_dss_reset(struct omap_dss_s *s); |
755 | 827df9f3 | balrog | struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
756 | c227f099 | Anthony Liguori | target_phys_addr_t l3_base, |
757 | 827df9f3 | balrog | qemu_irq irq, qemu_irq drq, |
758 | 827df9f3 | balrog | omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
759 | 827df9f3 | balrog | omap_clk ick1, omap_clk ick2); |
760 | 827df9f3 | balrog | void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
761 | 827df9f3 | balrog | |
762 | b30bb3a2 | balrog | /* omap_mmc.c */
|
763 | b30bb3a2 | balrog | struct omap_mmc_s;
|
764 | c227f099 | Anthony Liguori | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
765 | 87ecb68b | pbrook | BlockDriverState *bd, |
766 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
767 | 827df9f3 | balrog | struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
768 | 827df9f3 | balrog | BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
769 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk); |
770 | b30bb3a2 | balrog | void omap_mmc_reset(struct omap_mmc_s *s); |
771 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
772 | 827df9f3 | balrog | void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
773 | b30bb3a2 | balrog | |
774 | 02645926 | balrog | /* omap_i2c.c */
|
775 | 02645926 | balrog | struct omap_i2c_s;
|
776 | c227f099 | Anthony Liguori | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
777 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk); |
778 | 29885477 | balrog | struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
779 | 29885477 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); |
780 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s); |
781 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
|
782 | 02645926 | balrog | |
783 | c3d2689d | balrog | # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
|
784 | c3d2689d | balrog | # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
|
785 | 827df9f3 | balrog | # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
|
786 | 827df9f3 | balrog | # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
|
787 | 827df9f3 | balrog | # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
|
788 | 827df9f3 | balrog | # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
|
789 | 827df9f3 | balrog | # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
|
790 | 827df9f3 | balrog | # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
|
791 | 827df9f3 | balrog | |
792 | c3d2689d | balrog | # define cpu_is_omap15xx(cpu) \
|
793 | c3d2689d | balrog | (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
794 | 827df9f3 | balrog | # define cpu_is_omap16xx(cpu) \
|
795 | 827df9f3 | balrog | (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
796 | 827df9f3 | balrog | # define cpu_is_omap24xx(cpu) \
|
797 | 827df9f3 | balrog | (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
798 | 827df9f3 | balrog | |
799 | 827df9f3 | balrog | # define cpu_class_omap1(cpu) \
|
800 | 827df9f3 | balrog | (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
801 | 827df9f3 | balrog | # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
|
802 | 827df9f3 | balrog | # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
|
803 | c3d2689d | balrog | |
804 | c3d2689d | balrog | struct omap_mpu_state_s {
|
805 | 827df9f3 | balrog | enum omap_mpu_model {
|
806 | c3d2689d | balrog | omap310, |
807 | c3d2689d | balrog | omap1510, |
808 | 827df9f3 | balrog | omap1610, |
809 | 827df9f3 | balrog | omap1710, |
810 | 827df9f3 | balrog | omap2410, |
811 | 827df9f3 | balrog | omap2420, |
812 | 827df9f3 | balrog | omap2422, |
813 | 827df9f3 | balrog | omap2423, |
814 | 827df9f3 | balrog | omap2430, |
815 | 827df9f3 | balrog | omap3430, |
816 | c3d2689d | balrog | } mpu_model; |
817 | c3d2689d | balrog | |
818 | c3d2689d | balrog | CPUState *env; |
819 | c3d2689d | balrog | |
820 | c3d2689d | balrog | qemu_irq *irq[2];
|
821 | c3d2689d | balrog | qemu_irq *drq; |
822 | c3d2689d | balrog | |
823 | c3d2689d | balrog | qemu_irq wakeup; |
824 | c3d2689d | balrog | |
825 | c3d2689d | balrog | struct omap_dma_port_if_s {
|
826 | 5fafdf24 | ths | uint32_t (*read[3])(struct omap_mpu_state_s *s, |
827 | c227f099 | Anthony Liguori | target_phys_addr_t offset); |
828 | c3d2689d | balrog | void (*write[3])(struct omap_mpu_state_s *s, |
829 | c227f099 | Anthony Liguori | target_phys_addr_t offset, uint32_t value); |
830 | c3d2689d | balrog | int (*addr_valid)(struct omap_mpu_state_s *s, |
831 | c227f099 | Anthony Liguori | target_phys_addr_t addr); |
832 | 827df9f3 | balrog | } port[__omap_dma_port_last]; |
833 | c3d2689d | balrog | |
834 | c3d2689d | balrog | unsigned long sdram_size; |
835 | c3d2689d | balrog | unsigned long sram_size; |
836 | c3d2689d | balrog | |
837 | c3d2689d | balrog | /* MPUI-TIPB peripherals */
|
838 | d951f6ff | balrog | struct omap_uart_s *uart[3]; |
839 | d951f6ff | balrog | |
840 | 77831c20 | Juha Riihimäki | DeviceState *gpio; |
841 | c3d2689d | balrog | |
842 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp1;
|
843 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp3;
|
844 | d8f699cb | balrog | |
845 | c3d2689d | balrog | /* MPU public TIPB peripherals */
|
846 | c3d2689d | balrog | struct omap_32khz_timer_s *os_timer;
|
847 | c3d2689d | balrog | |
848 | b30bb3a2 | balrog | struct omap_mmc_s *mmc;
|
849 | b30bb3a2 | balrog | |
850 | d951f6ff | balrog | struct omap_mpuio_s *mpuio;
|
851 | d951f6ff | balrog | |
852 | d951f6ff | balrog | struct omap_uwire_s *microwire;
|
853 | d951f6ff | balrog | |
854 | 66450b15 | balrog | struct {
|
855 | 66450b15 | balrog | uint8_t output; |
856 | 66450b15 | balrog | uint8_t level; |
857 | 66450b15 | balrog | uint8_t enable; |
858 | 66450b15 | balrog | int clk;
|
859 | 66450b15 | balrog | } pwl; |
860 | 66450b15 | balrog | |
861 | f34c417b | balrog | struct {
|
862 | f34c417b | balrog | uint8_t frc; |
863 | f34c417b | balrog | uint8_t vrc; |
864 | f34c417b | balrog | uint8_t gcr; |
865 | f34c417b | balrog | omap_clk clk; |
866 | f34c417b | balrog | } pwt; |
867 | f34c417b | balrog | |
868 | 827df9f3 | balrog | struct omap_i2c_s *i2c[2]; |
869 | 4a2c8ac2 | balrog | |
870 | 02645926 | balrog | struct omap_rtc_s *rtc;
|
871 | 02645926 | balrog | |
872 | d8f699cb | balrog | struct omap_mcbsp_s *mcbsp2;
|
873 | d8f699cb | balrog | |
874 | f9d43072 | balrog | struct omap_lpg_s *led[2]; |
875 | f9d43072 | balrog | |
876 | c3d2689d | balrog | /* MPU private TIPB peripherals */
|
877 | c3d2689d | balrog | struct omap_intr_handler_s *ih[2]; |
878 | c3d2689d | balrog | |
879 | afbb5194 | balrog | struct soc_dma_s *dma;
|
880 | c3d2689d | balrog | |
881 | c3d2689d | balrog | struct omap_mpu_timer_s *timer[3]; |
882 | c3d2689d | balrog | struct omap_watchdog_timer_s *wdt;
|
883 | c3d2689d | balrog | |
884 | c3d2689d | balrog | struct omap_lcd_panel_s *lcd;
|
885 | c3d2689d | balrog | |
886 | c3d2689d | balrog | uint32_t ulpd_pm_regs[21];
|
887 | c3d2689d | balrog | int64_t ulpd_gauge_start; |
888 | c3d2689d | balrog | |
889 | c3d2689d | balrog | uint32_t func_mux_ctrl[14];
|
890 | c3d2689d | balrog | uint32_t comp_mode_ctrl[1];
|
891 | c3d2689d | balrog | uint32_t pull_dwn_ctrl[4];
|
892 | c3d2689d | balrog | uint32_t gate_inh_ctrl[1];
|
893 | c3d2689d | balrog | uint32_t voltage_ctrl[1];
|
894 | c3d2689d | balrog | uint32_t test_dbg_ctrl[1];
|
895 | c3d2689d | balrog | uint32_t mod_conf_ctrl[1];
|
896 | c3d2689d | balrog | int compat1509;
|
897 | c3d2689d | balrog | |
898 | c3d2689d | balrog | uint32_t mpui_ctrl; |
899 | c3d2689d | balrog | |
900 | c3d2689d | balrog | struct omap_tipb_bridge_s *private_tipb;
|
901 | c3d2689d | balrog | struct omap_tipb_bridge_s *public_tipb;
|
902 | c3d2689d | balrog | |
903 | c3d2689d | balrog | uint32_t tcmi_regs[17];
|
904 | c3d2689d | balrog | |
905 | c3d2689d | balrog | struct dpll_ctl_s {
|
906 | c3d2689d | balrog | uint16_t mode; |
907 | c3d2689d | balrog | omap_clk dpll; |
908 | c3d2689d | balrog | } dpll[3];
|
909 | c3d2689d | balrog | |
910 | c3d2689d | balrog | omap_clk clks; |
911 | c3d2689d | balrog | struct {
|
912 | c3d2689d | balrog | int cold_start;
|
913 | c3d2689d | balrog | int clocking_scheme;
|
914 | c3d2689d | balrog | uint16_t arm_ckctl; |
915 | c3d2689d | balrog | uint16_t arm_idlect1; |
916 | c3d2689d | balrog | uint16_t arm_idlect2; |
917 | c3d2689d | balrog | uint16_t arm_ewupct; |
918 | c3d2689d | balrog | uint16_t arm_rstct1; |
919 | c3d2689d | balrog | uint16_t arm_rstct2; |
920 | c3d2689d | balrog | uint16_t arm_ckout1; |
921 | c3d2689d | balrog | int dpll1_mode;
|
922 | c3d2689d | balrog | uint16_t dsp_idlect1; |
923 | c3d2689d | balrog | uint16_t dsp_idlect2; |
924 | c3d2689d | balrog | uint16_t dsp_rstct2; |
925 | c3d2689d | balrog | } clkm; |
926 | 827df9f3 | balrog | |
927 | 827df9f3 | balrog | /* OMAP2-only peripherals */
|
928 | 827df9f3 | balrog | struct omap_l4_s *l4;
|
929 | 827df9f3 | balrog | |
930 | 827df9f3 | balrog | struct omap_gp_timer_s *gptimer[12]; |
931 | 011d87d0 | cmchao | struct omap_synctimer_s *synctimer;
|
932 | 827df9f3 | balrog | |
933 | 827df9f3 | balrog | struct omap_prcm_s *prcm;
|
934 | 827df9f3 | balrog | struct omap_sdrc_s *sdrc;
|
935 | 827df9f3 | balrog | struct omap_gpmc_s *gpmc;
|
936 | 827df9f3 | balrog | struct omap_sysctl_s *sysc;
|
937 | 827df9f3 | balrog | |
938 | 827df9f3 | balrog | struct omap_mcspi_s *mcspi[2]; |
939 | 827df9f3 | balrog | |
940 | 827df9f3 | balrog | struct omap_dss_s *dss;
|
941 | 99570a40 | balrog | |
942 | 99570a40 | balrog | struct omap_eac_s *eac;
|
943 | 827df9f3 | balrog | }; |
944 | 827df9f3 | balrog | |
945 | 827df9f3 | balrog | /* omap1.c */
|
946 | 827df9f3 | balrog | struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
947 | 3023f332 | aliguori | const char *core); |
948 | 827df9f3 | balrog | |
949 | 827df9f3 | balrog | /* omap2.c */
|
950 | 827df9f3 | balrog | struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
951 | 3023f332 | aliguori | const char *core); |
952 | c3d2689d | balrog | |
953 | c3d2689d | balrog | # if TARGET_PHYS_ADDR_BITS == 32 |
954 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08x" |
955 | c3d2689d | balrog | # elif TARGET_PHYS_ADDR_BITS == 64 |
956 | c3d2689d | balrog | # define OMAP_FMT_plx "%#08" PRIx64 |
957 | c3d2689d | balrog | # else
|
958 | c3d2689d | balrog | # error TARGET_PHYS_ADDR_BITS undefined
|
959 | c3d2689d | balrog | # endif
|
960 | c3d2689d | balrog | |
961 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
|
962 | c227f099 | Anthony Liguori | void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
963 | 9596ebb7 | pbrook | uint32_t value); |
964 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
|
965 | c227f099 | Anthony Liguori | void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
966 | b30bb3a2 | balrog | uint32_t value); |
967 | c227f099 | Anthony Liguori | uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
|
968 | c227f099 | Anthony Liguori | void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
969 | b30bb3a2 | balrog | uint32_t value); |
970 | b30bb3a2 | balrog | |
971 | 827df9f3 | balrog | void omap_mpu_wakeup(void *opaque, int irq, int req); |
972 | 827df9f3 | balrog | |
973 | c3d2689d | balrog | # define OMAP_BAD_REG(paddr) \
|
974 | 827df9f3 | balrog | fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ |
975 | 827df9f3 | balrog | __FUNCTION__, paddr) |
976 | c3d2689d | balrog | # define OMAP_RO_REG(paddr) \
|
977 | 827df9f3 | balrog | fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ |
978 | c3d2689d | balrog | __FUNCTION__, paddr) |
979 | b854bc19 | balrog | |
980 | 827df9f3 | balrog | /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
|
981 | 827df9f3 | balrog | (Board-specifc tags are not here) */
|
982 | 827df9f3 | balrog | #define OMAP_TAG_CLOCK 0x4f01 |
983 | 827df9f3 | balrog | #define OMAP_TAG_MMC 0x4f02 |
984 | 827df9f3 | balrog | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
985 | 827df9f3 | balrog | #define OMAP_TAG_USB 0x4f04 |
986 | 827df9f3 | balrog | #define OMAP_TAG_LCD 0x4f05 |
987 | 827df9f3 | balrog | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
988 | 827df9f3 | balrog | #define OMAP_TAG_UART 0x4f07 |
989 | 827df9f3 | balrog | #define OMAP_TAG_FBMEM 0x4f08 |
990 | 827df9f3 | balrog | #define OMAP_TAG_STI_CONSOLE 0x4f09 |
991 | 827df9f3 | balrog | #define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
992 | 827df9f3 | balrog | #define OMAP_TAG_PARTITION 0x4f0b |
993 | 827df9f3 | balrog | #define OMAP_TAG_TEA5761 0x4f10 |
994 | 827df9f3 | balrog | #define OMAP_TAG_TMP105 0x4f11 |
995 | 827df9f3 | balrog | #define OMAP_TAG_BOOT_REASON 0x4f80 |
996 | 827df9f3 | balrog | #define OMAP_TAG_FLASH_PART_STR 0x4f81 |
997 | 827df9f3 | balrog | #define OMAP_TAG_VERSION_STR 0x4f82 |
998 | 827df9f3 | balrog | |
999 | e927bb00 | balrog | enum {
|
1000 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_COVER = 0 << 4, |
1001 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, |
1002 | e927bb00 | balrog | OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, |
1003 | e927bb00 | balrog | }; |
1004 | e927bb00 | balrog | |
1005 | e927bb00 | balrog | #define OMAP_GPIOSW_INVERTED 0x0001 |
1006 | e927bb00 | balrog | #define OMAP_GPIOSW_OUTPUT 0x0002 |
1007 | e927bb00 | balrog | |
1008 | b854bc19 | balrog | # define TCMI_VERBOSE 1 |
1009 | d8f699cb | balrog | //# define MEM_VERBOSE 1
|
1010 | b854bc19 | balrog | |
1011 | b854bc19 | balrog | # ifdef TCMI_VERBOSE
|
1012 | b854bc19 | balrog | # define OMAP_8B_REG(paddr) \
|
1013 | 827df9f3 | balrog | fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ |
1014 | 66450b15 | balrog | __FUNCTION__, paddr) |
1015 | b854bc19 | balrog | # define OMAP_16B_REG(paddr) \
|
1016 | 827df9f3 | balrog | fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ |
1017 | c3d2689d | balrog | __FUNCTION__, paddr) |
1018 | b854bc19 | balrog | # define OMAP_32B_REG(paddr) \
|
1019 | 827df9f3 | balrog | fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ |
1020 | c3d2689d | balrog | __FUNCTION__, paddr) |
1021 | b854bc19 | balrog | # else
|
1022 | b854bc19 | balrog | # define OMAP_8B_REG(paddr)
|
1023 | b854bc19 | balrog | # define OMAP_16B_REG(paddr)
|
1024 | b854bc19 | balrog | # define OMAP_32B_REG(paddr)
|
1025 | b854bc19 | balrog | # endif
|
1026 | c3d2689d | balrog | |
1027 | cf965d24 | balrog | # define OMAP_MPUI_REG_MASK 0x000007ff |
1028 | cf965d24 | balrog | |
1029 | d8f699cb | balrog | # ifdef MEM_VERBOSE
|
1030 | d8f699cb | balrog | struct io_fn {
|
1031 | d60efc6b | Blue Swirl | CPUReadMemoryFunc * const *mem_read;
|
1032 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write;
|
1033 | d8f699cb | balrog | void *opaque;
|
1034 | d8f699cb | balrog | int in;
|
1035 | d8f699cb | balrog | }; |
1036 | d8f699cb | balrog | |
1037 | c227f099 | Anthony Liguori | static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
1038 | d8f699cb | balrog | { |
1039 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1040 | d8f699cb | balrog | uint32_t ret; |
1041 | d8f699cb | balrog | |
1042 | d8f699cb | balrog | s->in ++; |
1043 | d8f699cb | balrog | ret = s->mem_read[0](s->opaque, addr);
|
1044 | d8f699cb | balrog | s->in --; |
1045 | d8f699cb | balrog | if (!s->in)
|
1046 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
|
1047 | d8f699cb | balrog | return ret;
|
1048 | d8f699cb | balrog | } |
1049 | c227f099 | Anthony Liguori | static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
1050 | d8f699cb | balrog | { |
1051 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1052 | d8f699cb | balrog | uint32_t ret; |
1053 | d8f699cb | balrog | |
1054 | d8f699cb | balrog | s->in ++; |
1055 | d8f699cb | balrog | ret = s->mem_read[1](s->opaque, addr);
|
1056 | d8f699cb | balrog | s->in --; |
1057 | d8f699cb | balrog | if (!s->in)
|
1058 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
|
1059 | d8f699cb | balrog | return ret;
|
1060 | d8f699cb | balrog | } |
1061 | c227f099 | Anthony Liguori | static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
1062 | d8f699cb | balrog | { |
1063 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1064 | d8f699cb | balrog | uint32_t ret; |
1065 | d8f699cb | balrog | |
1066 | d8f699cb | balrog | s->in ++; |
1067 | d8f699cb | balrog | ret = s->mem_read[2](s->opaque, addr);
|
1068 | d8f699cb | balrog | s->in --; |
1069 | d8f699cb | balrog | if (!s->in)
|
1070 | d8f699cb | balrog | fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
|
1071 | d8f699cb | balrog | return ret;
|
1072 | d8f699cb | balrog | } |
1073 | c227f099 | Anthony Liguori | static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
1074 | d8f699cb | balrog | { |
1075 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1076 | d8f699cb | balrog | |
1077 | d8f699cb | balrog | if (!s->in)
|
1078 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
|
1079 | d8f699cb | balrog | s->in ++; |
1080 | d8f699cb | balrog | s->mem_write[0](s->opaque, addr, value);
|
1081 | d8f699cb | balrog | s->in --; |
1082 | d8f699cb | balrog | } |
1083 | c227f099 | Anthony Liguori | static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
1084 | d8f699cb | balrog | { |
1085 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1086 | d8f699cb | balrog | |
1087 | d8f699cb | balrog | if (!s->in)
|
1088 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
|
1089 | d8f699cb | balrog | s->in ++; |
1090 | d8f699cb | balrog | s->mem_write[1](s->opaque, addr, value);
|
1091 | d8f699cb | balrog | s->in --; |
1092 | d8f699cb | balrog | } |
1093 | c227f099 | Anthony Liguori | static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
1094 | d8f699cb | balrog | { |
1095 | d8f699cb | balrog | struct io_fn *s = opaque;
|
1096 | d8f699cb | balrog | |
1097 | d8f699cb | balrog | if (!s->in)
|
1098 | d8f699cb | balrog | fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
|
1099 | d8f699cb | balrog | s->in ++; |
1100 | d8f699cb | balrog | s->mem_write[2](s->opaque, addr, value);
|
1101 | d8f699cb | balrog | s->in --; |
1102 | d8f699cb | balrog | } |
1103 | d8f699cb | balrog | |
1104 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, }; |
1105 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, }; |
1106 | d8f699cb | balrog | |
1107 | d60efc6b | Blue Swirl | inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read, |
1108 | d60efc6b | Blue Swirl | CPUWriteMemoryFunc * const *mem_write,
|
1109 | d60efc6b | Blue Swirl | void *opaque)
|
1110 | d8f699cb | balrog | { |
1111 | 7267c094 | Anthony Liguori | struct io_fn *s = g_malloc(sizeof(struct io_fn)); |
1112 | d8f699cb | balrog | |
1113 | d8f699cb | balrog | s->mem_read = mem_read; |
1114 | d8f699cb | balrog | s->mem_write = mem_write; |
1115 | d8f699cb | balrog | s->opaque = opaque; |
1116 | d8f699cb | balrog | s->in = 0;
|
1117 | 2507c12a | Alexander Graf | return cpu_register_io_memory(io_readfn, io_writefn, s,
|
1118 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
1119 | d8f699cb | balrog | } |
1120 | d8f699cb | balrog | # define cpu_register_io_memory debug_register_io_memory
|
1121 | d8f699cb | balrog | # endif
|
1122 | d8f699cb | balrog | |
1123 | c66fb5bc | balrog | /* Define when we want to reduce the number of IO regions registered. */
|
1124 | 477b24ef | balrog | /*# define L4_MUX_HACK*/
|
1125 | c66fb5bc | balrog | |
1126 | c3d2689d | balrog | #endif /* hw_omap_h */ |