root / hw / etraxfs_eth.c @ 0dad6c35
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1 | a3ea5df5 | edgar_igl | /*
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2 | a3ea5df5 | edgar_igl | * QEMU ETRAX Ethernet Controller.
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3 | a3ea5df5 | edgar_igl | *
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4 | a3ea5df5 | edgar_igl | * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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5 | a3ea5df5 | edgar_igl | *
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6 | a3ea5df5 | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a3ea5df5 | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | a3ea5df5 | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | a3ea5df5 | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a3ea5df5 | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | a3ea5df5 | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | a3ea5df5 | edgar_igl | *
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13 | a3ea5df5 | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | a3ea5df5 | edgar_igl | * all copies or substantial portions of the Software.
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15 | a3ea5df5 | edgar_igl | *
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16 | a3ea5df5 | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a3ea5df5 | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a3ea5df5 | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a3ea5df5 | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a3ea5df5 | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a3ea5df5 | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a3ea5df5 | edgar_igl | * THE SOFTWARE.
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23 | a3ea5df5 | edgar_igl | */
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24 | a3ea5df5 | edgar_igl | |
25 | a3ea5df5 | edgar_igl | #include <stdio.h> |
26 | d949396e | Edgar E. Iglesias | #include "sysbus.h" |
27 | a3ea5df5 | edgar_igl | #include "net.h" |
28 | cc53adbc | edgar_igl | #include "etraxfs.h" |
29 | a3ea5df5 | edgar_igl | |
30 | a3ea5df5 | edgar_igl | #define D(x)
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31 | a3ea5df5 | edgar_igl | |
32 | c6488268 | edgar_igl | /* Advertisement control register. */
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33 | c6488268 | edgar_igl | #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
34 | c6488268 | edgar_igl | #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
35 | c6488268 | edgar_igl | #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
36 | c6488268 | edgar_igl | #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
37 | c6488268 | edgar_igl | |
38 | 2e56350e | edgar_igl | /*
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39 | 2e56350e | edgar_igl | * The MDIO extensions in the TDK PHY model were reversed engineered from the
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40 | 2e56350e | edgar_igl | * linux driver (PHYID and Diagnostics reg).
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41 | 2e56350e | edgar_igl | * TODO: Add friendly names for the register nums.
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42 | 2e56350e | edgar_igl | */
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43 | a3ea5df5 | edgar_igl | struct qemu_phy
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44 | a3ea5df5 | edgar_igl | { |
45 | a3ea5df5 | edgar_igl | uint32_t regs[32];
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46 | a3ea5df5 | edgar_igl | |
47 | 94410b78 | edgar_igl | int link;
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48 | 94410b78 | edgar_igl | |
49 | a3ea5df5 | edgar_igl | unsigned int (*read)(struct qemu_phy *phy, unsigned int req); |
50 | 2e56350e | edgar_igl | void (*write)(struct qemu_phy *phy, unsigned int req, |
51 | 2e56350e | edgar_igl | unsigned int data); |
52 | a3ea5df5 | edgar_igl | }; |
53 | a3ea5df5 | edgar_igl | |
54 | a3ea5df5 | edgar_igl | static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) |
55 | a3ea5df5 | edgar_igl | { |
56 | a3ea5df5 | edgar_igl | int regnum;
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57 | a3ea5df5 | edgar_igl | unsigned r = 0; |
58 | a3ea5df5 | edgar_igl | |
59 | a3ea5df5 | edgar_igl | regnum = req & 0x1f;
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60 | a3ea5df5 | edgar_igl | |
61 | a3ea5df5 | edgar_igl | switch (regnum) {
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62 | a3ea5df5 | edgar_igl | case 1: |
63 | 94410b78 | edgar_igl | if (!phy->link)
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64 | 94410b78 | edgar_igl | break;
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65 | f6953f13 | edgar_igl | /* MR1. */
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66 | a3ea5df5 | edgar_igl | /* Speeds and modes. */
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67 | a3ea5df5 | edgar_igl | r |= (1 << 13) | (1 << 14); |
68 | a3ea5df5 | edgar_igl | r |= (1 << 11) | (1 << 12); |
69 | a3ea5df5 | edgar_igl | r |= (1 << 5); /* Autoneg complete. */ |
70 | f6953f13 | edgar_igl | r |= (1 << 3); /* Autoneg able. */ |
71 | 94410b78 | edgar_igl | r |= (1 << 2); /* link. */ |
72 | a3ea5df5 | edgar_igl | break;
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73 | 2e56350e | edgar_igl | case 5: |
74 | 2e56350e | edgar_igl | /* Link partner ability.
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75 | 2e56350e | edgar_igl | We are kind; always agree with whatever best mode
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76 | 2e56350e | edgar_igl | the guest advertises. */
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77 | 2e56350e | edgar_igl | r = 1 << 14; /* Success. */ |
78 | 2e56350e | edgar_igl | /* Copy advertised modes. */
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79 | 2e56350e | edgar_igl | r |= phy->regs[4] & (15 << 5); |
80 | 2e56350e | edgar_igl | /* Autoneg support. */
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81 | 2e56350e | edgar_igl | r |= 1;
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82 | 2e56350e | edgar_igl | break;
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83 | 2e56350e | edgar_igl | case 18: |
84 | 2e56350e | edgar_igl | { |
85 | 2e56350e | edgar_igl | /* Diagnostics reg. */
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86 | 2e56350e | edgar_igl | int duplex = 0; |
87 | 2e56350e | edgar_igl | int speed_100 = 0; |
88 | 2e56350e | edgar_igl | |
89 | 94410b78 | edgar_igl | if (!phy->link)
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90 | 94410b78 | edgar_igl | break;
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91 | 94410b78 | edgar_igl | |
92 | 2e56350e | edgar_igl | /* Are we advertising 100 half or 100 duplex ? */
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93 | c6488268 | edgar_igl | speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
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94 | c6488268 | edgar_igl | speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
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95 | c6488268 | edgar_igl | |
96 | 2e56350e | edgar_igl | /* Are we advertising 10 duplex or 100 duplex ? */
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97 | c6488268 | edgar_igl | duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
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98 | c6488268 | edgar_igl | duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
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99 | 2e56350e | edgar_igl | r = (speed_100 << 10) | (duplex << 11); |
100 | 2e56350e | edgar_igl | } |
101 | 2e56350e | edgar_igl | break;
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102 | 2e56350e | edgar_igl | |
103 | a3ea5df5 | edgar_igl | default:
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104 | a3ea5df5 | edgar_igl | r = phy->regs[regnum]; |
105 | a3ea5df5 | edgar_igl | break;
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106 | a3ea5df5 | edgar_igl | } |
107 | 2e56350e | edgar_igl | D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
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108 | a3ea5df5 | edgar_igl | return r;
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109 | a3ea5df5 | edgar_igl | } |
110 | a3ea5df5 | edgar_igl | |
111 | a3ea5df5 | edgar_igl | static void |
112 | a3ea5df5 | edgar_igl | tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) |
113 | a3ea5df5 | edgar_igl | { |
114 | a3ea5df5 | edgar_igl | int regnum;
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115 | a3ea5df5 | edgar_igl | |
116 | a3ea5df5 | edgar_igl | regnum = req & 0x1f;
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117 | a3ea5df5 | edgar_igl | D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
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118 | a3ea5df5 | edgar_igl | switch (regnum) {
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119 | a3ea5df5 | edgar_igl | default:
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120 | a3ea5df5 | edgar_igl | phy->regs[regnum] = data; |
121 | a3ea5df5 | edgar_igl | break;
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122 | a3ea5df5 | edgar_igl | } |
123 | a3ea5df5 | edgar_igl | } |
124 | a3ea5df5 | edgar_igl | |
125 | a3ea5df5 | edgar_igl | static void |
126 | a3ea5df5 | edgar_igl | tdk_init(struct qemu_phy *phy)
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127 | a3ea5df5 | edgar_igl | { |
128 | 2e56350e | edgar_igl | phy->regs[0] = 0x3100; |
129 | 2e56350e | edgar_igl | /* PHY Id. */
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130 | 2e56350e | edgar_igl | phy->regs[2] = 0x0300; |
131 | 2e56350e | edgar_igl | phy->regs[3] = 0xe400; |
132 | 2e56350e | edgar_igl | /* Autonegotiation advertisement reg. */
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133 | 2e56350e | edgar_igl | phy->regs[4] = 0x01E1; |
134 | 94410b78 | edgar_igl | phy->link = 1;
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135 | 2e56350e | edgar_igl | |
136 | a3ea5df5 | edgar_igl | phy->read = tdk_read; |
137 | a3ea5df5 | edgar_igl | phy->write = tdk_write; |
138 | a3ea5df5 | edgar_igl | } |
139 | a3ea5df5 | edgar_igl | |
140 | a3ea5df5 | edgar_igl | struct qemu_mdio
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141 | a3ea5df5 | edgar_igl | { |
142 | f6953f13 | edgar_igl | /* bus. */
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143 | a3ea5df5 | edgar_igl | int mdc;
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144 | a3ea5df5 | edgar_igl | int mdio;
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145 | a3ea5df5 | edgar_igl | |
146 | a3ea5df5 | edgar_igl | /* decoder. */
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147 | a3ea5df5 | edgar_igl | enum {
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148 | a3ea5df5 | edgar_igl | PREAMBLE, |
149 | a3ea5df5 | edgar_igl | SOF, |
150 | a3ea5df5 | edgar_igl | OPC, |
151 | a3ea5df5 | edgar_igl | ADDR, |
152 | a3ea5df5 | edgar_igl | REQ, |
153 | a3ea5df5 | edgar_igl | TURNAROUND, |
154 | a3ea5df5 | edgar_igl | DATA |
155 | a3ea5df5 | edgar_igl | } state; |
156 | a3ea5df5 | edgar_igl | unsigned int drive; |
157 | a3ea5df5 | edgar_igl | |
158 | a3ea5df5 | edgar_igl | unsigned int cnt; |
159 | a3ea5df5 | edgar_igl | unsigned int addr; |
160 | a3ea5df5 | edgar_igl | unsigned int opc; |
161 | a3ea5df5 | edgar_igl | unsigned int req; |
162 | a3ea5df5 | edgar_igl | unsigned int data; |
163 | a3ea5df5 | edgar_igl | |
164 | a3ea5df5 | edgar_igl | struct qemu_phy *devs[32]; |
165 | a3ea5df5 | edgar_igl | }; |
166 | a3ea5df5 | edgar_igl | |
167 | a3ea5df5 | edgar_igl | static void |
168 | a3ea5df5 | edgar_igl | mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
169 | a3ea5df5 | edgar_igl | { |
170 | a3ea5df5 | edgar_igl | bus->devs[addr & 0x1f] = phy;
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171 | a3ea5df5 | edgar_igl | } |
172 | a3ea5df5 | edgar_igl | |
173 | d297f464 | edgar_igl | #ifdef USE_THIS_DEAD_CODE
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174 | a3ea5df5 | edgar_igl | static void |
175 | a3ea5df5 | edgar_igl | mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
176 | a3ea5df5 | edgar_igl | { |
177 | a3ea5df5 | edgar_igl | bus->devs[addr & 0x1f] = NULL; |
178 | a3ea5df5 | edgar_igl | } |
179 | d297f464 | edgar_igl | #endif
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180 | a3ea5df5 | edgar_igl | |
181 | a3ea5df5 | edgar_igl | static void mdio_read_req(struct qemu_mdio *bus) |
182 | a3ea5df5 | edgar_igl | { |
183 | a3ea5df5 | edgar_igl | struct qemu_phy *phy;
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184 | a3ea5df5 | edgar_igl | |
185 | a3ea5df5 | edgar_igl | phy = bus->devs[bus->addr]; |
186 | a3ea5df5 | edgar_igl | if (phy && phy->read)
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187 | a3ea5df5 | edgar_igl | bus->data = phy->read(phy, bus->req); |
188 | a3ea5df5 | edgar_igl | else
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189 | a3ea5df5 | edgar_igl | bus->data = 0xffff;
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190 | a3ea5df5 | edgar_igl | } |
191 | a3ea5df5 | edgar_igl | |
192 | a3ea5df5 | edgar_igl | static void mdio_write_req(struct qemu_mdio *bus) |
193 | a3ea5df5 | edgar_igl | { |
194 | a3ea5df5 | edgar_igl | struct qemu_phy *phy;
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195 | a3ea5df5 | edgar_igl | |
196 | a3ea5df5 | edgar_igl | phy = bus->devs[bus->addr]; |
197 | a3ea5df5 | edgar_igl | if (phy && phy->write)
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198 | a3ea5df5 | edgar_igl | phy->write(phy, bus->req, bus->data); |
199 | a3ea5df5 | edgar_igl | } |
200 | a3ea5df5 | edgar_igl | |
201 | a3ea5df5 | edgar_igl | static void mdio_cycle(struct qemu_mdio *bus) |
202 | a3ea5df5 | edgar_igl | { |
203 | a3ea5df5 | edgar_igl | bus->cnt++; |
204 | a3ea5df5 | edgar_igl | |
205 | a3ea5df5 | edgar_igl | D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
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206 | a3ea5df5 | edgar_igl | bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); |
207 | a3ea5df5 | edgar_igl | #if 0
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208 | a3ea5df5 | edgar_igl | if (bus->mdc)
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209 | a3ea5df5 | edgar_igl | printf("%d", bus->mdio);
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210 | a3ea5df5 | edgar_igl | #endif
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211 | a3ea5df5 | edgar_igl | switch (bus->state)
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212 | a3ea5df5 | edgar_igl | { |
213 | a3ea5df5 | edgar_igl | case PREAMBLE:
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214 | a3ea5df5 | edgar_igl | if (bus->mdc) {
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215 | a3ea5df5 | edgar_igl | if (bus->cnt >= (32 * 2) && !bus->mdio) { |
216 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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217 | a3ea5df5 | edgar_igl | bus->state = SOF; |
218 | a3ea5df5 | edgar_igl | bus->data = 0;
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219 | a3ea5df5 | edgar_igl | } |
220 | a3ea5df5 | edgar_igl | } |
221 | a3ea5df5 | edgar_igl | break;
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222 | a3ea5df5 | edgar_igl | case SOF:
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223 | a3ea5df5 | edgar_igl | if (bus->mdc) {
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224 | a3ea5df5 | edgar_igl | if (bus->mdio != 1) |
225 | a3ea5df5 | edgar_igl | printf("WARNING: no SOF\n");
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226 | a3ea5df5 | edgar_igl | if (bus->cnt == 1*2) { |
227 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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228 | a3ea5df5 | edgar_igl | bus->opc = 0;
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229 | a3ea5df5 | edgar_igl | bus->state = OPC; |
230 | a3ea5df5 | edgar_igl | } |
231 | a3ea5df5 | edgar_igl | } |
232 | a3ea5df5 | edgar_igl | break;
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233 | a3ea5df5 | edgar_igl | case OPC:
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234 | a3ea5df5 | edgar_igl | if (bus->mdc) {
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235 | a3ea5df5 | edgar_igl | bus->opc <<= 1;
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236 | a3ea5df5 | edgar_igl | bus->opc |= bus->mdio & 1;
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237 | a3ea5df5 | edgar_igl | if (bus->cnt == 2*2) { |
238 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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239 | a3ea5df5 | edgar_igl | bus->addr = 0;
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240 | a3ea5df5 | edgar_igl | bus->state = ADDR; |
241 | a3ea5df5 | edgar_igl | } |
242 | a3ea5df5 | edgar_igl | } |
243 | a3ea5df5 | edgar_igl | break;
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244 | a3ea5df5 | edgar_igl | case ADDR:
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245 | a3ea5df5 | edgar_igl | if (bus->mdc) {
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246 | a3ea5df5 | edgar_igl | bus->addr <<= 1;
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247 | a3ea5df5 | edgar_igl | bus->addr |= bus->mdio & 1;
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248 | a3ea5df5 | edgar_igl | |
249 | a3ea5df5 | edgar_igl | if (bus->cnt == 5*2) { |
250 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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251 | a3ea5df5 | edgar_igl | bus->req = 0;
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252 | a3ea5df5 | edgar_igl | bus->state = REQ; |
253 | a3ea5df5 | edgar_igl | } |
254 | a3ea5df5 | edgar_igl | } |
255 | a3ea5df5 | edgar_igl | break;
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256 | a3ea5df5 | edgar_igl | case REQ:
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257 | a3ea5df5 | edgar_igl | if (bus->mdc) {
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258 | a3ea5df5 | edgar_igl | bus->req <<= 1;
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259 | a3ea5df5 | edgar_igl | bus->req |= bus->mdio & 1;
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260 | a3ea5df5 | edgar_igl | if (bus->cnt == 5*2) { |
261 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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262 | a3ea5df5 | edgar_igl | bus->state = TURNAROUND; |
263 | a3ea5df5 | edgar_igl | } |
264 | a3ea5df5 | edgar_igl | } |
265 | a3ea5df5 | edgar_igl | break;
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266 | a3ea5df5 | edgar_igl | case TURNAROUND:
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267 | a3ea5df5 | edgar_igl | if (bus->mdc && bus->cnt == 2*2) { |
268 | a3ea5df5 | edgar_igl | bus->mdio = 0;
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269 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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270 | a3ea5df5 | edgar_igl | |
271 | a3ea5df5 | edgar_igl | if (bus->opc == 2) { |
272 | a3ea5df5 | edgar_igl | bus->drive = 1;
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273 | a3ea5df5 | edgar_igl | mdio_read_req(bus); |
274 | a3ea5df5 | edgar_igl | bus->mdio = bus->data & 1;
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275 | a3ea5df5 | edgar_igl | } |
276 | a3ea5df5 | edgar_igl | bus->state = DATA; |
277 | a3ea5df5 | edgar_igl | } |
278 | a3ea5df5 | edgar_igl | break;
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279 | a3ea5df5 | edgar_igl | case DATA:
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280 | a3ea5df5 | edgar_igl | if (!bus->mdc) {
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281 | a3ea5df5 | edgar_igl | if (bus->drive) {
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282 | 2e56350e | edgar_igl | bus->mdio = !!(bus->data & (1 << 15)); |
283 | 2e56350e | edgar_igl | bus->data <<= 1;
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284 | a3ea5df5 | edgar_igl | } |
285 | a3ea5df5 | edgar_igl | } else {
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286 | a3ea5df5 | edgar_igl | if (!bus->drive) {
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287 | a3ea5df5 | edgar_igl | bus->data <<= 1;
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288 | a3ea5df5 | edgar_igl | bus->data |= bus->mdio; |
289 | a3ea5df5 | edgar_igl | } |
290 | a3ea5df5 | edgar_igl | if (bus->cnt == 16 * 2) { |
291 | a3ea5df5 | edgar_igl | bus->cnt = 0;
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292 | a3ea5df5 | edgar_igl | bus->state = PREAMBLE; |
293 | 2e56350e | edgar_igl | if (!bus->drive)
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294 | 2e56350e | edgar_igl | mdio_write_req(bus); |
295 | 2e56350e | edgar_igl | bus->drive = 0;
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296 | a3ea5df5 | edgar_igl | } |
297 | a3ea5df5 | edgar_igl | } |
298 | a3ea5df5 | edgar_igl | break;
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299 | a3ea5df5 | edgar_igl | default:
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300 | a3ea5df5 | edgar_igl | break;
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301 | a3ea5df5 | edgar_igl | } |
302 | a3ea5df5 | edgar_igl | } |
303 | a3ea5df5 | edgar_igl | |
304 | 2e56350e | edgar_igl | /* ETRAX-FS Ethernet MAC block starts here. */
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305 | 2e56350e | edgar_igl | |
306 | f6953f13 | edgar_igl | #define RW_MA0_LO 0x00 |
307 | 35ef81d6 | edgar_igl | #define RW_MA0_HI 0x01 |
308 | 35ef81d6 | edgar_igl | #define RW_MA1_LO 0x02 |
309 | 35ef81d6 | edgar_igl | #define RW_MA1_HI 0x03 |
310 | 35ef81d6 | edgar_igl | #define RW_GA_LO 0x04 |
311 | 35ef81d6 | edgar_igl | #define RW_GA_HI 0x05 |
312 | 35ef81d6 | edgar_igl | #define RW_GEN_CTRL 0x06 |
313 | 35ef81d6 | edgar_igl | #define RW_REC_CTRL 0x07 |
314 | 35ef81d6 | edgar_igl | #define RW_TR_CTRL 0x08 |
315 | 35ef81d6 | edgar_igl | #define RW_CLR_ERR 0x09 |
316 | 35ef81d6 | edgar_igl | #define RW_MGM_CTRL 0x0a |
317 | 35ef81d6 | edgar_igl | #define R_STAT 0x0b |
318 | 35ef81d6 | edgar_igl | #define FS_ETH_MAX_REGS 0x17 |
319 | a3ea5df5 | edgar_igl | |
320 | a3ea5df5 | edgar_igl | struct fs_eth
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321 | a3ea5df5 | edgar_igl | { |
322 | d949396e | Edgar E. Iglesias | SysBusDevice busdev; |
323 | 06dccb82 | Edgar E. Iglesias | MemoryRegion mmio; |
324 | 163bf3a5 | Mark McLoughlin | NICState *nic; |
325 | 163bf3a5 | Mark McLoughlin | NICConf conf; |
326 | a3ea5df5 | edgar_igl | |
327 | f6953f13 | edgar_igl | /* Two addrs in the filter. */
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328 | f6953f13 | edgar_igl | uint8_t macaddr[2][6]; |
329 | a3ea5df5 | edgar_igl | uint32_t regs[FS_ETH_MAX_REGS]; |
330 | a3ea5df5 | edgar_igl | |
331 | d949396e | Edgar E. Iglesias | union {
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332 | d949396e | Edgar E. Iglesias | void *vdma_out;
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333 | d949396e | Edgar E. Iglesias | struct etraxfs_dma_client *dma_out;
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334 | d949396e | Edgar E. Iglesias | }; |
335 | d949396e | Edgar E. Iglesias | union {
|
336 | d949396e | Edgar E. Iglesias | void *vdma_in;
|
337 | d949396e | Edgar E. Iglesias | struct etraxfs_dma_client *dma_in;
|
338 | d949396e | Edgar E. Iglesias | }; |
339 | a3ea5df5 | edgar_igl | |
340 | a3ea5df5 | edgar_igl | /* MDIO bus. */
|
341 | a3ea5df5 | edgar_igl | struct qemu_mdio mdio_bus;
|
342 | c6488268 | edgar_igl | unsigned int phyaddr; |
343 | c6488268 | edgar_igl | int duplex_mismatch;
|
344 | c6488268 | edgar_igl | |
345 | f6953f13 | edgar_igl | /* PHY. */
|
346 | a3ea5df5 | edgar_igl | struct qemu_phy phy;
|
347 | a3ea5df5 | edgar_igl | }; |
348 | a3ea5df5 | edgar_igl | |
349 | c6488268 | edgar_igl | static void eth_validate_duplex(struct fs_eth *eth) |
350 | c6488268 | edgar_igl | { |
351 | c6488268 | edgar_igl | struct qemu_phy *phy;
|
352 | c6488268 | edgar_igl | unsigned int phy_duplex; |
353 | c6488268 | edgar_igl | unsigned int mac_duplex; |
354 | c6488268 | edgar_igl | int new_mm = 0; |
355 | c6488268 | edgar_igl | |
356 | c6488268 | edgar_igl | phy = eth->mdio_bus.devs[eth->phyaddr]; |
357 | c6488268 | edgar_igl | phy_duplex = !!(phy->read(phy, 18) & (1 << 11)); |
358 | c6488268 | edgar_igl | mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
|
359 | c6488268 | edgar_igl | |
360 | c6488268 | edgar_igl | if (mac_duplex != phy_duplex)
|
361 | c6488268 | edgar_igl | new_mm = 1;
|
362 | c6488268 | edgar_igl | |
363 | c6488268 | edgar_igl | if (eth->regs[RW_GEN_CTRL] & 1) { |
364 | c6488268 | edgar_igl | if (new_mm != eth->duplex_mismatch) {
|
365 | c6488268 | edgar_igl | if (new_mm)
|
366 | c6488268 | edgar_igl | printf("HW: WARNING "
|
367 | c6488268 | edgar_igl | "ETH duplex mismatch MAC=%d PHY=%d\n",
|
368 | c6488268 | edgar_igl | mac_duplex, phy_duplex); |
369 | c6488268 | edgar_igl | else
|
370 | c6488268 | edgar_igl | printf("HW: ETH duplex ok.\n");
|
371 | c6488268 | edgar_igl | } |
372 | c6488268 | edgar_igl | eth->duplex_mismatch = new_mm; |
373 | c6488268 | edgar_igl | } |
374 | c6488268 | edgar_igl | } |
375 | c6488268 | edgar_igl | |
376 | 06dccb82 | Edgar E. Iglesias | static uint64_t
|
377 | 06dccb82 | Edgar E. Iglesias | eth_read(void *opaque, target_phys_addr_t addr, unsigned int size) |
378 | a3ea5df5 | edgar_igl | { |
379 | f6953f13 | edgar_igl | struct fs_eth *eth = opaque;
|
380 | f6953f13 | edgar_igl | uint32_t r = 0;
|
381 | a3ea5df5 | edgar_igl | |
382 | 35ef81d6 | edgar_igl | addr >>= 2;
|
383 | 35ef81d6 | edgar_igl | |
384 | f6953f13 | edgar_igl | switch (addr) {
|
385 | a3ea5df5 | edgar_igl | case R_STAT:
|
386 | a3ea5df5 | edgar_igl | r = eth->mdio_bus.mdio & 1;
|
387 | a3ea5df5 | edgar_igl | break;
|
388 | f6953f13 | edgar_igl | default:
|
389 | a3ea5df5 | edgar_igl | r = eth->regs[addr]; |
390 | 35ef81d6 | edgar_igl | D(printf ("%s %x\n", __func__, addr * 4)); |
391 | f6953f13 | edgar_igl | break;
|
392 | f6953f13 | edgar_igl | } |
393 | f6953f13 | edgar_igl | return r;
|
394 | a3ea5df5 | edgar_igl | } |
395 | a3ea5df5 | edgar_igl | |
396 | f6953f13 | edgar_igl | static void eth_update_ma(struct fs_eth *eth, int ma) |
397 | f6953f13 | edgar_igl | { |
398 | f6953f13 | edgar_igl | int reg;
|
399 | f6953f13 | edgar_igl | int i = 0; |
400 | f6953f13 | edgar_igl | |
401 | f6953f13 | edgar_igl | ma &= 1;
|
402 | f6953f13 | edgar_igl | |
403 | f6953f13 | edgar_igl | reg = RW_MA0_LO; |
404 | f6953f13 | edgar_igl | if (ma)
|
405 | f6953f13 | edgar_igl | reg = RW_MA1_LO; |
406 | f6953f13 | edgar_igl | |
407 | f6953f13 | edgar_igl | eth->macaddr[ma][i++] = eth->regs[reg]; |
408 | f6953f13 | edgar_igl | eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
|
409 | f6953f13 | edgar_igl | eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
|
410 | f6953f13 | edgar_igl | eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
|
411 | 4af6e404 | Edgar E. Iglesias | eth->macaddr[ma][i++] = eth->regs[reg + 1];
|
412 | 0d84be5b | Blue Swirl | eth->macaddr[ma][i] = eth->regs[reg + 1] >> 8; |
413 | f6953f13 | edgar_igl | |
414 | f6953f13 | edgar_igl | D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
|
415 | f6953f13 | edgar_igl | eth->macaddr[ma][0], eth->macaddr[ma][1], |
416 | f6953f13 | edgar_igl | eth->macaddr[ma][2], eth->macaddr[ma][3], |
417 | f6953f13 | edgar_igl | eth->macaddr[ma][4], eth->macaddr[ma][5])); |
418 | a3ea5df5 | edgar_igl | } |
419 | a3ea5df5 | edgar_igl | |
420 | a3ea5df5 | edgar_igl | static void |
421 | 06dccb82 | Edgar E. Iglesias | eth_write(void *opaque, target_phys_addr_t addr,
|
422 | 06dccb82 | Edgar E. Iglesias | uint64_t val64, unsigned int size) |
423 | a3ea5df5 | edgar_igl | { |
424 | f6953f13 | edgar_igl | struct fs_eth *eth = opaque;
|
425 | 06dccb82 | Edgar E. Iglesias | uint32_t value = val64; |
426 | f6953f13 | edgar_igl | |
427 | 35ef81d6 | edgar_igl | addr >>= 2;
|
428 | f6953f13 | edgar_igl | switch (addr)
|
429 | f6953f13 | edgar_igl | { |
430 | f6953f13 | edgar_igl | case RW_MA0_LO:
|
431 | f6953f13 | edgar_igl | case RW_MA0_HI:
|
432 | f6953f13 | edgar_igl | eth->regs[addr] = value; |
433 | f6953f13 | edgar_igl | eth_update_ma(eth, 0);
|
434 | f6953f13 | edgar_igl | break;
|
435 | f6953f13 | edgar_igl | case RW_MA1_LO:
|
436 | f6953f13 | edgar_igl | case RW_MA1_HI:
|
437 | f6953f13 | edgar_igl | eth->regs[addr] = value; |
438 | f6953f13 | edgar_igl | eth_update_ma(eth, 1);
|
439 | f6953f13 | edgar_igl | break;
|
440 | a3ea5df5 | edgar_igl | |
441 | a3ea5df5 | edgar_igl | case RW_MGM_CTRL:
|
442 | a3ea5df5 | edgar_igl | /* Attach an MDIO/PHY abstraction. */
|
443 | a3ea5df5 | edgar_igl | if (value & 2) |
444 | a3ea5df5 | edgar_igl | eth->mdio_bus.mdio = value & 1;
|
445 | c6488268 | edgar_igl | if (eth->mdio_bus.mdc != (value & 4)) { |
446 | a3ea5df5 | edgar_igl | mdio_cycle(ð->mdio_bus); |
447 | c6488268 | edgar_igl | eth_validate_duplex(eth); |
448 | c6488268 | edgar_igl | } |
449 | a3ea5df5 | edgar_igl | eth->mdio_bus.mdc = !!(value & 4);
|
450 | cdcf9153 | Edgar E. Iglesias | eth->regs[addr] = value; |
451 | a3ea5df5 | edgar_igl | break;
|
452 | a3ea5df5 | edgar_igl | |
453 | c6488268 | edgar_igl | case RW_REC_CTRL:
|
454 | c6488268 | edgar_igl | eth->regs[addr] = value; |
455 | c6488268 | edgar_igl | eth_validate_duplex(eth); |
456 | c6488268 | edgar_igl | break;
|
457 | c6488268 | edgar_igl | |
458 | f6953f13 | edgar_igl | default:
|
459 | f6953f13 | edgar_igl | eth->regs[addr] = value; |
460 | 9bcd77d6 | edgar_igl | D(printf ("%s %x %x\n",
|
461 | 9bcd77d6 | edgar_igl | __func__, addr, value)); |
462 | f6953f13 | edgar_igl | break;
|
463 | f6953f13 | edgar_igl | } |
464 | f6953f13 | edgar_igl | } |
465 | f6953f13 | edgar_igl | |
466 | f6953f13 | edgar_igl | /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
|
467 | f6953f13 | edgar_igl | filter dropping group addresses we have not joined. The filter has 64
|
468 | f6953f13 | edgar_igl | bits (m). The has function is a simple nible xor of the group addr. */
|
469 | f6953f13 | edgar_igl | static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) |
470 | f6953f13 | edgar_igl | { |
471 | f6953f13 | edgar_igl | unsigned int hsh; |
472 | f6953f13 | edgar_igl | int m_individual = eth->regs[RW_REC_CTRL] & 4; |
473 | f6953f13 | edgar_igl | int match;
|
474 | f6953f13 | edgar_igl | |
475 | f6953f13 | edgar_igl | /* First bit on the wire of a MAC address signals multicast or
|
476 | f6953f13 | edgar_igl | physical address. */
|
477 | 9e84a470 | Blue Swirl | if (!m_individual && !(sa[0] & 1)) |
478 | f6953f13 | edgar_igl | return 0; |
479 | f6953f13 | edgar_igl | |
480 | f6953f13 | edgar_igl | /* Calculate the hash index for the GA registers. */
|
481 | f6953f13 | edgar_igl | hsh = 0;
|
482 | f6953f13 | edgar_igl | hsh ^= (*sa) & 0x3f;
|
483 | f6953f13 | edgar_igl | hsh ^= ((*sa) >> 6) & 0x03; |
484 | f6953f13 | edgar_igl | ++sa; |
485 | f6953f13 | edgar_igl | hsh ^= ((*sa) << 2) & 0x03c; |
486 | f6953f13 | edgar_igl | hsh ^= ((*sa) >> 4) & 0xf; |
487 | f6953f13 | edgar_igl | ++sa; |
488 | f6953f13 | edgar_igl | hsh ^= ((*sa) << 4) & 0x30; |
489 | f6953f13 | edgar_igl | hsh ^= ((*sa) >> 2) & 0x3f; |
490 | f6953f13 | edgar_igl | ++sa; |
491 | f6953f13 | edgar_igl | hsh ^= (*sa) & 0x3f;
|
492 | f6953f13 | edgar_igl | hsh ^= ((*sa) >> 6) & 0x03; |
493 | f6953f13 | edgar_igl | ++sa; |
494 | f6953f13 | edgar_igl | hsh ^= ((*sa) << 2) & 0x03c; |
495 | f6953f13 | edgar_igl | hsh ^= ((*sa) >> 4) & 0xf; |
496 | f6953f13 | edgar_igl | ++sa; |
497 | f6953f13 | edgar_igl | hsh ^= ((*sa) << 4) & 0x30; |
498 | f6953f13 | edgar_igl | hsh ^= ((*sa) >> 2) & 0x3f; |
499 | f6953f13 | edgar_igl | |
500 | f6953f13 | edgar_igl | hsh &= 63;
|
501 | f6953f13 | edgar_igl | if (hsh > 31) |
502 | f6953f13 | edgar_igl | match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); |
503 | f6953f13 | edgar_igl | else
|
504 | f6953f13 | edgar_igl | match = eth->regs[RW_GA_LO] & (1 << hsh);
|
505 | f6953f13 | edgar_igl | D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
|
506 | f6953f13 | edgar_igl | eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); |
507 | f6953f13 | edgar_igl | return match;
|
508 | a3ea5df5 | edgar_igl | } |
509 | a3ea5df5 | edgar_igl | |
510 | 163bf3a5 | Mark McLoughlin | static int eth_can_receive(VLANClientState *nc) |
511 | a3ea5df5 | edgar_igl | { |
512 | aa25cf46 | edgar_igl | return 1; |
513 | a3ea5df5 | edgar_igl | } |
514 | a3ea5df5 | edgar_igl | |
515 | 163bf3a5 | Mark McLoughlin | static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
516 | a3ea5df5 | edgar_igl | { |
517 | f6953f13 | edgar_igl | unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
518 | 163bf3a5 | Mark McLoughlin | struct fs_eth *eth = DO_UPCAST(NICState, nc, nc)->opaque;
|
519 | f6953f13 | edgar_igl | int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
520 | f6953f13 | edgar_igl | int use_ma1 = eth->regs[RW_REC_CTRL] & 2; |
521 | f6953f13 | edgar_igl | int r_bcast = eth->regs[RW_REC_CTRL] & 8; |
522 | f6953f13 | edgar_igl | |
523 | f6953f13 | edgar_igl | if (size < 12) |
524 | 4f1c942b | Mark McLoughlin | return -1; |
525 | f6953f13 | edgar_igl | |
526 | f6953f13 | edgar_igl | D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
|
527 | f6953f13 | edgar_igl | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
528 | f6953f13 | edgar_igl | use_ma0, use_ma1, r_bcast)); |
529 | f6953f13 | edgar_igl | |
530 | f6953f13 | edgar_igl | /* Does the frame get through the address filters? */
|
531 | f6953f13 | edgar_igl | if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) |
532 | f6953f13 | edgar_igl | && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) |
533 | f6953f13 | edgar_igl | && (!r_bcast || memcmp(buf, sa_bcast, 6))
|
534 | f6953f13 | edgar_igl | && !eth_match_groupaddr(eth, buf)) |
535 | 4f1c942b | Mark McLoughlin | return size;
|
536 | f6953f13 | edgar_igl | |
537 | aa25cf46 | edgar_igl | /* FIXME: Find another way to pass on the fake csum. */
|
538 | aa25cf46 | edgar_igl | etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1); |
539 | 4f1c942b | Mark McLoughlin | |
540 | 4f1c942b | Mark McLoughlin | return size;
|
541 | a3ea5df5 | edgar_igl | } |
542 | a3ea5df5 | edgar_igl | |
543 | 73a511de | Lars Persson | static int eth_tx_push(void *opaque, unsigned char *buf, int len, bool eop) |
544 | a3ea5df5 | edgar_igl | { |
545 | a3ea5df5 | edgar_igl | struct fs_eth *eth = opaque;
|
546 | a3ea5df5 | edgar_igl | |
547 | a3ea5df5 | edgar_igl | D(printf("%s buf=%p len=%d\n", __func__, buf, len));
|
548 | 163bf3a5 | Mark McLoughlin | qemu_send_packet(ð->nic->nc, buf, len); |
549 | a3ea5df5 | edgar_igl | return len;
|
550 | a3ea5df5 | edgar_igl | } |
551 | a3ea5df5 | edgar_igl | |
552 | 163bf3a5 | Mark McLoughlin | static void eth_set_link(VLANClientState *nc) |
553 | 94410b78 | edgar_igl | { |
554 | 163bf3a5 | Mark McLoughlin | struct fs_eth *eth = DO_UPCAST(NICState, nc, nc)->opaque;
|
555 | 163bf3a5 | Mark McLoughlin | D(printf("%s %d\n", __func__, nc->link_down));
|
556 | 163bf3a5 | Mark McLoughlin | eth->phy.link = !nc->link_down; |
557 | 94410b78 | edgar_igl | } |
558 | 94410b78 | edgar_igl | |
559 | 06dccb82 | Edgar E. Iglesias | static const MemoryRegionOps eth_ops = { |
560 | 06dccb82 | Edgar E. Iglesias | .read = eth_read, |
561 | 06dccb82 | Edgar E. Iglesias | .write = eth_write, |
562 | 06dccb82 | Edgar E. Iglesias | .endianness = DEVICE_LITTLE_ENDIAN, |
563 | 06dccb82 | Edgar E. Iglesias | .valid = { |
564 | 06dccb82 | Edgar E. Iglesias | .min_access_size = 4,
|
565 | 06dccb82 | Edgar E. Iglesias | .max_access_size = 4
|
566 | 06dccb82 | Edgar E. Iglesias | } |
567 | a3ea5df5 | edgar_igl | }; |
568 | a3ea5df5 | edgar_igl | |
569 | 163bf3a5 | Mark McLoughlin | static void eth_cleanup(VLANClientState *nc) |
570 | b946a153 | aliguori | { |
571 | 163bf3a5 | Mark McLoughlin | struct fs_eth *eth = DO_UPCAST(NICState, nc, nc)->opaque;
|
572 | b946a153 | aliguori | |
573 | 1da005b3 | Edgar E. Iglesias | /* Disconnect the client. */
|
574 | 1da005b3 | Edgar E. Iglesias | eth->dma_out->client.push = NULL;
|
575 | 1da005b3 | Edgar E. Iglesias | eth->dma_out->client.opaque = NULL;
|
576 | 1da005b3 | Edgar E. Iglesias | eth->dma_in->client.opaque = NULL;
|
577 | 1da005b3 | Edgar E. Iglesias | eth->dma_in->client.pull = NULL;
|
578 | 7267c094 | Anthony Liguori | g_free(eth); |
579 | b946a153 | aliguori | } |
580 | b946a153 | aliguori | |
581 | 163bf3a5 | Mark McLoughlin | static NetClientInfo net_etraxfs_info = {
|
582 | 163bf3a5 | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
583 | 163bf3a5 | Mark McLoughlin | .size = sizeof(NICState),
|
584 | 163bf3a5 | Mark McLoughlin | .can_receive = eth_can_receive, |
585 | 163bf3a5 | Mark McLoughlin | .receive = eth_receive, |
586 | 163bf3a5 | Mark McLoughlin | .cleanup = eth_cleanup, |
587 | 163bf3a5 | Mark McLoughlin | .link_status_changed = eth_set_link, |
588 | 163bf3a5 | Mark McLoughlin | }; |
589 | 163bf3a5 | Mark McLoughlin | |
590 | d949396e | Edgar E. Iglesias | static int fs_eth_init(SysBusDevice *dev) |
591 | a3ea5df5 | edgar_igl | { |
592 | d949396e | Edgar E. Iglesias | struct fs_eth *s = FROM_SYSBUS(typeof(*s), dev);
|
593 | a3ea5df5 | edgar_igl | |
594 | d949396e | Edgar E. Iglesias | if (!s->dma_out || !s->dma_in) {
|
595 | d949396e | Edgar E. Iglesias | hw_error("Unconnected ETRAX-FS Ethernet MAC.\n");
|
596 | d949396e | Edgar E. Iglesias | } |
597 | a3ea5df5 | edgar_igl | |
598 | d949396e | Edgar E. Iglesias | s->dma_out->client.push = eth_tx_push; |
599 | d949396e | Edgar E. Iglesias | s->dma_out->client.opaque = s; |
600 | d949396e | Edgar E. Iglesias | s->dma_in->client.opaque = s; |
601 | d949396e | Edgar E. Iglesias | s->dma_in->client.pull = NULL;
|
602 | a3ea5df5 | edgar_igl | |
603 | 06dccb82 | Edgar E. Iglesias | memory_region_init_io(&s->mmio, ð_ops, s, "etraxfs-eth", 0x5c); |
604 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->mmio); |
605 | a3ea5df5 | edgar_igl | |
606 | d949396e | Edgar E. Iglesias | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
607 | d949396e | Edgar E. Iglesias | s->nic = qemu_new_nic(&net_etraxfs_info, &s->conf, |
608 | f79f2bfc | Anthony Liguori | object_get_typename(OBJECT(s)), dev->qdev.id, s); |
609 | d949396e | Edgar E. Iglesias | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
610 | a3ea5df5 | edgar_igl | |
611 | d949396e | Edgar E. Iglesias | tdk_init(&s->phy); |
612 | d949396e | Edgar E. Iglesias | mdio_attach(&s->mdio_bus, &s->phy, s->phyaddr); |
613 | d949396e | Edgar E. Iglesias | return 0; |
614 | d949396e | Edgar E. Iglesias | } |
615 | a3ea5df5 | edgar_igl | |
616 | 999e12bb | Anthony Liguori | static Property etraxfs_eth_properties[] = {
|
617 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("phyaddr", struct fs_eth, phyaddr, 1), |
618 | 999e12bb | Anthony Liguori | DEFINE_PROP_PTR("dma_out", struct fs_eth, vdma_out), |
619 | 999e12bb | Anthony Liguori | DEFINE_PROP_PTR("dma_in", struct fs_eth, vdma_in), |
620 | 999e12bb | Anthony Liguori | DEFINE_NIC_PROPERTIES(struct fs_eth, conf),
|
621 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
622 | 999e12bb | Anthony Liguori | }; |
623 | 999e12bb | Anthony Liguori | |
624 | 999e12bb | Anthony Liguori | static void etraxfs_eth_class_init(ObjectClass *klass, void *data) |
625 | 999e12bb | Anthony Liguori | { |
626 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
627 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
628 | 999e12bb | Anthony Liguori | |
629 | 999e12bb | Anthony Liguori | k->init = fs_eth_init; |
630 | 39bffca2 | Anthony Liguori | dc->props = etraxfs_eth_properties; |
631 | 999e12bb | Anthony Liguori | } |
632 | 999e12bb | Anthony Liguori | |
633 | 39bffca2 | Anthony Liguori | static TypeInfo etraxfs_eth_info = {
|
634 | 39bffca2 | Anthony Liguori | .name = "etraxfs-eth",
|
635 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
636 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(struct fs_eth), |
637 | 39bffca2 | Anthony Liguori | .class_init = etraxfs_eth_class_init, |
638 | d949396e | Edgar E. Iglesias | }; |
639 | 163bf3a5 | Mark McLoughlin | |
640 | d949396e | Edgar E. Iglesias | static void etraxfs_eth_register(void) |
641 | d949396e | Edgar E. Iglesias | { |
642 | 39bffca2 | Anthony Liguori | type_register_static(&etraxfs_eth_info); |
643 | a3ea5df5 | edgar_igl | } |
644 | d949396e | Edgar E. Iglesias | |
645 | d949396e | Edgar E. Iglesias | device_init(etraxfs_eth_register) |