root / hw / sparc32_dma.c @ 0dad6c35
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1 | 67e999be | bellard | /*
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2 | 67e999be | bellard | * QEMU Sparc32 DMA controller emulation
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3 | 67e999be | bellard | *
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4 | 67e999be | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 67e999be | bellard | *
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6 | 6f57bbf4 | Artyom Tarasenko | * Modifications:
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7 | 6f57bbf4 | Artyom Tarasenko | * 2010-Feb-14 Artyom Tarasenko : reworked irq generation
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8 | 6f57bbf4 | Artyom Tarasenko | *
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9 | 67e999be | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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10 | 67e999be | bellard | * of this software and associated documentation files (the "Software"), to deal
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11 | 67e999be | bellard | * in the Software without restriction, including without limitation the rights
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12 | 67e999be | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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13 | 67e999be | bellard | * copies of the Software, and to permit persons to whom the Software is
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14 | 67e999be | bellard | * furnished to do so, subject to the following conditions:
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15 | 67e999be | bellard | *
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16 | 67e999be | bellard | * The above copyright notice and this permission notice shall be included in
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17 | 67e999be | bellard | * all copies or substantial portions of the Software.
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18 | 67e999be | bellard | *
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19 | 67e999be | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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20 | 67e999be | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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21 | 67e999be | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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22 | 67e999be | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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23 | 67e999be | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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24 | 67e999be | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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25 | 67e999be | bellard | * THE SOFTWARE.
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26 | 67e999be | bellard | */
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27 | 6f6260c7 | Blue Swirl | |
28 | 87ecb68b | pbrook | #include "hw.h" |
29 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
30 | 87ecb68b | pbrook | #include "sun4m.h" |
31 | 6f6260c7 | Blue Swirl | #include "sysbus.h" |
32 | 97bf4851 | Blue Swirl | #include "trace.h" |
33 | 67e999be | bellard | |
34 | 67e999be | bellard | /*
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35 | 67e999be | bellard | * This is the DMA controller part of chip STP2000 (Master I/O), also
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36 | 67e999be | bellard | * produced as NCR89C100. See
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37 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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38 | 67e999be | bellard | * and
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39 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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40 | 67e999be | bellard | */
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41 | 67e999be | bellard | |
42 | 5aca8c3b | blueswir1 | #define DMA_REGS 4 |
43 | 5aca8c3b | blueswir1 | #define DMA_SIZE (4 * sizeof(uint32_t)) |
44 | 09723aa1 | blueswir1 | /* We need the mask, because one instance of the device is not page
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45 | 09723aa1 | blueswir1 | aligned (ledma, start address 0x0010) */
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46 | 09723aa1 | blueswir1 | #define DMA_MASK (DMA_SIZE - 1) |
47 | e0087e61 | Bob Breuer | /* OBP says 0x20 bytes for ledma, the extras are aliased to espdma */
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48 | 86d1c388 | Bob Breuer | #define DMA_ETH_SIZE (8 * sizeof(uint32_t)) |
49 | 86d1c388 | Bob Breuer | #define DMA_MAX_REG_OFFSET (2 * DMA_SIZE - 1) |
50 | 67e999be | bellard | |
51 | 67e999be | bellard | #define DMA_VER 0xa0000000 |
52 | 67e999be | bellard | #define DMA_INTR 1 |
53 | 67e999be | bellard | #define DMA_INTREN 0x10 |
54 | 67e999be | bellard | #define DMA_WRITE_MEM 0x100 |
55 | 73d74342 | Blue Swirl | #define DMA_EN 0x200 |
56 | 67e999be | bellard | #define DMA_LOADED 0x04000000 |
57 | 5aca8c3b | blueswir1 | #define DMA_DRAIN_FIFO 0x40 |
58 | 67e999be | bellard | #define DMA_RESET 0x80 |
59 | 67e999be | bellard | |
60 | 65899fe3 | Artyom Tarasenko | /* XXX SCSI and ethernet should have different read-only bit masks */
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61 | 65899fe3 | Artyom Tarasenko | #define DMA_CSR_RO_MASK 0xfe000007 |
62 | 65899fe3 | Artyom Tarasenko | |
63 | 67e999be | bellard | typedef struct DMAState DMAState; |
64 | 67e999be | bellard | |
65 | 67e999be | bellard | struct DMAState {
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66 | 6f6260c7 | Blue Swirl | SysBusDevice busdev; |
67 | d6c5f066 | Avi Kivity | MemoryRegion iomem; |
68 | 67e999be | bellard | uint32_t dmaregs[DMA_REGS]; |
69 | 5aca8c3b | blueswir1 | qemu_irq irq; |
70 | 2d069bab | blueswir1 | void *iommu;
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71 | 73d74342 | Blue Swirl | qemu_irq gpio[2];
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72 | 86d1c388 | Bob Breuer | uint32_t is_ledma; |
73 | 73d74342 | Blue Swirl | }; |
74 | 73d74342 | Blue Swirl | |
75 | 73d74342 | Blue Swirl | enum {
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76 | 73d74342 | Blue Swirl | GPIO_RESET = 0,
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77 | 73d74342 | Blue Swirl | GPIO_DMA, |
78 | 67e999be | bellard | }; |
79 | 67e999be | bellard | |
80 | 9b94dc32 | bellard | /* Note: on sparc, the lance 16 bit bus is swapped */
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81 | c227f099 | Anthony Liguori | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
82 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
83 | 67e999be | bellard | { |
84 | 67e999be | bellard | DMAState *s = opaque; |
85 | 9b94dc32 | bellard | int i;
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86 | 67e999be | bellard | |
87 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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88 | 97bf4851 | Blue Swirl | trace_ledma_memory_read(addr); |
89 | 9b94dc32 | bellard | if (do_bswap) {
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90 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
91 | 9b94dc32 | bellard | } else {
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92 | 9b94dc32 | bellard | addr &= ~1;
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93 | 9b94dc32 | bellard | len &= ~1;
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94 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
95 | 9b94dc32 | bellard | for(i = 0; i < len; i += 2) { |
96 | 9b94dc32 | bellard | bswap16s((uint16_t *)(buf + i)); |
97 | 9b94dc32 | bellard | } |
98 | 9b94dc32 | bellard | } |
99 | 67e999be | bellard | } |
100 | 67e999be | bellard | |
101 | c227f099 | Anthony Liguori | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
102 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
103 | 67e999be | bellard | { |
104 | 67e999be | bellard | DMAState *s = opaque; |
105 | 9b94dc32 | bellard | int l, i;
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106 | 9b94dc32 | bellard | uint16_t tmp_buf[32];
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107 | 67e999be | bellard | |
108 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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109 | 97bf4851 | Blue Swirl | trace_ledma_memory_write(addr); |
110 | 9b94dc32 | bellard | if (do_bswap) {
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111 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, buf, len); |
112 | 9b94dc32 | bellard | } else {
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113 | 9b94dc32 | bellard | addr &= ~1;
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114 | 9b94dc32 | bellard | len &= ~1;
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115 | 9b94dc32 | bellard | while (len > 0) { |
116 | 9b94dc32 | bellard | l = len; |
117 | 9b94dc32 | bellard | if (l > sizeof(tmp_buf)) |
118 | 9b94dc32 | bellard | l = sizeof(tmp_buf);
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119 | 9b94dc32 | bellard | for(i = 0; i < l; i += 2) { |
120 | 9b94dc32 | bellard | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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121 | 9b94dc32 | bellard | } |
122 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); |
123 | 9b94dc32 | bellard | len -= l; |
124 | 9b94dc32 | bellard | buf += l; |
125 | 9b94dc32 | bellard | addr += l; |
126 | 9b94dc32 | bellard | } |
127 | 9b94dc32 | bellard | } |
128 | 67e999be | bellard | } |
129 | 67e999be | bellard | |
130 | 70c0de96 | blueswir1 | static void dma_set_irq(void *opaque, int irq, int level) |
131 | 67e999be | bellard | { |
132 | 67e999be | bellard | DMAState *s = opaque; |
133 | 70c0de96 | blueswir1 | if (level) {
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134 | 70c0de96 | blueswir1 | s->dmaregs[0] |= DMA_INTR;
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135 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTREN) { |
136 | 97bf4851 | Blue Swirl | trace_sparc32_dma_set_irq_raise(); |
137 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_raise(s->irq); |
138 | 6f57bbf4 | Artyom Tarasenko | } |
139 | 70c0de96 | blueswir1 | } else {
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140 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTR) { |
141 | 6f57bbf4 | Artyom Tarasenko | s->dmaregs[0] &= ~DMA_INTR;
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142 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTREN) { |
143 | 97bf4851 | Blue Swirl | trace_sparc32_dma_set_irq_lower(); |
144 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_lower(s->irq); |
145 | 6f57bbf4 | Artyom Tarasenko | } |
146 | 6f57bbf4 | Artyom Tarasenko | } |
147 | 70c0de96 | blueswir1 | } |
148 | 67e999be | bellard | } |
149 | 67e999be | bellard | |
150 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
151 | 67e999be | bellard | { |
152 | 67e999be | bellard | DMAState *s = opaque; |
153 | 67e999be | bellard | |
154 | 97bf4851 | Blue Swirl | trace_espdma_memory_read(s->dmaregs[1]);
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155 | 67e999be | bellard | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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156 | 67e999be | bellard | s->dmaregs[1] += len;
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157 | 67e999be | bellard | } |
158 | 67e999be | bellard | |
159 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
160 | 67e999be | bellard | { |
161 | 67e999be | bellard | DMAState *s = opaque; |
162 | 67e999be | bellard | |
163 | 97bf4851 | Blue Swirl | trace_espdma_memory_write(s->dmaregs[1]);
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164 | 67e999be | bellard | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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165 | 67e999be | bellard | s->dmaregs[1] += len;
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166 | 67e999be | bellard | } |
167 | 67e999be | bellard | |
168 | d6c5f066 | Avi Kivity | static uint64_t dma_mem_read(void *opaque, target_phys_addr_t addr, |
169 | d6c5f066 | Avi Kivity | unsigned size)
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170 | 67e999be | bellard | { |
171 | 67e999be | bellard | DMAState *s = opaque; |
172 | 67e999be | bellard | uint32_t saddr; |
173 | 67e999be | bellard | |
174 | 86d1c388 | Bob Breuer | if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
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175 | e0087e61 | Bob Breuer | /* aliased to espdma, but we can't get there from here */
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176 | e0087e61 | Bob Breuer | /* buggy driver if using undocumented behavior, just return 0 */
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177 | e0087e61 | Bob Breuer | trace_sparc32_dma_mem_readl(addr, 0);
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178 | e0087e61 | Bob Breuer | return 0; |
179 | 86d1c388 | Bob Breuer | } |
180 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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181 | 97bf4851 | Blue Swirl | trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]); |
182 | 67e999be | bellard | return s->dmaregs[saddr];
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183 | 67e999be | bellard | } |
184 | 67e999be | bellard | |
185 | d6c5f066 | Avi Kivity | static void dma_mem_write(void *opaque, target_phys_addr_t addr, |
186 | d6c5f066 | Avi Kivity | uint64_t val, unsigned size)
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187 | 67e999be | bellard | { |
188 | 67e999be | bellard | DMAState *s = opaque; |
189 | 67e999be | bellard | uint32_t saddr; |
190 | 67e999be | bellard | |
191 | 86d1c388 | Bob Breuer | if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {
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192 | e0087e61 | Bob Breuer | /* aliased to espdma, but we can't get there from here */
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193 | e0087e61 | Bob Breuer | trace_sparc32_dma_mem_writel(addr, 0, val);
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194 | e0087e61 | Bob Breuer | return;
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195 | 86d1c388 | Bob Breuer | } |
196 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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197 | 97bf4851 | Blue Swirl | trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val); |
198 | 67e999be | bellard | switch (saddr) {
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199 | 67e999be | bellard | case 0: |
200 | 6f57bbf4 | Artyom Tarasenko | if (val & DMA_INTREN) {
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201 | 65899fe3 | Artyom Tarasenko | if (s->dmaregs[0] & DMA_INTR) { |
202 | 97bf4851 | Blue Swirl | trace_sparc32_dma_set_irq_raise(); |
203 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_raise(s->irq); |
204 | 6f57bbf4 | Artyom Tarasenko | } |
205 | 6f57bbf4 | Artyom Tarasenko | } else {
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206 | 6f57bbf4 | Artyom Tarasenko | if (s->dmaregs[0] & (DMA_INTR | DMA_INTREN)) { |
207 | 97bf4851 | Blue Swirl | trace_sparc32_dma_set_irq_lower(); |
208 | 6f57bbf4 | Artyom Tarasenko | qemu_irq_lower(s->irq); |
209 | 6f57bbf4 | Artyom Tarasenko | } |
210 | d537cf6c | pbrook | } |
211 | 67e999be | bellard | if (val & DMA_RESET) {
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212 | 73d74342 | Blue Swirl | qemu_irq_raise(s->gpio[GPIO_RESET]); |
213 | 73d74342 | Blue Swirl | qemu_irq_lower(s->gpio[GPIO_RESET]); |
214 | 5aca8c3b | blueswir1 | } else if (val & DMA_DRAIN_FIFO) { |
215 | 5aca8c3b | blueswir1 | val &= ~DMA_DRAIN_FIFO; |
216 | 67e999be | bellard | } else if (val == 0) |
217 | 5aca8c3b | blueswir1 | val = DMA_DRAIN_FIFO; |
218 | 73d74342 | Blue Swirl | |
219 | 73d74342 | Blue Swirl | if (val & DMA_EN && !(s->dmaregs[0] & DMA_EN)) { |
220 | 97bf4851 | Blue Swirl | trace_sparc32_dma_enable_raise(); |
221 | 73d74342 | Blue Swirl | qemu_irq_raise(s->gpio[GPIO_DMA]); |
222 | 73d74342 | Blue Swirl | } else if (!(val & DMA_EN) && !!(s->dmaregs[0] & DMA_EN)) { |
223 | 97bf4851 | Blue Swirl | trace_sparc32_dma_enable_lower(); |
224 | 73d74342 | Blue Swirl | qemu_irq_lower(s->gpio[GPIO_DMA]); |
225 | 73d74342 | Blue Swirl | } |
226 | 73d74342 | Blue Swirl | |
227 | 65899fe3 | Artyom Tarasenko | val &= ~DMA_CSR_RO_MASK; |
228 | 67e999be | bellard | val |= DMA_VER; |
229 | 65899fe3 | Artyom Tarasenko | s->dmaregs[0] = (s->dmaregs[0] & DMA_CSR_RO_MASK) | val; |
230 | 67e999be | bellard | break;
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231 | 67e999be | bellard | case 1: |
232 | 67e999be | bellard | s->dmaregs[0] |= DMA_LOADED;
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233 | 65899fe3 | Artyom Tarasenko | /* fall through */
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234 | 67e999be | bellard | default:
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235 | 65899fe3 | Artyom Tarasenko | s->dmaregs[saddr] = val; |
236 | 67e999be | bellard | break;
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237 | 67e999be | bellard | } |
238 | 67e999be | bellard | } |
239 | 67e999be | bellard | |
240 | d6c5f066 | Avi Kivity | static const MemoryRegionOps dma_mem_ops = { |
241 | d6c5f066 | Avi Kivity | .read = dma_mem_read, |
242 | d6c5f066 | Avi Kivity | .write = dma_mem_write, |
243 | d6c5f066 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
244 | d6c5f066 | Avi Kivity | .valid = { |
245 | d6c5f066 | Avi Kivity | .min_access_size = 4,
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246 | d6c5f066 | Avi Kivity | .max_access_size = 4,
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247 | d6c5f066 | Avi Kivity | }, |
248 | 67e999be | bellard | }; |
249 | 67e999be | bellard | |
250 | 49ef6c90 | Blue Swirl | static void dma_reset(DeviceState *d) |
251 | 67e999be | bellard | { |
252 | 49ef6c90 | Blue Swirl | DMAState *s = container_of(d, DMAState, busdev.qdev); |
253 | 67e999be | bellard | |
254 | 5aca8c3b | blueswir1 | memset(s->dmaregs, 0, DMA_SIZE);
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255 | 67e999be | bellard | s->dmaregs[0] = DMA_VER;
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256 | 67e999be | bellard | } |
257 | 67e999be | bellard | |
258 | 75c497dc | Blue Swirl | static const VMStateDescription vmstate_dma = { |
259 | 75c497dc | Blue Swirl | .name ="sparc32_dma",
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260 | 75c497dc | Blue Swirl | .version_id = 2,
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261 | 75c497dc | Blue Swirl | .minimum_version_id = 2,
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262 | 75c497dc | Blue Swirl | .minimum_version_id_old = 2,
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263 | 75c497dc | Blue Swirl | .fields = (VMStateField []) { |
264 | 75c497dc | Blue Swirl | VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS), |
265 | 75c497dc | Blue Swirl | VMSTATE_END_OF_LIST() |
266 | 75c497dc | Blue Swirl | } |
267 | 75c497dc | Blue Swirl | }; |
268 | 67e999be | bellard | |
269 | 81a322d4 | Gerd Hoffmann | static int sparc32_dma_init1(SysBusDevice *dev) |
270 | 6f6260c7 | Blue Swirl | { |
271 | 6f6260c7 | Blue Swirl | DMAState *s = FROM_SYSBUS(DMAState, dev); |
272 | 86d1c388 | Bob Breuer | int reg_size;
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273 | 67e999be | bellard | |
274 | 6f6260c7 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
275 | 67e999be | bellard | |
276 | 86d1c388 | Bob Breuer | reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE; |
277 | d6c5f066 | Avi Kivity | memory_region_init_io(&s->iomem, &dma_mem_ops, s, "dma", reg_size);
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278 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
279 | 67e999be | bellard | |
280 | 6f6260c7 | Blue Swirl | qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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281 | 73d74342 | Blue Swirl | qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
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282 | 49ef6c90 | Blue Swirl | |
283 | 81a322d4 | Gerd Hoffmann | return 0; |
284 | 6f6260c7 | Blue Swirl | } |
285 | 67e999be | bellard | |
286 | 999e12bb | Anthony Liguori | static Property sparc32_dma_properties[] = {
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287 | 999e12bb | Anthony Liguori | DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
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288 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0), |
289 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
290 | 999e12bb | Anthony Liguori | }; |
291 | 999e12bb | Anthony Liguori | |
292 | 999e12bb | Anthony Liguori | static void sparc32_dma_class_init(ObjectClass *klass, void *data) |
293 | 999e12bb | Anthony Liguori | { |
294 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
295 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
296 | 999e12bb | Anthony Liguori | |
297 | 999e12bb | Anthony Liguori | k->init = sparc32_dma_init1; |
298 | 39bffca2 | Anthony Liguori | dc->reset = dma_reset; |
299 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_dma; |
300 | 39bffca2 | Anthony Liguori | dc->props = sparc32_dma_properties; |
301 | 999e12bb | Anthony Liguori | } |
302 | 999e12bb | Anthony Liguori | |
303 | 39bffca2 | Anthony Liguori | static TypeInfo sparc32_dma_info = {
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304 | 39bffca2 | Anthony Liguori | .name = "sparc32_dma",
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305 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
306 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(DMAState),
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307 | 39bffca2 | Anthony Liguori | .class_init = sparc32_dma_class_init, |
308 | 6f6260c7 | Blue Swirl | }; |
309 | 6f6260c7 | Blue Swirl | |
310 | 6f6260c7 | Blue Swirl | static void sparc32_dma_register_devices(void) |
311 | 6f6260c7 | Blue Swirl | { |
312 | 39bffca2 | Anthony Liguori | type_register_static(&sparc32_dma_info); |
313 | 67e999be | bellard | } |
314 | 6f6260c7 | Blue Swirl | |
315 | 6f6260c7 | Blue Swirl | device_init(sparc32_dma_register_devices) |