root / hw / unin_pci.c @ 0dad6c35
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/*
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* QEMU Uninorth PCI host (for all Mac99 and newer machines)
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "ppc_mac.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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/* debug UniNorth */
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//#define DEBUG_UNIN
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#ifdef DEBUG_UNIN
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#define UNIN_DPRINTF(fmt, ...) \
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do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define UNIN_DPRINTF(fmt, ...)
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#endif
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static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; |
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typedef struct UNINState { |
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PCIHostState host_state; |
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MemoryRegion pci_mmio; |
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MemoryRegion pci_hole; |
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} UNINState; |
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static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) |
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{ |
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int retval;
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int devfn = pci_dev->devfn & 0x00FFFFFF; |
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retval = (((devfn >> 11) & 0x1F) + irq_num) & 3; |
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return retval;
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} |
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static void pci_unin_set_irq(void *opaque, int irq_num, int level) |
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{ |
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qemu_irq *pic = opaque; |
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UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
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unin_irq_line[irq_num], level); |
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qemu_set_irq(pic[unin_irq_line[irq_num]], level); |
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} |
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static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
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{ |
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uint32_t retval; |
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if (reg & (1u << 31)) { |
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/* XXX OpenBIOS compatibility hack */
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retval = reg | (addr & 3);
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} else if (reg & 1) { |
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/* CFA1 style */
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retval = (reg & ~7u) | (addr & 7); |
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} else {
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uint32_t slot, func; |
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/* Grab CFA0 style values */
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slot = ffs(reg & 0xfffff800) - 1; |
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func = (reg >> 8) & 7; |
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/* ... and then convert them to x86 format */
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/* config pointer */
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retval = (reg & (0xff - 7)) | (addr & 7); |
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/* slot */
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retval |= slot << 11;
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/* fn */
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retval |= func << 8;
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} |
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UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
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reg, addr, retval); |
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return retval;
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} |
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static void unin_data_write(void *opaque, target_phys_addr_t addr, |
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uint64_t val, unsigned len)
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{ |
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UNINState *s = opaque; |
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UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n", |
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addr, len, val); |
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pci_data_write(s->host_state.bus, |
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unin_get_config_reg(s->host_state.config_reg, addr), |
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val, len); |
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} |
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static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr, |
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unsigned len)
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{ |
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UNINState *s = opaque; |
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uint32_t val; |
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val = pci_data_read(s->host_state.bus, |
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unin_get_config_reg(s->host_state.config_reg, addr), |
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len); |
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UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n", |
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addr, len, val); |
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return val;
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} |
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static const MemoryRegionOps unin_data_ops = { |
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.read = unin_data_read, |
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.write = unin_data_write, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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}; |
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static int pci_unin_main_init_device(SysBusDevice *dev) |
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{ |
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PCIHostState *h; |
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UNINState *s; |
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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h = FROM_SYSBUS(PCIHostState, dev); |
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s = DO_UPCAST(UNINState, host_state, h); |
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memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, |
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&s->host_state, "pci-conf-idx", 0x1000); |
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memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s, |
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"pci-conf-data", 0x1000); |
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sysbus_init_mmio(dev, &s->host_state.conf_mem); |
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sysbus_init_mmio(dev, &s->host_state.data_mem); |
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return 0; |
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} |
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static int pci_u3_agp_init_device(SysBusDevice *dev) |
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{ |
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PCIHostState *h; |
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UNINState *s; |
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/* Uninorth U3 AGP bus */
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h = FROM_SYSBUS(PCIHostState, dev); |
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s = DO_UPCAST(UNINState, host_state, h); |
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memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, |
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&s->host_state, "pci-conf-idx", 0x1000); |
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memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s, |
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"pci-conf-data", 0x1000); |
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sysbus_init_mmio(dev, &s->host_state.conf_mem); |
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sysbus_init_mmio(dev, &s->host_state.data_mem); |
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return 0; |
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} |
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static int pci_unin_agp_init_device(SysBusDevice *dev) |
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{ |
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PCIHostState *h; |
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UNINState *s; |
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/* Uninorth AGP bus */
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h = FROM_SYSBUS(PCIHostState, dev); |
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s = DO_UPCAST(UNINState, host_state, h); |
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memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, |
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&s->host_state, "pci-conf-idx", 0x1000); |
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memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, |
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&s->host_state, "pci-conf-data", 0x1000); |
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sysbus_init_mmio(dev, &s->host_state.conf_mem); |
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sysbus_init_mmio(dev, &s->host_state.data_mem); |
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return 0; |
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} |
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static int pci_unin_internal_init_device(SysBusDevice *dev) |
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{ |
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PCIHostState *h; |
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UNINState *s; |
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/* Uninorth internal bus */
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h = FROM_SYSBUS(PCIHostState, dev); |
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s = DO_UPCAST(UNINState, host_state, h); |
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memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, |
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&s->host_state, "pci-conf-idx", 0x1000); |
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memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, |
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&s->host_state, "pci-conf-data", 0x1000); |
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sysbus_init_mmio(dev, &s->host_state.conf_mem); |
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sysbus_init_mmio(dev, &s->host_state.data_mem); |
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return 0; |
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} |
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PCIBus *pci_pmac_init(qemu_irq *pic, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
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PCIHostState *h; |
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UNINState *d; |
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/* Use values found on a real PowerMac */
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/* Uninorth main bus */
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dev = qdev_create(NULL, "uni-north-pci-pcihost"); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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h = FROM_SYSBUS(PCIHostState, s); |
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d = DO_UPCAST(UNINState, host_state, h); |
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memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); |
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memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
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0x80000000ULL, 0x70000000ULL); |
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memory_region_add_subregion(address_space_mem, 0x80000000ULL,
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&d->pci_hole); |
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d->host_state.bus = pci_register_bus(dev, "pci",
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pci_unin_set_irq, pci_unin_map_irq, |
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pic, |
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&d->pci_mmio, |
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address_space_io, |
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PCI_DEVFN(11, 0), 4); |
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#if 0
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pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
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#endif
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sysbus_mmio_map(s, 0, 0xf2800000); |
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sysbus_mmio_map(s, 1, 0xf2c00000); |
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/* DEC 21154 bridge */
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#if 0
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/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
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pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
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#endif
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/* Uninorth AGP bus */
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pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp"); |
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dev = qdev_create(NULL, "uni-north-agp-pcihost"); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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sysbus_mmio_map(s, 0, 0xf0800000); |
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sysbus_mmio_map(s, 1, 0xf0c00000); |
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/* Uninorth internal bus */
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#if 0
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/* XXX: not needed for now */
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pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0),
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"uni-north-internal-pci");
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dev = qdev_create(NULL, "uni-north-internal-pci-pcihost");
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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sysbus_mmio_map(s, 0, 0xf4800000);
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sysbus_mmio_map(s, 1, 0xf4c00000);
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#endif
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return d->host_state.bus;
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} |
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PCIBus *pci_pmac_u3_init(qemu_irq *pic, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io) |
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{ |
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DeviceState *dev; |
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SysBusDevice *s; |
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PCIHostState *h; |
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UNINState *d; |
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/* Uninorth AGP bus */
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dev = qdev_create(NULL, "u3-agp-pcihost"); |
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev); |
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h = FROM_SYSBUS(PCIHostState, s); |
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d = DO_UPCAST(UNINState, host_state, h); |
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memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); |
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memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
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0x80000000ULL, 0x70000000ULL); |
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memory_region_add_subregion(address_space_mem, 0x80000000ULL,
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&d->pci_hole); |
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d->host_state.bus = pci_register_bus(dev, "pci",
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pci_unin_set_irq, pci_unin_map_irq, |
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pic, |
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&d->pci_mmio, |
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address_space_io, |
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PCI_DEVFN(11, 0), 4); |
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sysbus_mmio_map(s, 0, 0xf0800000); |
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sysbus_mmio_map(s, 1, 0xf0c00000); |
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pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp"); |
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return d->host_state.bus;
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} |
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static int unin_main_pci_host_init(PCIDevice *d) |
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{ |
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d->config[0x0C] = 0x08; // cache_line_size |
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d->config[0x0D] = 0x10; // latency_timer |
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d->config[0x34] = 0x00; // capabilities_pointer |
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return 0; |
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} |
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static int unin_agp_pci_host_init(PCIDevice *d) |
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{ |
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d->config[0x0C] = 0x08; // cache_line_size |
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d->config[0x0D] = 0x10; // latency_timer |
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// d->config[0x34] = 0x80; // capabilities_pointer
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return 0; |
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} |
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static int u3_agp_pci_host_init(PCIDevice *d) |
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{ |
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/* cache line size */
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d->config[0x0C] = 0x08; |
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/* latency timer */
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d->config[0x0D] = 0x10; |
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return 0; |
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} |
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static int unin_internal_pci_host_init(PCIDevice *d) |
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{ |
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d->config[0x0C] = 0x08; // cache_line_size |
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d->config[0x0D] = 0x10; // latency_timer |
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d->config[0x34] = 0x00; // capabilities_pointer |
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return 0; |
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} |
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static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) |
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{ |
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
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k->init = unin_main_pci_host_init; |
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k->vendor_id = PCI_VENDOR_ID_APPLE; |
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k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI; |
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST; |
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} |
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static TypeInfo unin_main_pci_host_info = {
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.name = "uni-north-pci",
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.parent = TYPE_PCI_DEVICE, |
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_main_pci_host_class_init, |
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}; |
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static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) |
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{ |
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
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k->init = u3_agp_pci_host_init; |
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k->vendor_id = PCI_VENDOR_ID_APPLE; |
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k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP; |
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST; |
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} |
370 |
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static TypeInfo u3_agp_pci_host_info = {
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.name = "u3-agp",
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.parent = TYPE_PCI_DEVICE, |
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.instance_size = sizeof(PCIDevice),
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.class_init = u3_agp_pci_host_class_init, |
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}; |
377 |
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static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) |
379 |
{ |
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
381 |
|
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k->init = unin_agp_pci_host_init; |
383 |
k->vendor_id = PCI_VENDOR_ID_APPLE; |
384 |
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP; |
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST; |
387 |
} |
388 |
|
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static TypeInfo unin_agp_pci_host_info = {
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.name = "uni-north-agp",
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.parent = TYPE_PCI_DEVICE, |
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.instance_size = sizeof(PCIDevice),
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.class_init = unin_agp_pci_host_class_init, |
394 |
}; |
395 |
|
396 |
static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) |
397 |
{ |
398 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
399 |
|
400 |
k->init = unin_internal_pci_host_init; |
401 |
k->vendor_id = PCI_VENDOR_ID_APPLE; |
402 |
k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI; |
403 |
k->revision = 0x00;
|
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k->class_id = PCI_CLASS_BRIDGE_HOST; |
405 |
} |
406 |
|
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static TypeInfo unin_internal_pci_host_info = {
|
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.name = "uni-north-internal-pci",
|
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.parent = TYPE_PCI_DEVICE, |
410 |
.instance_size = sizeof(PCIDevice),
|
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.class_init = unin_internal_pci_host_class_init, |
412 |
}; |
413 |
|
414 |
static void pci_unin_main_class_init(ObjectClass *klass, void *data) |
415 |
{ |
416 |
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
417 |
|
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sbc->init = pci_unin_main_init_device; |
419 |
} |
420 |
|
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static TypeInfo pci_unin_main_info = {
|
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.name = "uni-north-pci-pcihost",
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.parent = TYPE_SYS_BUS_DEVICE, |
424 |
.instance_size = sizeof(UNINState),
|
425 |
.class_init = pci_unin_main_class_init, |
426 |
}; |
427 |
|
428 |
static void pci_u3_agp_class_init(ObjectClass *klass, void *data) |
429 |
{ |
430 |
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
431 |
|
432 |
sbc->init = pci_u3_agp_init_device; |
433 |
} |
434 |
|
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static TypeInfo pci_u3_agp_info = {
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.name = "u3-agp-pcihost",
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.parent = TYPE_SYS_BUS_DEVICE, |
438 |
.instance_size = sizeof(UNINState),
|
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.class_init = pci_u3_agp_class_init, |
440 |
}; |
441 |
|
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static void pci_unin_agp_class_init(ObjectClass *klass, void *data) |
443 |
{ |
444 |
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
445 |
|
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sbc->init = pci_unin_agp_init_device; |
447 |
} |
448 |
|
449 |
static TypeInfo pci_unin_agp_info = {
|
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.name = "uni-north-agp-pcihost",
|
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.parent = TYPE_SYS_BUS_DEVICE, |
452 |
.instance_size = sizeof(UNINState),
|
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.class_init = pci_unin_agp_class_init, |
454 |
}; |
455 |
|
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static void pci_unin_internal_class_init(ObjectClass *klass, void *data) |
457 |
{ |
458 |
SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
459 |
|
460 |
sbc->init = pci_unin_internal_init_device; |
461 |
} |
462 |
|
463 |
static TypeInfo pci_unin_internal_info = {
|
464 |
.name = "uni-north-internal-pci-pcihost",
|
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.parent = TYPE_SYS_BUS_DEVICE, |
466 |
.instance_size = sizeof(UNINState),
|
467 |
.class_init = pci_unin_internal_class_init, |
468 |
}; |
469 |
|
470 |
static void unin_register_devices(void) |
471 |
{ |
472 |
type_register_static(&unin_main_pci_host_info); |
473 |
type_register_static(&u3_agp_pci_host_info); |
474 |
type_register_static(&unin_agp_pci_host_info); |
475 |
type_register_static(&unin_internal_pci_host_info); |
476 |
|
477 |
type_register_static(&pci_unin_main_info); |
478 |
type_register_static(&pci_u3_agp_info); |
479 |
type_register_static(&pci_unin_agp_info); |
480 |
type_register_static(&pci_unin_internal_info); |
481 |
} |
482 |
|
483 |
device_init(unin_register_devices) |