root / hw / vt82c686.c @ 0dad6c35
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/*
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* VT82C686B south bridge support
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*
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* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
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* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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* This code is licensed under the GNU GPL v2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "vt82c686.h" |
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#include "i2c.h" |
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#include "smbus.h" |
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#include "pci.h" |
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#include "isa.h" |
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#include "sysbus.h" |
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#include "mips.h" |
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#include "apm.h" |
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#include "acpi.h" |
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#include "pm_smbus.h" |
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#include "sysemu.h" |
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#include "qemu-timer.h" |
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typedef uint32_t pci_addr_t;
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#include "pci_host.h" |
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//#define DEBUG_VT82C686B
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#ifdef DEBUG_VT82C686B
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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typedef struct SuperIOConfig |
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{ |
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uint8_t config[0xff];
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uint8_t index; |
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uint8_t data; |
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} SuperIOConfig; |
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typedef struct VT82C686BState { |
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PCIDevice dev; |
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SuperIOConfig superio_conf; |
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} VT82C686BState; |
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|
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static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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int can_write;
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SuperIOConfig *superio_conf = opaque; |
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DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
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if (addr == 0x3f0) { |
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superio_conf->index = data & 0xff;
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} else {
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/* 0x3f1 */
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switch (superio_conf->index) {
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case 0x00 ... 0xdf: |
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case 0xe4: |
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case 0xe5: |
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case 0xe9 ... 0xed: |
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case 0xf3: |
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case 0xf5: |
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case 0xf7: |
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case 0xf9 ... 0xfb: |
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case 0xfd ... 0xff: |
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can_write = 0;
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break;
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default:
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can_write = 1;
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if (can_write) {
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switch (superio_conf->index) {
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case 0xe7: |
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if ((data & 0xff) != 0xfe) { |
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DPRINTF("chage uart 1 base. unsupported yet\n");
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} |
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break;
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case 0xe8: |
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if ((data & 0xff) != 0xbe) { |
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DPRINTF("chage uart 2 base. unsupported yet\n");
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} |
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break;
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default:
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superio_conf->config[superio_conf->index] = data & 0xff;
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} |
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} |
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} |
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superio_conf->config[superio_conf->index] = data & 0xff;
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} |
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} |
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static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) |
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{ |
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SuperIOConfig *superio_conf = opaque; |
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DPRINTF("superio_ioport_readb address 0x%x\n", addr);
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return (superio_conf->config[superio_conf->index]);
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} |
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static void vt82c686b_reset(void * opaque) |
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{ |
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PCIDevice *d = opaque; |
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uint8_t *pci_conf = d->config; |
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VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); |
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ |
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ |
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ |
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ |
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pci_conf[0x59] = 0x04; |
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ |
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pci_conf[0x5f] = 0x04; |
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ |
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vt82c->superio_conf.config[0xe0] = 0x3c; |
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vt82c->superio_conf.config[0xe2] = 0x03; |
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vt82c->superio_conf.config[0xe3] = 0xfc; |
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vt82c->superio_conf.config[0xe6] = 0xde; |
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vt82c->superio_conf.config[0xe7] = 0xfe; |
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vt82c->superio_conf.config[0xe8] = 0xbe; |
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} |
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice * d, uint32_t address, |
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uint32_t val, int len)
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{ |
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VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); |
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DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
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address, val, len); |
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pci_default_write_config(d, address, val, len); |
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if (address == 0x85) { /* enable or disable super IO configure */ |
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if (val & 0x2) { |
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/* floppy also uses 0x3f0 and 0x3f1.
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* But we do not emulate flopy,so just set it here. */
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isa_unassign_ioport(0x3f0, 2); |
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register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, |
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&vt686->superio_conf); |
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register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, |
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&vt686->superio_conf); |
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} else {
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isa_unassign_ioport(0x3f0, 2); |
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} |
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} |
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} |
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#define ACPI_DBG_IO_ADDR 0xb044 |
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typedef struct VT686PMState { |
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PCIDevice dev; |
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ACPIPM1EVT pm1a; |
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ACPIPM1CNT pm1_cnt; |
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APMState apm; |
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ACPIPMTimer tmr; |
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PMSMBus smb; |
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uint32_t smb_io_base; |
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} VT686PMState; |
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typedef struct VT686AC97State { |
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PCIDevice dev; |
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} VT686AC97State; |
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typedef struct VT686MC97State { |
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PCIDevice dev; |
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} VT686MC97State; |
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static void pm_update_sci(VT686PMState *s) |
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{ |
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int sci_level, pmsts;
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pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
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sci_level = (((pmsts & s->pm1a.en) & |
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(ACPI_BITMASK_RT_CLOCK_ENABLE | |
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ACPI_BITMASK_POWER_BUTTON_ENABLE | |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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qemu_set_irq(s->dev.irq[0], sci_level);
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/* schedule a timer interruption if needed */
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acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) && |
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!(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
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} |
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static void pm_tmr_timer(ACPIPMTimer *tmr) |
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{ |
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VT686PMState *s = container_of(tmr, VT686PMState, tmr); |
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pm_update_sci(s); |
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} |
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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VT686PMState *s = opaque; |
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addr &= 0x0f;
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switch (addr) {
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case 0x00: |
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acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val); |
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pm_update_sci(s); |
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break;
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case 0x02: |
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s->pm1a.en = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val); |
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break;
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default:
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break;
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} |
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DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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VT686PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x0f;
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switch (addr) {
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case 0x00: |
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val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
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break;
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case 0x02: |
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val = s->pm1a.en; |
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break;
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case 0x04: |
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val = s->pm1_cnt.cnt; |
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break;
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default:
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val = 0;
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break;
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} |
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DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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addr &= 0x0f;
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DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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VT686PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x0f;
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switch (addr) {
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case 0x08: |
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val = acpi_pm_tmr_get(&s->tmr); |
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break;
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default:
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val = 0;
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break;
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} |
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DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val;
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} |
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static void pm_io_space_update(VT686PMState *s) |
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{ |
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uint32_t pm_io_base; |
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if (s->dev.config[0x80] & 1) { |
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pm_io_base = pci_get_long(s->dev.config + 0x40);
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
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} |
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} |
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static void pm_write_config(PCIDevice *d, |
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uint32_t address, uint32_t val, int len)
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{ |
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DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
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address, val, len); |
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pci_default_write_config(d, address, val, len); |
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} |
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static int vmstate_acpi_post_load(void *opaque, int version_id) |
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{ |
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VT686PMState *s = opaque; |
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pm_io_space_update(s); |
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return 0; |
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} |
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static const VMStateDescription vmstate_acpi = { |
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.name = "vt82c686b_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, VT686PMState), |
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VMSTATE_UINT16(pm1a.sts, VT686PMState), |
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VMSTATE_UINT16(pm1a.en, VT686PMState), |
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VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState), |
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr.timer, VT686PMState), |
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VMSTATE_INT64(tmr.overflow_time, VT686PMState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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|
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/*
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* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
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* just register a PCI device now, functionalities will be implemented later.
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*/
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static int vt82c686b_ac97_initfn(PCIDevice *dev) |
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{ |
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VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); |
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uint8_t *pci_conf = s->dev.config; |
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
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PCI_COMMAND_PARITY); |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | |
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PCI_STATUS_DEVSEL_MEDIUM); |
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pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
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return 0; |
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} |
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|
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void vt82c686b_ac97_init(PCIBus *bus, int devfn) |
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{ |
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PCIDevice *dev; |
344 |
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dev = pci_create(bus, devfn, "VT82C686B_AC97");
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qdev_init_nofail(&dev->qdev); |
347 |
} |
348 |
|
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static void via_ac97_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
353 |
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k->init = vt82c686b_ac97_initfn; |
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k->vendor_id = PCI_VENDOR_ID_VIA; |
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k->device_id = PCI_DEVICE_ID_VIA_AC97; |
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k->revision = 0x50;
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k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; |
359 |
dc->desc = "AC97";
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} |
361 |
|
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static TypeInfo via_ac97_info = {
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.name = "VT82C686B_AC97",
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.parent = TYPE_PCI_DEVICE, |
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.instance_size = sizeof(VT686AC97State),
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.class_init = via_ac97_class_init, |
367 |
}; |
368 |
|
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static void vt82c686b_ac97_register(void) |
370 |
{ |
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type_register_static(&via_ac97_info); |
372 |
} |
373 |
|
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device_init(vt82c686b_ac97_register); |
375 |
|
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static int vt82c686b_mc97_initfn(PCIDevice *dev) |
377 |
{ |
378 |
VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); |
379 |
uint8_t *pci_conf = s->dev.config; |
380 |
|
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
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PCI_COMMAND_VGA_PALETTE); |
383 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
384 |
pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
|
385 |
|
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return 0; |
387 |
} |
388 |
|
389 |
void vt82c686b_mc97_init(PCIBus *bus, int devfn) |
390 |
{ |
391 |
PCIDevice *dev; |
392 |
|
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dev = pci_create(bus, devfn, "VT82C686B_MC97");
|
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qdev_init_nofail(&dev->qdev); |
395 |
} |
396 |
|
397 |
static void via_mc97_class_init(ObjectClass *klass, void *data) |
398 |
{ |
399 |
DeviceClass *dc = DEVICE_CLASS(klass); |
400 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
401 |
|
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k->init = vt82c686b_mc97_initfn; |
403 |
k->vendor_id = PCI_VENDOR_ID_VIA; |
404 |
k->device_id = PCI_DEVICE_ID_VIA_MC97; |
405 |
k->class_id = PCI_CLASS_COMMUNICATION_OTHER; |
406 |
k->revision = 0x30;
|
407 |
dc->desc = "MC97";
|
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} |
409 |
|
410 |
static TypeInfo via_mc97_info = {
|
411 |
.name = "VT82C686B_MC97",
|
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.parent = TYPE_PCI_DEVICE, |
413 |
.instance_size = sizeof(VT686MC97State),
|
414 |
.class_init = via_mc97_class_init, |
415 |
}; |
416 |
|
417 |
static void vt82c686b_mc97_register(void) |
418 |
{ |
419 |
type_register_static(&via_mc97_info); |
420 |
} |
421 |
|
422 |
device_init(vt82c686b_mc97_register); |
423 |
|
424 |
/* vt82c686 pm init */
|
425 |
static int vt82c686b_pm_initfn(PCIDevice *dev) |
426 |
{ |
427 |
VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); |
428 |
uint8_t *pci_conf; |
429 |
|
430 |
pci_conf = s->dev.config; |
431 |
pci_set_word(pci_conf + PCI_COMMAND, 0);
|
432 |
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | |
433 |
PCI_STATUS_DEVSEL_MEDIUM); |
434 |
|
435 |
/* 0x48-0x4B is Power Management I/O Base */
|
436 |
pci_set_long(pci_conf + 0x48, 0x00000001); |
437 |
|
438 |
/* SMB ports:0xeee0~0xeeef */
|
439 |
s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); |
440 |
pci_conf[0x90] = s->smb_io_base | 1; |
441 |
pci_conf[0x91] = s->smb_io_base >> 8; |
442 |
pci_conf[0xd2] = 0x90; |
443 |
register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb); |
444 |
register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb); |
445 |
|
446 |
apm_init(&s->apm, NULL, s);
|
447 |
|
448 |
acpi_pm_tmr_init(&s->tmr, pm_tmr_timer); |
449 |
acpi_pm1_cnt_init(&s->pm1_cnt, NULL);
|
450 |
|
451 |
pm_smbus_init(&s->dev.qdev, &s->smb); |
452 |
|
453 |
return 0; |
454 |
} |
455 |
|
456 |
i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
457 |
qemu_irq sci_irq) |
458 |
{ |
459 |
PCIDevice *dev; |
460 |
VT686PMState *s; |
461 |
|
462 |
dev = pci_create(bus, devfn, "VT82C686B_PM");
|
463 |
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
464 |
|
465 |
s = DO_UPCAST(VT686PMState, dev, dev); |
466 |
|
467 |
qdev_init_nofail(&dev->qdev); |
468 |
|
469 |
return s->smb.smbus;
|
470 |
} |
471 |
|
472 |
static Property via_pm_properties[] = {
|
473 |
DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), |
474 |
DEFINE_PROP_END_OF_LIST(), |
475 |
}; |
476 |
|
477 |
static void via_pm_class_init(ObjectClass *klass, void *data) |
478 |
{ |
479 |
DeviceClass *dc = DEVICE_CLASS(klass); |
480 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
481 |
|
482 |
k->init = vt82c686b_pm_initfn; |
483 |
k->config_write = pm_write_config; |
484 |
k->vendor_id = PCI_VENDOR_ID_VIA; |
485 |
k->device_id = PCI_DEVICE_ID_VIA_ACPI; |
486 |
k->class_id = PCI_CLASS_BRIDGE_OTHER; |
487 |
k->revision = 0x40;
|
488 |
dc->desc = "PM";
|
489 |
dc->vmsd = &vmstate_acpi; |
490 |
dc->props = via_pm_properties; |
491 |
} |
492 |
|
493 |
static TypeInfo via_pm_info = {
|
494 |
.name = "VT82C686B_PM",
|
495 |
.parent = TYPE_PCI_DEVICE, |
496 |
.instance_size = sizeof(VT686PMState),
|
497 |
.class_init = via_pm_class_init, |
498 |
}; |
499 |
|
500 |
static void vt82c686b_pm_register(void) |
501 |
{ |
502 |
type_register_static(&via_pm_info); |
503 |
} |
504 |
|
505 |
device_init(vt82c686b_pm_register); |
506 |
|
507 |
static const VMStateDescription vmstate_via = { |
508 |
.name = "vt82c686b",
|
509 |
.version_id = 1,
|
510 |
.minimum_version_id = 1,
|
511 |
.minimum_version_id_old = 1,
|
512 |
.fields = (VMStateField []) { |
513 |
VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
514 |
VMSTATE_END_OF_LIST() |
515 |
} |
516 |
}; |
517 |
|
518 |
/* init the PCI-to-ISA bridge */
|
519 |
static int vt82c686b_initfn(PCIDevice *d) |
520 |
{ |
521 |
uint8_t *pci_conf; |
522 |
uint8_t *wmask; |
523 |
int i;
|
524 |
|
525 |
isa_bus_new(&d->qdev, pci_address_space_io(d)); |
526 |
|
527 |
pci_conf = d->config; |
528 |
pci_config_set_prog_interface(pci_conf, 0x0);
|
529 |
|
530 |
wmask = d->wmask; |
531 |
for (i = 0x00; i < 0xff; i++) { |
532 |
if (i<=0x03 || (i>=0x08 && i<=0x3f)) { |
533 |
wmask[i] = 0x00;
|
534 |
} |
535 |
} |
536 |
|
537 |
qemu_register_reset(vt82c686b_reset, d); |
538 |
|
539 |
return 0; |
540 |
} |
541 |
|
542 |
ISABus *vt82c686b_init(PCIBus *bus, int devfn)
|
543 |
{ |
544 |
PCIDevice *d; |
545 |
|
546 |
d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); |
547 |
|
548 |
return DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0")); |
549 |
} |
550 |
|
551 |
static void via_class_init(ObjectClass *klass, void *data) |
552 |
{ |
553 |
DeviceClass *dc = DEVICE_CLASS(klass); |
554 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
555 |
|
556 |
k->init = vt82c686b_initfn; |
557 |
k->config_write = vt82c686b_write_config; |
558 |
k->vendor_id = PCI_VENDOR_ID_VIA; |
559 |
k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; |
560 |
k->class_id = PCI_CLASS_BRIDGE_ISA; |
561 |
k->revision = 0x40;
|
562 |
dc->desc = "ISA bridge";
|
563 |
dc->no_user = 1;
|
564 |
dc->vmsd = &vmstate_via; |
565 |
} |
566 |
|
567 |
static TypeInfo via_info = {
|
568 |
.name = "VT82C686B",
|
569 |
.parent = TYPE_PCI_DEVICE, |
570 |
.instance_size = sizeof(VT82C686BState),
|
571 |
.class_init = via_class_init, |
572 |
}; |
573 |
|
574 |
static void vt82c686b_register(void) |
575 |
{ |
576 |
type_register_static(&via_info); |
577 |
} |
578 |
device_init(vt82c686b_register); |