root / target-mips / translate_init.c @ 0dba6195
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1 | 33d68b5f | ths | /*
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2 | 33d68b5f | ths | * MIPS emulation for qemu: CPU initialisation routines.
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3 | 33d68b5f | ths | *
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4 | 33d68b5f | ths | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 33d68b5f | ths | * Copyright (c) 2007 Herve Poussineau
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6 | 33d68b5f | ths | *
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7 | 33d68b5f | ths | * This library is free software; you can redistribute it and/or
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8 | 33d68b5f | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 33d68b5f | ths | * License as published by the Free Software Foundation; either
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10 | 33d68b5f | ths | * version 2 of the License, or (at your option) any later version.
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11 | 33d68b5f | ths | *
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12 | 33d68b5f | ths | * This library is distributed in the hope that it will be useful,
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13 | 33d68b5f | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 33d68b5f | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 33d68b5f | ths | * Lesser General Public License for more details.
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16 | 33d68b5f | ths | *
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17 | 33d68b5f | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 33d68b5f | ths | */
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20 | 33d68b5f | ths | |
21 | 3953d786 | ths | /* CPU / CPU family specific config register values. */
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22 | 3953d786 | ths | |
23 | 6d35524c | ths | /* Have config1, uncached coherency */
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24 | 3953d786 | ths | #define MIPS_CONFIG0 \
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25 | 6d35524c | ths | ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) |
26 | 3953d786 | ths | |
27 | ae5d8053 | ths | /* Have config2, no coprocessor2 attached, no MDMX support attached,
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28 | 3953d786 | ths | no performance counters, watch registers present,
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29 | 3953d786 | ths | no code compression, EJTAG present, no FPU */
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30 | 3953d786 | ths | #define MIPS_CONFIG1 \
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31 | fcb4a419 | ths | ((1 << CP0C1_M) | \
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32 | 3953d786 | ths | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
33 | 3953d786 | ths | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
34 | 3953d786 | ths | (0 << CP0C1_FP))
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35 | 3953d786 | ths | |
36 | 3953d786 | ths | /* Have config3, no tertiary/secondary caches implemented */
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37 | 3953d786 | ths | #define MIPS_CONFIG2 \
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38 | 3953d786 | ths | ((1 << CP0C2_M))
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39 | 3953d786 | ths | |
40 | 6d35524c | ths | /* No config4, no DSP ASE, no large physaddr (PABITS),
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41 | 3953d786 | ths | no external interrupt controller, no vectored interupts,
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42 | ead9360e | ths | no 1kb pages, no SmartMIPS ASE, no trace logic */
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43 | 3953d786 | ths | #define MIPS_CONFIG3 \
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44 | 3953d786 | ths | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
45 | 3953d786 | ths | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
46 | ead9360e | ths | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
47 | 3953d786 | ths | |
48 | 3953d786 | ths | /* Define a implementation number of 1.
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49 | 3953d786 | ths | Define a major version 1, minor version 0. */
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50 | 5a5012ec | ths | #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |
51 | 3953d786 | ths | |
52 | 6d35524c | ths | /* MMU types, the first four entries have the same layout as the
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53 | 6d35524c | ths | CP0C0_MT field. */
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54 | 6d35524c | ths | enum mips_mmu_types {
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55 | 6d35524c | ths | MMU_TYPE_NONE, |
56 | 6d35524c | ths | MMU_TYPE_R4000, |
57 | 6d35524c | ths | MMU_TYPE_RESERVED, |
58 | 6d35524c | ths | MMU_TYPE_FMT, |
59 | 6d35524c | ths | MMU_TYPE_R3000, |
60 | 6d35524c | ths | MMU_TYPE_R6000, |
61 | 6d35524c | ths | MMU_TYPE_R8000 |
62 | 6d35524c | ths | }; |
63 | 6d35524c | ths | |
64 | c227f099 | Anthony Liguori | struct mips_def_t {
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65 | 50366fe9 | ths | const char *name; |
66 | 33d68b5f | ths | int32_t CP0_PRid; |
67 | 33d68b5f | ths | int32_t CP0_Config0; |
68 | 33d68b5f | ths | int32_t CP0_Config1; |
69 | 3953d786 | ths | int32_t CP0_Config2; |
70 | 3953d786 | ths | int32_t CP0_Config3; |
71 | 34ee2ede | ths | int32_t CP0_Config6; |
72 | 34ee2ede | ths | int32_t CP0_Config7; |
73 | 2a6e32dd | Aurelien Jarno | target_ulong CP0_LLAddr_rw_bitmask; |
74 | 2a6e32dd | Aurelien Jarno | int CP0_LLAddr_shift;
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75 | 2f644545 | ths | int32_t SYNCI_Step; |
76 | 2f644545 | ths | int32_t CCRes; |
77 | ead9360e | ths | int32_t CP0_Status_rw_bitmask; |
78 | ead9360e | ths | int32_t CP0_TCStatus_rw_bitmask; |
79 | ead9360e | ths | int32_t CP0_SRSCtl; |
80 | 3953d786 | ths | int32_t CP1_fcr0; |
81 | e034e2c3 | ths | int32_t SEGBITS; |
82 | 6d35524c | ths | int32_t PABITS; |
83 | ead9360e | ths | int32_t CP0_SRSConf0_rw_bitmask; |
84 | ead9360e | ths | int32_t CP0_SRSConf0; |
85 | ead9360e | ths | int32_t CP0_SRSConf1_rw_bitmask; |
86 | ead9360e | ths | int32_t CP0_SRSConf1; |
87 | ead9360e | ths | int32_t CP0_SRSConf2_rw_bitmask; |
88 | ead9360e | ths | int32_t CP0_SRSConf2; |
89 | ead9360e | ths | int32_t CP0_SRSConf3_rw_bitmask; |
90 | ead9360e | ths | int32_t CP0_SRSConf3; |
91 | ead9360e | ths | int32_t CP0_SRSConf4_rw_bitmask; |
92 | ead9360e | ths | int32_t CP0_SRSConf4; |
93 | e189e748 | ths | int insn_flags;
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94 | 6d35524c | ths | enum mips_mmu_types mmu_type;
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95 | 33d68b5f | ths | }; |
96 | 33d68b5f | ths | |
97 | 33d68b5f | ths | /*****************************************************************************/
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98 | 33d68b5f | ths | /* MIPS CPU definitions */
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99 | c227f099 | Anthony Liguori | static const mips_def_t mips_defs[] = |
100 | 33d68b5f | ths | { |
101 | 33d68b5f | ths | { |
102 | 33d68b5f | ths | .name = "4Kc",
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103 | 33d68b5f | ths | .CP0_PRid = 0x00018000,
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104 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
105 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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106 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
107 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
108 | ab3aee26 | Stefan Weil | (0 << CP0C1_CA),
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109 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
110 | 3953d786 | ths | .CP0_Config3 = MIPS_CONFIG3, |
111 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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112 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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113 | 2f644545 | ths | .SYNCI_Step = 32,
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114 | 2f644545 | ths | .CCRes = 2,
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115 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x1278FF17,
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116 | 6d35524c | ths | .SEGBITS = 32,
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117 | 6d35524c | ths | .PABITS = 32,
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118 | 73642f5b | Stefan Weil | .insn_flags = CPU_MIPS32, |
119 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
120 | 33d68b5f | ths | }, |
121 | 33d68b5f | ths | { |
122 | 8d162c2b | ths | .name = "4Km",
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123 | 8d162c2b | ths | .CP0_PRid = 0x00018300,
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124 | 8d162c2b | ths | /* Config1 implemented, fixed mapping MMU,
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125 | 8d162c2b | ths | no virtual icache, uncached coherency. */
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126 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
127 | 8d162c2b | ths | .CP0_Config1 = MIPS_CONFIG1 | |
128 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
129 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
130 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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131 | 8d162c2b | ths | .CP0_Config2 = MIPS_CONFIG2, |
132 | 8d162c2b | ths | .CP0_Config3 = MIPS_CONFIG3, |
133 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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134 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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135 | 8d162c2b | ths | .SYNCI_Step = 32,
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136 | 8d162c2b | ths | .CCRes = 2,
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137 | 8d162c2b | ths | .CP0_Status_rw_bitmask = 0x1258FF17,
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138 | 6d35524c | ths | .SEGBITS = 32,
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139 | 6d35524c | ths | .PABITS = 32,
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140 | 8d162c2b | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
141 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |
142 | 8d162c2b | ths | }, |
143 | 8d162c2b | ths | { |
144 | 34ee2ede | ths | .name = "4KEcR1",
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145 | 33d68b5f | ths | .CP0_PRid = 0x00018400,
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146 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
147 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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148 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
149 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
150 | ab3aee26 | Stefan Weil | (0 << CP0C1_CA),
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151 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
152 | 34ee2ede | ths | .CP0_Config3 = MIPS_CONFIG3, |
153 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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154 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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155 | 2f644545 | ths | .SYNCI_Step = 32,
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156 | 2f644545 | ths | .CCRes = 2,
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157 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x1278FF17,
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158 | 6d35524c | ths | .SEGBITS = 32,
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159 | 6d35524c | ths | .PABITS = 32,
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160 | 73642f5b | Stefan Weil | .insn_flags = CPU_MIPS32, |
161 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
162 | 34ee2ede | ths | }, |
163 | 34ee2ede | ths | { |
164 | 8d162c2b | ths | .name = "4KEmR1",
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165 | 8d162c2b | ths | .CP0_PRid = 0x00018500,
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166 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
167 | 8d162c2b | ths | .CP0_Config1 = MIPS_CONFIG1 | |
168 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
169 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
170 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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171 | 8d162c2b | ths | .CP0_Config2 = MIPS_CONFIG2, |
172 | 8d162c2b | ths | .CP0_Config3 = MIPS_CONFIG3, |
173 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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174 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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175 | 8d162c2b | ths | .SYNCI_Step = 32,
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176 | 8d162c2b | ths | .CCRes = 2,
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177 | 8d162c2b | ths | .CP0_Status_rw_bitmask = 0x1258FF17,
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178 | 6d35524c | ths | .SEGBITS = 32,
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179 | 6d35524c | ths | .PABITS = 32,
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180 | 8d162c2b | ths | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
181 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |
182 | 8d162c2b | ths | }, |
183 | 8d162c2b | ths | { |
184 | 34ee2ede | ths | .name = "4KEc",
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185 | 34ee2ede | ths | .CP0_PRid = 0x00019000,
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186 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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187 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT), |
188 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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189 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
190 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
191 | ab3aee26 | Stefan Weil | (0 << CP0C1_CA),
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192 | 34ee2ede | ths | .CP0_Config2 = MIPS_CONFIG2, |
193 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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194 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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195 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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196 | 2f644545 | ths | .SYNCI_Step = 32,
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197 | 2f644545 | ths | .CCRes = 2,
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198 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x1278FF17,
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199 | 6d35524c | ths | .SEGBITS = 32,
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200 | 6d35524c | ths | .PABITS = 32,
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201 | 73642f5b | Stefan Weil | .insn_flags = CPU_MIPS32R2, |
202 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
203 | 34ee2ede | ths | }, |
204 | 34ee2ede | ths | { |
205 | 3e4587d5 | ths | .name = "4KEm",
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206 | 3e4587d5 | ths | .CP0_PRid = 0x00019100,
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207 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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208 | 6958549d | aurel32 | (MMU_TYPE_FMT << CP0C0_MT), |
209 | 3e4587d5 | ths | .CP0_Config1 = MIPS_CONFIG1 | |
210 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
211 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
212 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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213 | 3e4587d5 | ths | .CP0_Config2 = MIPS_CONFIG2, |
214 | 3e4587d5 | ths | .CP0_Config3 = MIPS_CONFIG3, |
215 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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216 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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217 | 3e4587d5 | ths | .SYNCI_Step = 32,
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218 | 3e4587d5 | ths | .CCRes = 2,
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219 | 3e4587d5 | ths | .CP0_Status_rw_bitmask = 0x1258FF17,
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220 | 6d35524c | ths | .SEGBITS = 32,
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221 | 6d35524c | ths | .PABITS = 32,
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222 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
223 | 6d35524c | ths | .mmu_type = MMU_TYPE_FMT, |
224 | 3e4587d5 | ths | }, |
225 | 3e4587d5 | ths | { |
226 | 34ee2ede | ths | .name = "24Kc",
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227 | 34ee2ede | ths | .CP0_PRid = 0x00019300,
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228 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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229 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
230 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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231 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
232 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
233 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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234 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
235 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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236 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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237 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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238 | 2f644545 | ths | .SYNCI_Step = 32,
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239 | 2f644545 | ths | .CCRes = 2,
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240 | ead9360e | ths | /* No DSP implemented. */
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241 | 671880e6 | ths | .CP0_Status_rw_bitmask = 0x1278FF1F,
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242 | 6d35524c | ths | .SEGBITS = 32,
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243 | 6d35524c | ths | .PABITS = 32,
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244 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
245 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
246 | 33d68b5f | ths | }, |
247 | 33d68b5f | ths | { |
248 | 33d68b5f | ths | .name = "24Kf",
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249 | 33d68b5f | ths | .CP0_PRid = 0x00019300,
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250 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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251 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT), |
252 | ae5d8053 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
253 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
254 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
255 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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256 | 3953d786 | ths | .CP0_Config2 = MIPS_CONFIG2, |
257 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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258 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
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259 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
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260 | 2f644545 | ths | .SYNCI_Step = 32,
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261 | 2f644545 | ths | .CCRes = 2,
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262 | ead9360e | ths | /* No DSP implemented. */
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263 | 671880e6 | ths | .CP0_Status_rw_bitmask = 0x3678FF1F,
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264 | 5a5012ec | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
265 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
266 | 6d35524c | ths | .SEGBITS = 32,
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267 | 6d35524c | ths | .PABITS = 32,
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268 | 3e4587d5 | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
269 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
270 | 33d68b5f | ths | }, |
271 | ead9360e | ths | { |
272 | ead9360e | ths | .name = "34Kf",
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273 | ead9360e | ths | .CP0_PRid = 0x00019500,
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274 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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275 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
276 | ead9360e | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
277 | 6958549d | aurel32 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
278 | d19954f4 | Nathan Froyd | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
279 | d19954f4 | Nathan Froyd | (1 << CP0C1_CA),
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280 | ead9360e | ths | .CP0_Config2 = MIPS_CONFIG2, |
281 | ead9360e | ths | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |
282 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
283 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 0,
|
284 | ead9360e | ths | .SYNCI_Step = 32,
|
285 | ead9360e | ths | .CCRes = 2,
|
286 | ead9360e | ths | /* No DSP implemented. */
|
287 | 671880e6 | ths | .CP0_Status_rw_bitmask = 0x3678FF1F,
|
288 | ead9360e | ths | /* No DSP implemented. */
|
289 | ead9360e | ths | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
290 | ead9360e | ths | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
291 | ead9360e | ths | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
292 | ead9360e | ths | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
293 | ead9360e | ths | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
294 | ead9360e | ths | (0xff << CP0TCSt_TASID),
|
295 | ead9360e | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
296 | ead9360e | ths | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
297 | ead9360e | ths | .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
|
298 | ead9360e | ths | .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
|
299 | ead9360e | ths | .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
300 | ead9360e | ths | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
301 | ead9360e | ths | .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
|
302 | ead9360e | ths | .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
303 | ead9360e | ths | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
304 | ead9360e | ths | .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
|
305 | ead9360e | ths | .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
306 | ead9360e | ths | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
307 | ead9360e | ths | .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
|
308 | ead9360e | ths | .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
309 | ead9360e | ths | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
310 | ead9360e | ths | .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
|
311 | ead9360e | ths | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
|
312 | ead9360e | ths | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
313 | 6d35524c | ths | .SEGBITS = 32,
|
314 | 6d35524c | ths | .PABITS = 32,
|
315 | 7385ac0b | ths | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
316 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
317 | ead9360e | ths | }, |
318 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
319 | 33d68b5f | ths | { |
320 | 33d68b5f | ths | .name = "R4000",
|
321 | 33d68b5f | ths | .CP0_PRid = 0x00000400,
|
322 | 6d35524c | ths | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
323 | 6d35524c | ths | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
324 | 6958549d | aurel32 | /* Note: Config1 is only used internally, the R4000 has only Config0. */
|
325 | 6d35524c | ths | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
326 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
|
327 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
328 | 2f644545 | ths | .SYNCI_Step = 16,
|
329 | 2f644545 | ths | .CCRes = 2,
|
330 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x3678FFFF,
|
331 | 6958549d | aurel32 | /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
332 | c9c1a064 | ths | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
333 | e034e2c3 | ths | .SEGBITS = 40,
|
334 | 6d35524c | ths | .PABITS = 36,
|
335 | e189e748 | ths | .insn_flags = CPU_MIPS3, |
336 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
337 | c9c1a064 | ths | }, |
338 | e9c71dd1 | ths | { |
339 | e9c71dd1 | ths | .name = "VR5432",
|
340 | e9c71dd1 | ths | .CP0_PRid = 0x00005400,
|
341 | e9c71dd1 | ths | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
342 | e9c71dd1 | ths | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
343 | e9c71dd1 | ths | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
344 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
|
345 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
346 | e9c71dd1 | ths | .SYNCI_Step = 16,
|
347 | e9c71dd1 | ths | .CCRes = 2,
|
348 | e9c71dd1 | ths | .CP0_Status_rw_bitmask = 0x3678FFFF,
|
349 | e9c71dd1 | ths | /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
350 | e9c71dd1 | ths | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
351 | e9c71dd1 | ths | .SEGBITS = 40,
|
352 | e9c71dd1 | ths | .PABITS = 32,
|
353 | e9c71dd1 | ths | .insn_flags = CPU_VR54XX, |
354 | e9c71dd1 | ths | .mmu_type = MMU_TYPE_R4000, |
355 | e9c71dd1 | ths | }, |
356 | c9c1a064 | ths | { |
357 | c9c1a064 | ths | .name = "5Kc",
|
358 | c9c1a064 | ths | .CP0_PRid = 0x00018100,
|
359 | 29fe0e34 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
360 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
361 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
|
362 | 6958549d | aurel32 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
363 | 6958549d | aurel32 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
364 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
365 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
366 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
367 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
368 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
369 | c9c1a064 | ths | .SYNCI_Step = 32,
|
370 | c9c1a064 | ths | .CCRes = 2,
|
371 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x32F8FFFF,
|
372 | e034e2c3 | ths | .SEGBITS = 42,
|
373 | 6d35524c | ths | .PABITS = 36,
|
374 | e189e748 | ths | .insn_flags = CPU_MIPS64, |
375 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
376 | c9c1a064 | ths | }, |
377 | c9c1a064 | ths | { |
378 | c9c1a064 | ths | .name = "5Kf",
|
379 | c9c1a064 | ths | .CP0_PRid = 0x00018100,
|
380 | 29fe0e34 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
381 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
382 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
383 | 6958549d | aurel32 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
384 | 6958549d | aurel32 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
385 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
386 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
387 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
388 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
389 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 4,
|
390 | c9c1a064 | ths | .SYNCI_Step = 32,
|
391 | c9c1a064 | ths | .CCRes = 2,
|
392 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x36F8FFFF,
|
393 | 6958549d | aurel32 | /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
|
394 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
395 | c9c1a064 | ths | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
396 | e034e2c3 | ths | .SEGBITS = 42,
|
397 | 6d35524c | ths | .PABITS = 36,
|
398 | e189e748 | ths | .insn_flags = CPU_MIPS64, |
399 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
400 | c9c1a064 | ths | }, |
401 | c9c1a064 | ths | { |
402 | c9c1a064 | ths | .name = "20Kc",
|
403 | 6958549d | aurel32 | /* We emulate a later version of the 20Kc, earlier ones had a broken
|
404 | bd04c6fe | ths | WAIT instruction. */
|
405 | bd04c6fe | ths | .CP0_PRid = 0x000182a0,
|
406 | 29fe0e34 | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
407 | 6d35524c | ths | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
|
408 | c9c1a064 | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
409 | 6958549d | aurel32 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
410 | 6958549d | aurel32 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
411 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
412 | c9c1a064 | ths | .CP0_Config2 = MIPS_CONFIG2, |
413 | c9c1a064 | ths | .CP0_Config3 = MIPS_CONFIG3, |
414 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
415 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 0,
|
416 | c9c1a064 | ths | .SYNCI_Step = 32,
|
417 | a1daafd8 | ths | .CCRes = 1,
|
418 | ead9360e | ths | .CP0_Status_rw_bitmask = 0x36FBFFFF,
|
419 | 6958549d | aurel32 | /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
|
420 | c9c1a064 | ths | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
421 | 5a5012ec | ths | (1 << FCR0_D) | (1 << FCR0_S) | |
422 | c9c1a064 | ths | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
423 | e034e2c3 | ths | .SEGBITS = 40,
|
424 | 6d35524c | ths | .PABITS = 36,
|
425 | e189e748 | ths | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
426 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
427 | 33d68b5f | ths | }, |
428 | d2123ead | ths | { |
429 | 6958549d | aurel32 | /* A generic CPU providing MIPS64 Release 2 features.
|
430 | d2123ead | ths | FIXME: Eventually this should be replaced by a real CPU model. */
|
431 | d2123ead | ths | .name = "MIPS64R2-generic",
|
432 | 8c89395e | ths | .CP0_PRid = 0x00010000,
|
433 | 6d35524c | ths | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
434 | 6958549d | aurel32 | (MMU_TYPE_R4000 << CP0C0_MT), |
435 | d2123ead | ths | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
436 | 6958549d | aurel32 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
437 | 6958549d | aurel32 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
438 | 6958549d | aurel32 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
439 | d2123ead | ths | .CP0_Config2 = MIPS_CONFIG2, |
440 | 6d35524c | ths | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
|
441 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_rw_bitmask = 0,
|
442 | 2a6e32dd | Aurelien Jarno | .CP0_LLAddr_shift = 0,
|
443 | d2123ead | ths | .SYNCI_Step = 32,
|
444 | d2123ead | ths | .CCRes = 2,
|
445 | d2123ead | ths | .CP0_Status_rw_bitmask = 0x36FBFFFF,
|
446 | ea4b07f7 | ths | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
447 | ea4b07f7 | ths | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
448 | ea4b07f7 | ths | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
449 | 6d35524c | ths | .SEGBITS = 42,
|
450 | 6d35524c | ths | /* The architectural limit is 59, but we have hardcoded 36 bit
|
451 | 6d35524c | ths | in some places...
|
452 | 6d35524c | ths | .PABITS = 59, */ /* the architectural limit */ |
453 | 6d35524c | ths | .PABITS = 36,
|
454 | d2123ead | ths | .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
455 | 6d35524c | ths | .mmu_type = MMU_TYPE_R4000, |
456 | d2123ead | ths | }, |
457 | 33d68b5f | ths | #endif
|
458 | 33d68b5f | ths | }; |
459 | 33d68b5f | ths | |
460 | c227f099 | Anthony Liguori | static const mips_def_t *cpu_mips_find_by_name (const char *name) |
461 | 33d68b5f | ths | { |
462 | aaed909a | bellard | int i;
|
463 | 33d68b5f | ths | |
464 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
465 | 33d68b5f | ths | if (strcasecmp(name, mips_defs[i].name) == 0) { |
466 | aaed909a | bellard | return &mips_defs[i];
|
467 | 33d68b5f | ths | } |
468 | 33d68b5f | ths | } |
469 | aaed909a | bellard | return NULL; |
470 | 33d68b5f | ths | } |
471 | 33d68b5f | ths | |
472 | 33d68b5f | ths | void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
473 | 33d68b5f | ths | { |
474 | 33d68b5f | ths | int i;
|
475 | 33d68b5f | ths | |
476 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
477 | 33d68b5f | ths | (*cpu_fprintf)(f, "MIPS '%s'\n",
|
478 | 33d68b5f | ths | mips_defs[i].name); |
479 | 33d68b5f | ths | } |
480 | 33d68b5f | ths | } |
481 | 33d68b5f | ths | |
482 | f8a6ec58 | ths | #ifndef CONFIG_USER_ONLY
|
483 | c227f099 | Anthony Liguori | static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
484 | 29929e34 | ths | { |
485 | ead9360e | ths | env->tlb->nb_tlb = 1;
|
486 | ead9360e | ths | env->tlb->map_address = &no_mmu_map_address; |
487 | 29929e34 | ths | } |
488 | 29929e34 | ths | |
489 | c227f099 | Anthony Liguori | static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
490 | 29929e34 | ths | { |
491 | ead9360e | ths | env->tlb->nb_tlb = 1;
|
492 | ead9360e | ths | env->tlb->map_address = &fixed_mmu_map_address; |
493 | 29929e34 | ths | } |
494 | 29929e34 | ths | |
495 | c227f099 | Anthony Liguori | static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
496 | 29929e34 | ths | { |
497 | ead9360e | ths | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
498 | ead9360e | ths | env->tlb->map_address = &r4k_map_address; |
499 | c01fccd2 | aurel32 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
500 | c01fccd2 | aurel32 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
501 | c01fccd2 | aurel32 | env->tlb->helper_tlbp = r4k_helper_tlbp; |
502 | c01fccd2 | aurel32 | env->tlb->helper_tlbr = r4k_helper_tlbr; |
503 | ead9360e | ths | } |
504 | ead9360e | ths | |
505 | c227f099 | Anthony Liguori | static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
506 | ead9360e | ths | { |
507 | ead9360e | ths | env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext));
|
508 | ead9360e | ths | |
509 | 6d35524c | ths | switch (def->mmu_type) {
|
510 | 6d35524c | ths | case MMU_TYPE_NONE:
|
511 | ead9360e | ths | no_mmu_init(env, def); |
512 | ead9360e | ths | break;
|
513 | 6d35524c | ths | case MMU_TYPE_R4000:
|
514 | ead9360e | ths | r4k_mmu_init(env, def); |
515 | ead9360e | ths | break;
|
516 | 6d35524c | ths | case MMU_TYPE_FMT:
|
517 | ead9360e | ths | fixed_mmu_init(env, def); |
518 | ead9360e | ths | break;
|
519 | 6d35524c | ths | case MMU_TYPE_R3000:
|
520 | 6d35524c | ths | case MMU_TYPE_R6000:
|
521 | 6d35524c | ths | case MMU_TYPE_R8000:
|
522 | ead9360e | ths | default:
|
523 | ead9360e | ths | cpu_abort(env, "MMU type not supported\n");
|
524 | ead9360e | ths | } |
525 | 29929e34 | ths | } |
526 | f8a6ec58 | ths | #endif /* CONFIG_USER_ONLY */ |
527 | 29929e34 | ths | |
528 | c227f099 | Anthony Liguori | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
529 | ead9360e | ths | { |
530 | f01be154 | ths | int i;
|
531 | f01be154 | ths | |
532 | f01be154 | ths | for (i = 0; i < MIPS_FPU_MAX; i++) |
533 | f01be154 | ths | env->fpus[i].fcr0 = def->CP1_fcr0; |
534 | ead9360e | ths | |
535 | f01be154 | ths | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
536 | ead9360e | ths | } |
537 | ead9360e | ths | |
538 | c227f099 | Anthony Liguori | static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
539 | ead9360e | ths | { |
540 | ead9360e | ths | env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext));
|
541 | ead9360e | ths | |
542 | ead9360e | ths | /* MVPConf1 implemented, TLB sharable, no gating storage support,
|
543 | ead9360e | ths | programmable cache partitioning implemented, number of allocatable
|
544 | ead9360e | ths | and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
|
545 | ead9360e | ths | implemented, 5 TCs implemented. */
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546 | ead9360e | ths | env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
547 | ead9360e | ths | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
548 | ead9360e | ths | // TODO: actually do 2 VPEs.
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549 | ead9360e | ths | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
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550 | ead9360e | ths | // (0x04 << CP0MVPC0_PTC);
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551 | ead9360e | ths | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
552 | ead9360e | ths | (0x04 << CP0MVPC0_PTC);
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553 | 932e71cd | aurel32 | #if !defined(CONFIG_USER_ONLY)
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554 | 0eaef5aa | ths | /* Usermode has no TLB support */
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555 | 932e71cd | aurel32 | env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
556 | 932e71cd | aurel32 | #endif
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557 | 0eaef5aa | ths | |
558 | ead9360e | ths | /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
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559 | ead9360e | ths | no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
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560 | ead9360e | ths | env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
561 | ead9360e | ths | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
562 | ead9360e | ths | (0x1 << CP0MVPC1_PCP1);
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563 | ead9360e | ths | } |