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/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include <signal.h> |
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#include <assert.h> |
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#include <sys/mman.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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//#define DEBUG_MMU
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#ifdef USE_CODE_COPY
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#include <asm/ldt.h> |
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#include <linux/unistd.h> |
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|
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_syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount) |
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#endif
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CPUX86State *cpu_x86_init(void)
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{ |
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CPUX86State *env; |
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int i;
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static int inited; |
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cpu_exec_init(); |
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env = malloc(sizeof(CPUX86State));
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if (!env)
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return NULL; |
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memset(env, 0, sizeof(CPUX86State)); |
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/* init to reset state */
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tlb_flush(env, 1);
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#ifdef CONFIG_SOFTMMU
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env->hflags |= HF_SOFTMMU_MASK; |
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#endif
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cpu_x86_update_cr0(env, 0x60000010);
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env->a20_mask = 0xffffffff;
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env->idt.limit = 0xffff;
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env->gdt.limit = 0xffff;
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env->ldt.limit = 0xffff;
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env->ldt.flags = DESC_P_MASK; |
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env->tr.limit = 0xffff;
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env->tr.flags = DESC_P_MASK; |
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/* not correct (CS base=0xffff0000) */
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cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0); |
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cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0); |
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env->eip = 0xfff0;
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env->regs[R_EDX] = 0x600; /* indicate P6 processor */ |
81 |
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env->eflags = 0x2;
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/* FPU init */
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for(i = 0;i < 8; i++) |
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env->fptags[i] = 1;
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env->fpuc = 0x37f;
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/* init various static tables */
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if (!inited) {
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inited = 1;
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optimize_flags_init(); |
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} |
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#ifdef USE_CODE_COPY
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/* testing code for code copy case */
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{ |
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struct modify_ldt_ldt_s ldt;
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ldt.entry_number = 1;
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ldt.base_addr = (unsigned long)env; |
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ldt.limit = (sizeof(CPUState) + 0xfff) >> 12; |
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ldt.seg_32bit = 1;
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ldt.contents = MODIFY_LDT_CONTENTS_DATA; |
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ldt.read_exec_only = 0;
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ldt.limit_in_pages = 1;
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ldt.seg_not_present = 0;
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ldt.useable = 1;
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modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */ |
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asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7)); |
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cpu_single_env = env; |
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} |
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#endif
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return env;
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} |
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void cpu_x86_close(CPUX86State *env)
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{ |
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free(env); |
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} |
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/***********************************************************/
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/* x86 debug */
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static const char *cc_op_str[] = { |
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"DYNAMIC",
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"EFLAGS",
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"MULB",
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"MULW",
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"MULL",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADCB",
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"ADCW",
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"ADCL",
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"SUBB",
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"SUBW",
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"SUBL",
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"SBBB",
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"SBBW",
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"SBBL",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"INCB",
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"INCW",
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"INCL",
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"DECB",
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"DECW",
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"DECL",
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"SHLB",
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"SHLW",
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"SHLL",
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"SARB",
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"SARW",
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"SARL",
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}; |
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void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags) |
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{ |
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int eflags, i;
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char cc_op_name[32]; |
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; |
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eflags = env->eflags; |
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fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d\n",
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env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX], |
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env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP], |
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env->eip, eflags, |
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eflags & DF_MASK ? 'D' : '-', |
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eflags & CC_O ? 'O' : '-', |
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eflags & CC_S ? 'S' : '-', |
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eflags & CC_Z ? 'Z' : '-', |
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eflags & CC_A ? 'A' : '-', |
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eflags & CC_P ? 'P' : '-', |
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eflags & CC_C ? 'C' : '-', |
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env->hflags & HF_CPL_MASK, |
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1);
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for(i = 0; i < 6; i++) { |
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SegmentCache *sc = &env->segs[i]; |
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fprintf(f, "%s =%04x %08x %08x %08x\n",
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seg_name[i], |
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sc->selector, |
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(int)sc->base,
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sc->limit, |
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sc->flags); |
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} |
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fprintf(f, "LDT=%04x %08x %08x %08x\n",
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env->ldt.selector, |
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(int)env->ldt.base,
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env->ldt.limit, |
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env->ldt.flags); |
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fprintf(f, "TR =%04x %08x %08x %08x\n",
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env->tr.selector, |
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(int)env->tr.base,
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env->tr.limit, |
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env->tr.flags); |
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fprintf(f, "GDT= %08x %08x\n",
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(int)env->gdt.base, env->gdt.limit);
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fprintf(f, "IDT= %08x %08x\n",
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(int)env->idt.base, env->idt.limit);
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fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
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env->cr[0], env->cr[2], env->cr[3], env->cr[4]); |
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if (flags & X86_DUMP_CCOP) {
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if ((unsigned)env->cc_op < CC_OP_NB) |
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strcpy(cc_op_name, cc_op_str[env->cc_op]); |
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else
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); |
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fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
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env->cc_src, env->cc_dst, cc_op_name); |
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} |
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if (flags & X86_DUMP_FPU) {
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fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
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(double)env->fpregs[0], |
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(double)env->fpregs[1], |
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(double)env->fpregs[2], |
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(double)env->fpregs[3]); |
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fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
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(double)env->fpregs[4], |
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(double)env->fpregs[5], |
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(double)env->fpregs[7], |
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(double)env->fpregs[8]); |
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} |
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} |
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/***********************************************************/
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/* x86 mmu */
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/* XXX: add PGE support */
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void cpu_x86_set_a20(CPUX86State *env, int a20_state) |
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{ |
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a20_state = (a20_state != 0);
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if (a20_state != ((env->a20_mask >> 20) & 1)) { |
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#if defined(DEBUG_MMU)
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printf("A20 update: a20=%d\n", a20_state);
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#endif
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/* if the cpu is currently executing code, we must unlink it and
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all the potentially executing TB */
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cpu_interrupt(env, CPU_INTERRUPT_EXITTB); |
244 |
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/* when a20 is changed, all the MMU mappings are invalid, so
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we must flush everything */
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tlb_flush(env, 1);
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env->a20_mask = 0xffefffff | (a20_state << 20); |
249 |
} |
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} |
251 |
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
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{ |
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int pe_state;
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#if defined(DEBUG_MMU)
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printf("CR0 update: CR0=0x%08x\n", new_cr0);
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#endif
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if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
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(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
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tlb_flush(env, 1);
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} |
263 |
env->cr[0] = new_cr0;
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/* update PE flag in hidden flags */
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pe_state = (env->cr[0] & CR0_PE_MASK);
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env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT); |
268 |
/* ensure that ADDSEG is always set in real mode */
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env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
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} |
271 |
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void cpu_x86_update_cr3(CPUX86State *env, uint32_t new_cr3)
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{ |
274 |
env->cr[3] = new_cr3;
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if (env->cr[0] & CR0_PG_MASK) { |
276 |
#if defined(DEBUG_MMU)
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277 |
printf("CR3 update: CR3=%08x\n", new_cr3);
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#endif
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279 |
tlb_flush(env, 0);
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} |
281 |
} |
282 |
|
283 |
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
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284 |
{ |
285 |
#if defined(DEBUG_MMU)
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286 |
printf("CR4 update: CR4=%08x\n", env->cr[4]); |
287 |
#endif
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288 |
if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
|
289 |
(env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
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290 |
tlb_flush(env, 1);
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291 |
} |
292 |
env->cr[4] = new_cr4;
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293 |
} |
294 |
|
295 |
/* XXX: also flush 4MB pages */
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296 |
void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
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297 |
{ |
298 |
tlb_flush_page(env, addr); |
299 |
} |
300 |
|
301 |
/* return value:
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302 |
-1 = cannot handle fault
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303 |
0 = nothing more to do
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304 |
1 = generate PF fault
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305 |
2 = soft MMU activation required for this block
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306 |
*/
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307 |
int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
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308 |
int is_write, int is_user, int is_softmmu) |
309 |
{ |
310 |
uint8_t *pde_ptr, *pte_ptr; |
311 |
uint32_t pde, pte, virt_addr, ptep; |
312 |
int error_code, is_dirty, prot, page_size, ret;
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313 |
unsigned long paddr, vaddr, page_offset; |
314 |
|
315 |
#if defined(DEBUG_MMU)
|
316 |
printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
|
317 |
addr, is_write, is_user, env->eip); |
318 |
#endif
|
319 |
|
320 |
if (env->user_mode_only) {
|
321 |
/* user mode only emulation */
|
322 |
error_code = 0;
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323 |
goto do_fault;
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324 |
} |
325 |
|
326 |
if (!(env->cr[0] & CR0_PG_MASK)) { |
327 |
pte = addr; |
328 |
virt_addr = addr & TARGET_PAGE_MASK; |
329 |
prot = PROT_READ | PROT_WRITE; |
330 |
page_size = 4096;
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331 |
goto do_mapping;
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332 |
} |
333 |
|
334 |
/* page directory entry */
|
335 |
pde_ptr = phys_ram_base + |
336 |
(((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask); |
337 |
pde = ldl_raw(pde_ptr); |
338 |
if (!(pde & PG_PRESENT_MASK)) {
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339 |
error_code = 0;
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340 |
goto do_fault;
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341 |
} |
342 |
/* if PSE bit is set, then we use a 4MB page */
|
343 |
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { |
344 |
if (is_user) {
|
345 |
if (!(pde & PG_USER_MASK))
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346 |
goto do_fault_protect;
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347 |
if (is_write && !(pde & PG_RW_MASK))
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348 |
goto do_fault_protect;
|
349 |
} else {
|
350 |
if ((env->cr[0] & CR0_WP_MASK) && |
351 |
is_write && !(pde & PG_RW_MASK)) |
352 |
goto do_fault_protect;
|
353 |
} |
354 |
is_dirty = is_write && !(pde & PG_DIRTY_MASK); |
355 |
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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356 |
pde |= PG_ACCESSED_MASK; |
357 |
if (is_dirty)
|
358 |
pde |= PG_DIRTY_MASK; |
359 |
stl_raw(pde_ptr, pde); |
360 |
} |
361 |
|
362 |
pte = pde & ~0x003ff000; /* align to 4MB */ |
363 |
ptep = pte; |
364 |
page_size = 4096 * 1024; |
365 |
virt_addr = addr & ~0x003fffff;
|
366 |
} else {
|
367 |
if (!(pde & PG_ACCESSED_MASK)) {
|
368 |
pde |= PG_ACCESSED_MASK; |
369 |
stl_raw(pde_ptr, pde); |
370 |
} |
371 |
|
372 |
/* page directory entry */
|
373 |
pte_ptr = phys_ram_base + |
374 |
(((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask); |
375 |
pte = ldl_raw(pte_ptr); |
376 |
if (!(pte & PG_PRESENT_MASK)) {
|
377 |
error_code = 0;
|
378 |
goto do_fault;
|
379 |
} |
380 |
/* combine pde and pte user and rw protections */
|
381 |
ptep = pte & pde; |
382 |
if (is_user) {
|
383 |
if (!(ptep & PG_USER_MASK))
|
384 |
goto do_fault_protect;
|
385 |
if (is_write && !(ptep & PG_RW_MASK))
|
386 |
goto do_fault_protect;
|
387 |
} else {
|
388 |
if ((env->cr[0] & CR0_WP_MASK) && |
389 |
is_write && !(ptep & PG_RW_MASK)) |
390 |
goto do_fault_protect;
|
391 |
} |
392 |
is_dirty = is_write && !(pte & PG_DIRTY_MASK); |
393 |
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
394 |
pte |= PG_ACCESSED_MASK; |
395 |
if (is_dirty)
|
396 |
pte |= PG_DIRTY_MASK; |
397 |
stl_raw(pte_ptr, pte); |
398 |
} |
399 |
page_size = 4096;
|
400 |
virt_addr = addr & ~0xfff;
|
401 |
} |
402 |
|
403 |
/* the page can be put in the TLB */
|
404 |
prot = PROT_READ; |
405 |
if (pte & PG_DIRTY_MASK) {
|
406 |
/* only set write access if already dirty... otherwise wait
|
407 |
for dirty access */
|
408 |
if (is_user) {
|
409 |
if (ptep & PG_RW_MASK)
|
410 |
prot |= PROT_WRITE; |
411 |
} else {
|
412 |
if (!(env->cr[0] & CR0_WP_MASK) || |
413 |
(ptep & PG_RW_MASK)) |
414 |
prot |= PROT_WRITE; |
415 |
} |
416 |
} |
417 |
|
418 |
do_mapping:
|
419 |
pte = pte & env->a20_mask; |
420 |
|
421 |
/* Even if 4MB pages, we map only one 4KB page in the cache to
|
422 |
avoid filling it too fast */
|
423 |
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
424 |
paddr = (pte & TARGET_PAGE_MASK) + page_offset; |
425 |
vaddr = virt_addr + page_offset; |
426 |
|
427 |
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
428 |
return ret;
|
429 |
do_fault_protect:
|
430 |
error_code = PG_ERROR_P_MASK; |
431 |
do_fault:
|
432 |
env->cr[2] = addr;
|
433 |
env->error_code = (is_write << PG_ERROR_W_BIT) | error_code; |
434 |
if (is_user)
|
435 |
env->error_code |= PG_ERROR_U_MASK; |
436 |
return 1; |
437 |
} |
438 |
|
439 |
#if defined(CONFIG_USER_ONLY)
|
440 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
441 |
{ |
442 |
return addr;
|
443 |
} |
444 |
#else
|
445 |
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
446 |
{ |
447 |
uint8_t *pde_ptr, *pte_ptr; |
448 |
uint32_t pde, pte, paddr, page_offset, page_size; |
449 |
|
450 |
if (!(env->cr[0] & CR0_PG_MASK)) { |
451 |
pte = addr; |
452 |
page_size = 4096;
|
453 |
} else {
|
454 |
/* page directory entry */
|
455 |
pde_ptr = phys_ram_base + |
456 |
(((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask); |
457 |
pde = ldl_raw(pde_ptr); |
458 |
if (!(pde & PG_PRESENT_MASK))
|
459 |
return -1; |
460 |
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { |
461 |
pte = pde & ~0x003ff000; /* align to 4MB */ |
462 |
page_size = 4096 * 1024; |
463 |
} else {
|
464 |
/* page directory entry */
|
465 |
pte_ptr = phys_ram_base + |
466 |
(((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask); |
467 |
pte = ldl_raw(pte_ptr); |
468 |
if (!(pte & PG_PRESENT_MASK))
|
469 |
return -1; |
470 |
page_size = 4096;
|
471 |
} |
472 |
} |
473 |
pte = pte & env->a20_mask; |
474 |
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
475 |
paddr = (pte & TARGET_PAGE_MASK) + page_offset; |
476 |
return paddr;
|
477 |
} |
478 |
#endif
|