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1 | 5fafdf24 | ths | /*
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2 | e69954b9 | pbrook | * ARM RealView Baseboard System emulation.
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3 | e69954b9 | pbrook | *
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4 | a1bb27b1 | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | e69954b9 | pbrook | * This code is licenced under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | e69954b9 | pbrook | #include "vl.h" |
11 | e69954b9 | pbrook | #include "arm_pic.h" |
12 | e69954b9 | pbrook | |
13 | e69954b9 | pbrook | /* Board init. */
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14 | e69954b9 | pbrook | |
15 | 6ac0e82d | balrog | static void realview_init(int ram_size, int vga_ram_size, |
16 | 6ac0e82d | balrog | const char *boot_device, DisplayState *ds, |
17 | 6ac0e82d | balrog | const char **fd_filename, int snapshot, |
18 | e69954b9 | pbrook | const char *kernel_filename, const char *kernel_cmdline, |
19 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
20 | e69954b9 | pbrook | { |
21 | e69954b9 | pbrook | CPUState *env; |
22 | d537cf6c | pbrook | qemu_irq *pic; |
23 | e69954b9 | pbrook | void *scsi_hba;
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24 | e69954b9 | pbrook | PCIBus *pci_bus; |
25 | e69954b9 | pbrook | NICInfo *nd; |
26 | e69954b9 | pbrook | int n;
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27 | e69954b9 | pbrook | int done_smc = 0; |
28 | 9ee6e8bb | pbrook | qemu_irq cpu_irq[4];
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29 | 9ee6e8bb | pbrook | int ncpu;
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30 | e69954b9 | pbrook | |
31 | 3371d272 | pbrook | if (!cpu_model)
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32 | 3371d272 | pbrook | cpu_model = "arm926";
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33 | 9ee6e8bb | pbrook | /* FIXME: obey smp_cpus. */
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34 | 9ee6e8bb | pbrook | if (strcmp(cpu_model, "arm11mpcore") == 0) { |
35 | 9ee6e8bb | pbrook | ncpu = 4;
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36 | 9ee6e8bb | pbrook | } else {
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37 | 9ee6e8bb | pbrook | ncpu = 1;
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38 | 9ee6e8bb | pbrook | } |
39 | 9ee6e8bb | pbrook | |
40 | 9ee6e8bb | pbrook | for (n = 0; n < ncpu; n++) { |
41 | 9ee6e8bb | pbrook | env = cpu_init(cpu_model); |
42 | 9ee6e8bb | pbrook | if (!env) {
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43 | 9ee6e8bb | pbrook | fprintf(stderr, "Unable to find CPU definition\n");
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44 | 9ee6e8bb | pbrook | exit(1);
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45 | 9ee6e8bb | pbrook | } |
46 | 9ee6e8bb | pbrook | pic = arm_pic_init_cpu(env); |
47 | 9ee6e8bb | pbrook | cpu_irq[n] = pic[ARM_PIC_CPU_IRQ]; |
48 | 9ee6e8bb | pbrook | if (n > 0) { |
49 | 9ee6e8bb | pbrook | /* Set entry point for secondary CPUs. This assumes we're using
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50 | 9ee6e8bb | pbrook | the init code from arm_boot.c. Real hardware resets all CPUs
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51 | 9ee6e8bb | pbrook | the same. */
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52 | 9ee6e8bb | pbrook | env->regs[15] = 0x80000000; |
53 | 9ee6e8bb | pbrook | } |
54 | aaed909a | bellard | } |
55 | aaed909a | bellard | |
56 | e69954b9 | pbrook | /* ??? RAM shoud repeat to fill physical memory space. */
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57 | e69954b9 | pbrook | /* SDRAM at address zero. */
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58 | e69954b9 | pbrook | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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59 | e69954b9 | pbrook | |
60 | e69954b9 | pbrook | arm_sysctl_init(0x10000000, 0xc1400400); |
61 | 9ee6e8bb | pbrook | |
62 | 9ee6e8bb | pbrook | if (ncpu == 1) { |
63 | 9ee6e8bb | pbrook | /* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3
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64 | 9ee6e8bb | pbrook | is nIRQ (there are inconsistencies). However Linux 2.6.17 expects
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65 | 9ee6e8bb | pbrook | GIC1 to be nIRQ and ignores all the others, so do that for now. */
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66 | 9ee6e8bb | pbrook | pic = realview_gic_init(0x10040000, cpu_irq[0]); |
67 | 9ee6e8bb | pbrook | } else {
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68 | 9ee6e8bb | pbrook | pic = mpcore_irq_init(cpu_irq); |
69 | 9ee6e8bb | pbrook | } |
70 | 9ee6e8bb | pbrook | |
71 | d537cf6c | pbrook | pl050_init(0x10006000, pic[20], 0); |
72 | d537cf6c | pbrook | pl050_init(0x10007000, pic[21], 1); |
73 | e69954b9 | pbrook | |
74 | 9ee6e8bb | pbrook | pl011_init(0x10009000, pic[12], serial_hds[0], PL011_ARM); |
75 | 9ee6e8bb | pbrook | pl011_init(0x1000a000, pic[13], serial_hds[1], PL011_ARM); |
76 | 9ee6e8bb | pbrook | pl011_init(0x1000b000, pic[14], serial_hds[2], PL011_ARM); |
77 | 9ee6e8bb | pbrook | pl011_init(0x1000c000, pic[15], serial_hds[3], PL011_ARM); |
78 | e69954b9 | pbrook | |
79 | e69954b9 | pbrook | /* DMA controller is optional, apparently. */
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80 | d537cf6c | pbrook | pl080_init(0x10030000, pic[24], 2); |
81 | e69954b9 | pbrook | |
82 | d537cf6c | pbrook | sp804_init(0x10011000, pic[4]); |
83 | d537cf6c | pbrook | sp804_init(0x10012000, pic[5]); |
84 | e69954b9 | pbrook | |
85 | d537cf6c | pbrook | pl110_init(ds, 0x10020000, pic[23], 1); |
86 | e69954b9 | pbrook | |
87 | d537cf6c | pbrook | pl181_init(0x10005000, sd_bdrv, pic[17], pic[18]); |
88 | a1bb27b1 | pbrook | |
89 | 7e1543c2 | pbrook | pl031_init(0x10017000, pic[10]); |
90 | 7e1543c2 | pbrook | |
91 | e69954b9 | pbrook | pci_bus = pci_vpb_init(pic, 48, 1); |
92 | e69954b9 | pbrook | if (usb_enabled) {
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93 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
94 | e69954b9 | pbrook | } |
95 | e69954b9 | pbrook | scsi_hba = lsi_scsi_init(pci_bus, -1);
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96 | e69954b9 | pbrook | for (n = 0; n < MAX_DISKS; n++) { |
97 | e69954b9 | pbrook | if (bs_table[n]) {
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98 | e69954b9 | pbrook | lsi_scsi_attach(scsi_hba, bs_table[n], n); |
99 | e69954b9 | pbrook | } |
100 | e69954b9 | pbrook | } |
101 | e69954b9 | pbrook | for(n = 0; n < nb_nics; n++) { |
102 | e69954b9 | pbrook | nd = &nd_table[n]; |
103 | e69954b9 | pbrook | if (!nd->model)
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104 | e69954b9 | pbrook | nd->model = done_smc ? "rtl8139" : "smc91c111"; |
105 | e69954b9 | pbrook | if (strcmp(nd->model, "smc91c111") == 0) { |
106 | d537cf6c | pbrook | smc91c111_init(nd, 0x4e000000, pic[28]); |
107 | e69954b9 | pbrook | } else {
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108 | abcebc7e | ths | pci_nic_init(pci_bus, nd, -1);
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109 | e69954b9 | pbrook | } |
110 | e69954b9 | pbrook | } |
111 | e69954b9 | pbrook | |
112 | e69954b9 | pbrook | /* Memory map for RealView Emulation Baseboard: */
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113 | e69954b9 | pbrook | /* 0x10000000 System registers. */
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114 | e69954b9 | pbrook | /* 0x10001000 System controller. */
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115 | e69954b9 | pbrook | /* 0x10002000 Two-Wire Serial Bus. */
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116 | e69954b9 | pbrook | /* 0x10003000 Reserved. */
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117 | e69954b9 | pbrook | /* 0x10004000 AACI. */
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118 | e69954b9 | pbrook | /* 0x10005000 MCI. */
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119 | e69954b9 | pbrook | /* 0x10006000 KMI0. */
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120 | e69954b9 | pbrook | /* 0x10007000 KMI1. */
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121 | e69954b9 | pbrook | /* 0x10008000 Character LCD. */
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122 | e69954b9 | pbrook | /* 0x10009000 UART0. */
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123 | e69954b9 | pbrook | /* 0x1000a000 UART1. */
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124 | e69954b9 | pbrook | /* 0x1000b000 UART2. */
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125 | e69954b9 | pbrook | /* 0x1000c000 UART3. */
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126 | e69954b9 | pbrook | /* 0x1000d000 SSPI. */
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127 | e69954b9 | pbrook | /* 0x1000e000 SCI. */
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128 | e69954b9 | pbrook | /* 0x1000f000 Reserved. */
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129 | e69954b9 | pbrook | /* 0x10010000 Watchdog. */
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130 | e69954b9 | pbrook | /* 0x10011000 Timer 0+1. */
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131 | e69954b9 | pbrook | /* 0x10012000 Timer 2+3. */
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132 | e69954b9 | pbrook | /* 0x10013000 GPIO 0. */
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133 | e69954b9 | pbrook | /* 0x10014000 GPIO 1. */
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134 | e69954b9 | pbrook | /* 0x10015000 GPIO 2. */
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135 | e69954b9 | pbrook | /* 0x10016000 Reserved. */
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136 | 7e1543c2 | pbrook | /* 0x10017000 RTC. */
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137 | e69954b9 | pbrook | /* 0x10018000 DMC. */
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138 | e69954b9 | pbrook | /* 0x10019000 PCI controller config. */
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139 | e69954b9 | pbrook | /* 0x10020000 CLCD. */
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140 | e69954b9 | pbrook | /* 0x10030000 DMA Controller. */
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141 | 9ee6e8bb | pbrook | /* 0x10040000 GIC1. */
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142 | 9ee6e8bb | pbrook | /* 0x10050000 GIC2. */
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143 | 9ee6e8bb | pbrook | /* 0x10060000 GIC3. */
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144 | 9ee6e8bb | pbrook | /* 0x10070000 GIC4. */
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145 | e69954b9 | pbrook | /* 0x10080000 SMC. */
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146 | e69954b9 | pbrook | /* 0x40000000 NOR flash. */
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147 | e69954b9 | pbrook | /* 0x44000000 DoC flash. */
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148 | e69954b9 | pbrook | /* 0x48000000 SRAM. */
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149 | e69954b9 | pbrook | /* 0x4c000000 Configuration flash. */
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150 | e69954b9 | pbrook | /* 0x4e000000 Ethernet. */
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151 | e69954b9 | pbrook | /* 0x4f000000 USB. */
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152 | e69954b9 | pbrook | /* 0x50000000 PISMO. */
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153 | e69954b9 | pbrook | /* 0x54000000 PISMO. */
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154 | e69954b9 | pbrook | /* 0x58000000 PISMO. */
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155 | e69954b9 | pbrook | /* 0x5c000000 PISMO. */
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156 | e69954b9 | pbrook | /* 0x60000000 PCI. */
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157 | e69954b9 | pbrook | /* 0x61000000 PCI Self Config. */
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158 | e69954b9 | pbrook | /* 0x62000000 PCI Config. */
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159 | e69954b9 | pbrook | /* 0x63000000 PCI IO. */
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160 | e69954b9 | pbrook | /* 0x64000000 PCI mem 0. */
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161 | e69954b9 | pbrook | /* 0x68000000 PCI mem 1. */
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162 | e69954b9 | pbrook | /* 0x6c000000 PCI mem 2. */
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163 | e69954b9 | pbrook | |
164 | 9ee6e8bb | pbrook | arm_load_kernel(first_cpu, ram_size, kernel_filename, kernel_cmdline, |
165 | 9d551997 | balrog | initrd_filename, 0x33b, 0x0); |
166 | 9ee6e8bb | pbrook | |
167 | 9ee6e8bb | pbrook | /* ??? Hack to map an additional page of ram for the secondary CPU
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168 | 9ee6e8bb | pbrook | startup code. I guess this works on real hardware because the
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169 | 9ee6e8bb | pbrook | BootROM happens to be in ROM/flash or in memory that isn't clobbered
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170 | 9ee6e8bb | pbrook | until after Linux boots the secondary CPUs. */
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171 | 9ee6e8bb | pbrook | cpu_register_physical_memory(0x80000000, 0x1000, IO_MEM_RAM + ram_size); |
172 | e69954b9 | pbrook | } |
173 | e69954b9 | pbrook | |
174 | e69954b9 | pbrook | QEMUMachine realview_machine = { |
175 | e69954b9 | pbrook | "realview",
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176 | e69954b9 | pbrook | "ARM RealView Emulation Baseboard (ARM926EJ-S)",
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177 | e69954b9 | pbrook | realview_init |
178 | e69954b9 | pbrook | }; |