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1 | b9adb4a6 | bellard | /* General "disassemble this chunk" code. Used for debugging. */
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2 | 5bbe9299 | bellard | #include "config.h" |
3 | b9adb4a6 | bellard | #include "dis-asm.h" |
4 | b9adb4a6 | bellard | #include "elf.h" |
5 | aa0aa4fa | bellard | #include <errno.h> |
6 | b9adb4a6 | bellard | |
7 | c6105c0a | bellard | #include "cpu.h" |
8 | c6105c0a | bellard | #include "exec-all.h" |
9 | 9307c4c1 | bellard | #include "disas.h" |
10 | c6105c0a | bellard | |
11 | b9adb4a6 | bellard | /* Filled in by elfload.c. Simplistic, but will do for now. */
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12 | e80cfcfc | bellard | struct syminfo *syminfos = NULL; |
13 | b9adb4a6 | bellard | |
14 | aa0aa4fa | bellard | /* Get LENGTH bytes from info's buffer, at target address memaddr.
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15 | aa0aa4fa | bellard | Transfer them to myaddr. */
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16 | aa0aa4fa | bellard | int
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17 | aa0aa4fa | bellard | buffer_read_memory (memaddr, myaddr, length, info) |
18 | aa0aa4fa | bellard | bfd_vma memaddr; |
19 | aa0aa4fa | bellard | bfd_byte *myaddr; |
20 | aa0aa4fa | bellard | int length;
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21 | aa0aa4fa | bellard | struct disassemble_info *info;
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22 | aa0aa4fa | bellard | { |
23 | c6105c0a | bellard | if (memaddr < info->buffer_vma
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24 | c6105c0a | bellard | || memaddr + length > info->buffer_vma + info->buffer_length) |
25 | c6105c0a | bellard | /* Out of bounds. Use EIO because GDB uses it. */
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26 | c6105c0a | bellard | return EIO;
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27 | c6105c0a | bellard | memcpy (myaddr, info->buffer + (memaddr - info->buffer_vma), length); |
28 | c6105c0a | bellard | return 0; |
29 | aa0aa4fa | bellard | } |
30 | aa0aa4fa | bellard | |
31 | c6105c0a | bellard | /* Get LENGTH bytes from info's buffer, at target address memaddr.
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32 | c6105c0a | bellard | Transfer them to myaddr. */
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33 | c6105c0a | bellard | static int |
34 | c27004ec | bellard | target_read_memory (bfd_vma memaddr, |
35 | c27004ec | bellard | bfd_byte *myaddr, |
36 | c27004ec | bellard | int length,
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37 | c27004ec | bellard | struct disassemble_info *info)
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38 | c6105c0a | bellard | { |
39 | c6105c0a | bellard | int i;
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40 | c6105c0a | bellard | for(i = 0; i < length; i++) { |
41 | c27004ec | bellard | myaddr[i] = ldub_code(memaddr + i); |
42 | c6105c0a | bellard | } |
43 | c6105c0a | bellard | return 0; |
44 | c6105c0a | bellard | } |
45 | c6105c0a | bellard | |
46 | aa0aa4fa | bellard | /* Print an error message. We can assume that this is in response to
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47 | aa0aa4fa | bellard | an error return from buffer_read_memory. */
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48 | aa0aa4fa | bellard | void
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49 | aa0aa4fa | bellard | perror_memory (status, memaddr, info) |
50 | aa0aa4fa | bellard | int status;
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51 | aa0aa4fa | bellard | bfd_vma memaddr; |
52 | aa0aa4fa | bellard | struct disassemble_info *info;
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53 | aa0aa4fa | bellard | { |
54 | aa0aa4fa | bellard | if (status != EIO)
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55 | aa0aa4fa | bellard | /* Can't happen. */
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56 | aa0aa4fa | bellard | (*info->fprintf_func) (info->stream, "Unknown error %d\n", status);
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57 | aa0aa4fa | bellard | else
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58 | aa0aa4fa | bellard | /* Actually, address between memaddr and memaddr + len was
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59 | aa0aa4fa | bellard | out of bounds. */
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60 | aa0aa4fa | bellard | (*info->fprintf_func) (info->stream, |
61 | 26a76461 | bellard | "Address 0x%" PRIx64 " is out of bounds.\n", memaddr); |
62 | aa0aa4fa | bellard | } |
63 | aa0aa4fa | bellard | |
64 | aa0aa4fa | bellard | /* This could be in a separate file, to save miniscule amounts of space
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65 | aa0aa4fa | bellard | in statically linked executables. */
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66 | aa0aa4fa | bellard | |
67 | aa0aa4fa | bellard | /* Just print the address is hex. This is included for completeness even
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68 | aa0aa4fa | bellard | though both GDB and objdump provide their own (to print symbolic
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69 | aa0aa4fa | bellard | addresses). */
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70 | aa0aa4fa | bellard | |
71 | aa0aa4fa | bellard | void
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72 | aa0aa4fa | bellard | generic_print_address (addr, info) |
73 | aa0aa4fa | bellard | bfd_vma addr; |
74 | aa0aa4fa | bellard | struct disassemble_info *info;
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75 | aa0aa4fa | bellard | { |
76 | 26a76461 | bellard | (*info->fprintf_func) (info->stream, "0x%" PRIx64, addr);
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77 | aa0aa4fa | bellard | } |
78 | aa0aa4fa | bellard | |
79 | aa0aa4fa | bellard | /* Just return the given address. */
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80 | aa0aa4fa | bellard | |
81 | aa0aa4fa | bellard | int
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82 | aa0aa4fa | bellard | generic_symbol_at_address (addr, info) |
83 | aa0aa4fa | bellard | bfd_vma addr; |
84 | aa0aa4fa | bellard | struct disassemble_info * info;
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85 | aa0aa4fa | bellard | { |
86 | aa0aa4fa | bellard | return 1; |
87 | aa0aa4fa | bellard | } |
88 | aa0aa4fa | bellard | |
89 | aa0aa4fa | bellard | bfd_vma bfd_getl32 (const bfd_byte *addr)
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90 | aa0aa4fa | bellard | { |
91 | aa0aa4fa | bellard | unsigned long v; |
92 | aa0aa4fa | bellard | |
93 | aa0aa4fa | bellard | v = (unsigned long) addr[0]; |
94 | aa0aa4fa | bellard | v |= (unsigned long) addr[1] << 8; |
95 | aa0aa4fa | bellard | v |= (unsigned long) addr[2] << 16; |
96 | aa0aa4fa | bellard | v |= (unsigned long) addr[3] << 24; |
97 | aa0aa4fa | bellard | return (bfd_vma) v;
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98 | aa0aa4fa | bellard | } |
99 | aa0aa4fa | bellard | |
100 | aa0aa4fa | bellard | bfd_vma bfd_getb32 (const bfd_byte *addr)
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101 | aa0aa4fa | bellard | { |
102 | aa0aa4fa | bellard | unsigned long v; |
103 | aa0aa4fa | bellard | |
104 | aa0aa4fa | bellard | v = (unsigned long) addr[0] << 24; |
105 | aa0aa4fa | bellard | v |= (unsigned long) addr[1] << 16; |
106 | aa0aa4fa | bellard | v |= (unsigned long) addr[2] << 8; |
107 | aa0aa4fa | bellard | v |= (unsigned long) addr[3]; |
108 | aa0aa4fa | bellard | return (bfd_vma) v;
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109 | aa0aa4fa | bellard | } |
110 | aa0aa4fa | bellard | |
111 | 6af0bf9c | bellard | bfd_vma bfd_getl16 (const bfd_byte *addr)
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112 | 6af0bf9c | bellard | { |
113 | 6af0bf9c | bellard | unsigned long v; |
114 | 6af0bf9c | bellard | |
115 | 6af0bf9c | bellard | v = (unsigned long) addr[0]; |
116 | 6af0bf9c | bellard | v |= (unsigned long) addr[1] << 8; |
117 | 6af0bf9c | bellard | return (bfd_vma) v;
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118 | 6af0bf9c | bellard | } |
119 | 6af0bf9c | bellard | |
120 | 6af0bf9c | bellard | bfd_vma bfd_getb16 (const bfd_byte *addr)
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121 | 6af0bf9c | bellard | { |
122 | 6af0bf9c | bellard | unsigned long v; |
123 | 6af0bf9c | bellard | |
124 | 6af0bf9c | bellard | v = (unsigned long) addr[0] << 24; |
125 | 6af0bf9c | bellard | v |= (unsigned long) addr[1] << 16; |
126 | 6af0bf9c | bellard | return (bfd_vma) v;
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127 | 6af0bf9c | bellard | } |
128 | 6af0bf9c | bellard | |
129 | c2d551ff | bellard | #ifdef TARGET_ARM
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130 | c2d551ff | bellard | static int |
131 | c2d551ff | bellard | print_insn_thumb1(bfd_vma pc, disassemble_info *info) |
132 | c2d551ff | bellard | { |
133 | c2d551ff | bellard | return print_insn_arm(pc | 1, info); |
134 | c2d551ff | bellard | } |
135 | c2d551ff | bellard | #endif
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136 | c2d551ff | bellard | |
137 | e91c8a77 | ths | /* Disassemble this for me please... (debugging). 'flags' has the following
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138 | c2d551ff | bellard | values:
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139 | c2d551ff | bellard | i386 - nonzero means 16 bit code
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140 | 5fafdf24 | ths | arm - nonzero means thumb code
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141 | 6a00d601 | bellard | ppc - nonzero means little endian
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142 | c2d551ff | bellard | other targets - unused
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143 | c2d551ff | bellard | */
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144 | 83b34f8b | bellard | void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) |
145 | b9adb4a6 | bellard | { |
146 | c27004ec | bellard | target_ulong pc; |
147 | b9adb4a6 | bellard | int count;
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148 | b9adb4a6 | bellard | struct disassemble_info disasm_info;
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149 | b9adb4a6 | bellard | int (*print_insn)(bfd_vma pc, disassemble_info *info);
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150 | b9adb4a6 | bellard | |
151 | b9adb4a6 | bellard | INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); |
152 | b9adb4a6 | bellard | |
153 | c27004ec | bellard | disasm_info.read_memory_func = target_read_memory; |
154 | c27004ec | bellard | disasm_info.buffer_vma = code; |
155 | c27004ec | bellard | disasm_info.buffer_length = size; |
156 | c27004ec | bellard | |
157 | c27004ec | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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158 | c27004ec | bellard | disasm_info.endian = BFD_ENDIAN_BIG; |
159 | c27004ec | bellard | #else
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160 | c27004ec | bellard | disasm_info.endian = BFD_ENDIAN_LITTLE; |
161 | c27004ec | bellard | #endif
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162 | c27004ec | bellard | #if defined(TARGET_I386)
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163 | c27004ec | bellard | if (flags == 2) |
164 | c27004ec | bellard | disasm_info.mach = bfd_mach_x86_64; |
165 | 5fafdf24 | ths | else if (flags == 1) |
166 | c27004ec | bellard | disasm_info.mach = bfd_mach_i386_i8086; |
167 | c27004ec | bellard | else
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168 | c27004ec | bellard | disasm_info.mach = bfd_mach_i386_i386; |
169 | c27004ec | bellard | print_insn = print_insn_i386; |
170 | c27004ec | bellard | #elif defined(TARGET_ARM)
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171 | c2d551ff | bellard | if (flags)
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172 | c2d551ff | bellard | print_insn = print_insn_thumb1; |
173 | c2d551ff | bellard | else
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174 | c2d551ff | bellard | print_insn = print_insn_arm; |
175 | c27004ec | bellard | #elif defined(TARGET_SPARC)
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176 | c27004ec | bellard | print_insn = print_insn_sparc; |
177 | 3475187d | bellard | #ifdef TARGET_SPARC64
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178 | 3475187d | bellard | disasm_info.mach = bfd_mach_sparc_v9b; |
179 | 3b46e624 | ths | #endif
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180 | c27004ec | bellard | #elif defined(TARGET_PPC)
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181 | 237c0af0 | j_mayer | if (flags >> 16) |
182 | 111bfab3 | bellard | disasm_info.endian = BFD_ENDIAN_LITTLE; |
183 | 237c0af0 | j_mayer | if (flags & 0xFFFF) { |
184 | 237c0af0 | j_mayer | /* If we have a precise definitions of the instructions set, use it */
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185 | 237c0af0 | j_mayer | disasm_info.mach = flags & 0xFFFF;
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186 | 237c0af0 | j_mayer | } else {
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187 | a2458627 | bellard | #ifdef TARGET_PPC64
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188 | 237c0af0 | j_mayer | disasm_info.mach = bfd_mach_ppc64; |
189 | a2458627 | bellard | #else
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190 | 237c0af0 | j_mayer | disasm_info.mach = bfd_mach_ppc; |
191 | a2458627 | bellard | #endif
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192 | 237c0af0 | j_mayer | } |
193 | c27004ec | bellard | print_insn = print_insn_ppc; |
194 | e6e5906b | pbrook | #elif defined(TARGET_M68K)
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195 | e6e5906b | pbrook | print_insn = print_insn_m68k; |
196 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
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197 | 76b3030c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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198 | 6af0bf9c | bellard | print_insn = print_insn_big_mips; |
199 | 76b3030c | bellard | #else
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200 | 76b3030c | bellard | print_insn = print_insn_little_mips; |
201 | 76b3030c | bellard | #endif
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202 | fdf9b3e8 | bellard | #elif defined(TARGET_SH4)
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203 | fdf9b3e8 | bellard | disasm_info.mach = bfd_mach_sh4; |
204 | fdf9b3e8 | bellard | print_insn = print_insn_sh; |
205 | eddf68a6 | j_mayer | #elif defined(TARGET_ALPHA)
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206 | eddf68a6 | j_mayer | disasm_info.mach = bfd_mach_alpha; |
207 | eddf68a6 | j_mayer | print_insn = print_insn_alpha; |
208 | a25fd137 | ths | #elif defined(TARGET_CRIS)
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209 | a25fd137 | ths | disasm_info.mach = bfd_mach_cris_v32; |
210 | a25fd137 | ths | print_insn = print_insn_crisv32; |
211 | c27004ec | bellard | #else
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212 | b8076a74 | bellard | fprintf(out, "0x" TARGET_FMT_lx
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213 | b8076a74 | bellard | ": Asm output not supported on this arch\n", code);
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214 | c27004ec | bellard | return;
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215 | c6105c0a | bellard | #endif
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216 | c6105c0a | bellard | |
217 | c27004ec | bellard | for (pc = code; pc < code + size; pc += count) {
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218 | fa15e030 | bellard | fprintf(out, "0x" TARGET_FMT_lx ": ", pc); |
219 | c27004ec | bellard | count = print_insn(pc, &disasm_info); |
220 | c27004ec | bellard | #if 0
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221 | c27004ec | bellard | {
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222 | c27004ec | bellard | int i;
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223 | c27004ec | bellard | uint8_t b;
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224 | c27004ec | bellard | fprintf(out, " {");
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225 | c27004ec | bellard | for(i = 0; i < count; i++) {
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226 | c27004ec | bellard | target_read_memory(pc + i, &b, 1, &disasm_info);
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227 | c27004ec | bellard | fprintf(out, " %02x", b);
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228 | c27004ec | bellard | }
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229 | c27004ec | bellard | fprintf(out, " }");
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230 | c27004ec | bellard | }
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231 | c27004ec | bellard | #endif
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232 | c27004ec | bellard | fprintf(out, "\n");
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233 | c27004ec | bellard | if (count < 0) |
234 | c27004ec | bellard | break;
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235 | c27004ec | bellard | } |
236 | c27004ec | bellard | } |
237 | c27004ec | bellard | |
238 | c27004ec | bellard | /* Disassemble this for me please... (debugging). */
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239 | c27004ec | bellard | void disas(FILE *out, void *code, unsigned long size) |
240 | c27004ec | bellard | { |
241 | c27004ec | bellard | unsigned long pc; |
242 | c27004ec | bellard | int count;
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243 | c27004ec | bellard | struct disassemble_info disasm_info;
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244 | c27004ec | bellard | int (*print_insn)(bfd_vma pc, disassemble_info *info);
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245 | c27004ec | bellard | |
246 | c27004ec | bellard | INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); |
247 | c27004ec | bellard | |
248 | b9adb4a6 | bellard | disasm_info.buffer = code; |
249 | b9adb4a6 | bellard | disasm_info.buffer_vma = (unsigned long)code; |
250 | b9adb4a6 | bellard | disasm_info.buffer_length = size; |
251 | b9adb4a6 | bellard | |
252 | b9adb4a6 | bellard | #ifdef WORDS_BIGENDIAN
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253 | c27004ec | bellard | disasm_info.endian = BFD_ENDIAN_BIG; |
254 | b9adb4a6 | bellard | #else
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255 | c27004ec | bellard | disasm_info.endian = BFD_ENDIAN_LITTLE; |
256 | b9adb4a6 | bellard | #endif
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257 | bc51c5c9 | bellard | #if defined(__i386__)
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258 | c27004ec | bellard | disasm_info.mach = bfd_mach_i386_i386; |
259 | c27004ec | bellard | print_insn = print_insn_i386; |
260 | bc51c5c9 | bellard | #elif defined(__x86_64__)
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261 | c27004ec | bellard | disasm_info.mach = bfd_mach_x86_64; |
262 | c27004ec | bellard | print_insn = print_insn_i386; |
263 | b9adb4a6 | bellard | #elif defined(__powerpc__)
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264 | c27004ec | bellard | print_insn = print_insn_ppc; |
265 | a993ba85 | bellard | #elif defined(__alpha__)
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266 | c27004ec | bellard | print_insn = print_insn_alpha; |
267 | aa0aa4fa | bellard | #elif defined(__sparc__)
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268 | c27004ec | bellard | print_insn = print_insn_sparc; |
269 | 6ecd4534 | blueswir1 | #if defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
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270 | 6ecd4534 | blueswir1 | disasm_info.mach = bfd_mach_sparc_v9b; |
271 | 6ecd4534 | blueswir1 | #endif
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272 | 5fafdf24 | ths | #elif defined(__arm__)
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273 | c27004ec | bellard | print_insn = print_insn_arm; |
274 | 6af0bf9c | bellard | #elif defined(__MIPSEB__)
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275 | 6af0bf9c | bellard | print_insn = print_insn_big_mips; |
276 | 6af0bf9c | bellard | #elif defined(__MIPSEL__)
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277 | 6af0bf9c | bellard | print_insn = print_insn_little_mips; |
278 | 48024e4a | bellard | #elif defined(__m68k__)
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279 | 48024e4a | bellard | print_insn = print_insn_m68k; |
280 | 8f860bb8 | ths | #elif defined(__s390__)
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281 | 8f860bb8 | ths | print_insn = print_insn_s390; |
282 | f54b3f92 | aurel32 | #elif defined(__hppa__)
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283 | f54b3f92 | aurel32 | print_insn = print_insn_hppa; |
284 | b9adb4a6 | bellard | #else
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285 | b8076a74 | bellard | fprintf(out, "0x%lx: Asm output not supported on this arch\n",
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286 | b8076a74 | bellard | (long) code);
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287 | c27004ec | bellard | return;
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288 | b9adb4a6 | bellard | #endif
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289 | c27004ec | bellard | for (pc = (unsigned long)code; pc < (unsigned long)code + size; pc += count) { |
290 | c27004ec | bellard | fprintf(out, "0x%08lx: ", pc);
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291 | aa0aa4fa | bellard | #ifdef __arm__
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292 | 46152182 | pbrook | /* since data is included in the code, it is better to
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293 | aa0aa4fa | bellard | display code data too */
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294 | 46152182 | pbrook | fprintf(out, "%08x ", (int)bfd_getl32((const bfd_byte *)pc)); |
295 | aa0aa4fa | bellard | #endif
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296 | c27004ec | bellard | count = print_insn(pc, &disasm_info); |
297 | b9adb4a6 | bellard | fprintf(out, "\n");
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298 | b9adb4a6 | bellard | if (count < 0) |
299 | b9adb4a6 | bellard | break;
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300 | b9adb4a6 | bellard | } |
301 | b9adb4a6 | bellard | } |
302 | b9adb4a6 | bellard | |
303 | b9adb4a6 | bellard | /* Look up symbol for debugging purpose. Returns "" if unknown. */
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304 | c27004ec | bellard | const char *lookup_symbol(target_ulong orig_addr) |
305 | b9adb4a6 | bellard | { |
306 | b9adb4a6 | bellard | unsigned int i; |
307 | b9adb4a6 | bellard | /* Hack, because we know this is x86. */
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308 | e80cfcfc | bellard | Elf32_Sym *sym; |
309 | e80cfcfc | bellard | struct syminfo *s;
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310 | b3ecf620 | bellard | target_ulong addr; |
311 | 3b46e624 | ths | |
312 | e80cfcfc | bellard | for (s = syminfos; s; s = s->next) {
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313 | e80cfcfc | bellard | sym = s->disas_symtab; |
314 | e80cfcfc | bellard | for (i = 0; i < s->disas_num_syms; i++) { |
315 | e80cfcfc | bellard | if (sym[i].st_shndx == SHN_UNDEF
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316 | e80cfcfc | bellard | || sym[i].st_shndx >= SHN_LORESERVE) |
317 | e80cfcfc | bellard | continue;
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318 | b9adb4a6 | bellard | |
319 | e80cfcfc | bellard | if (ELF_ST_TYPE(sym[i].st_info) != STT_FUNC)
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320 | e80cfcfc | bellard | continue;
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321 | b9adb4a6 | bellard | |
322 | b3ecf620 | bellard | addr = sym[i].st_value; |
323 | a8fcf883 | ths | #if defined(TARGET_ARM) || defined (TARGET_MIPS)
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324 | a8fcf883 | ths | /* The bottom address bit marks a Thumb or MIPS16 symbol. */
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325 | b3ecf620 | bellard | addr &= ~(target_ulong)1;
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326 | b3ecf620 | bellard | #endif
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327 | b3ecf620 | bellard | if (orig_addr >= addr
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328 | b3ecf620 | bellard | && orig_addr < addr + sym[i].st_size) |
329 | e80cfcfc | bellard | return s->disas_strtab + sym[i].st_name;
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330 | e80cfcfc | bellard | } |
331 | b9adb4a6 | bellard | } |
332 | b9adb4a6 | bellard | return ""; |
333 | b9adb4a6 | bellard | } |
334 | 9307c4c1 | bellard | |
335 | 9307c4c1 | bellard | #if !defined(CONFIG_USER_ONLY)
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336 | 9307c4c1 | bellard | |
337 | 3d2cfdf1 | bellard | void term_vprintf(const char *fmt, va_list ap); |
338 | 3d2cfdf1 | bellard | void term_printf(const char *fmt, ...); |
339 | 3d2cfdf1 | bellard | |
340 | 9307c4c1 | bellard | static int monitor_disas_is_physical; |
341 | 6a00d601 | bellard | static CPUState *monitor_disas_env;
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342 | 9307c4c1 | bellard | |
343 | 9307c4c1 | bellard | static int |
344 | 9307c4c1 | bellard | monitor_read_memory (memaddr, myaddr, length, info) |
345 | 9307c4c1 | bellard | bfd_vma memaddr; |
346 | 9307c4c1 | bellard | bfd_byte *myaddr; |
347 | 9307c4c1 | bellard | int length;
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348 | 9307c4c1 | bellard | struct disassemble_info *info;
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349 | 9307c4c1 | bellard | { |
350 | 9307c4c1 | bellard | if (monitor_disas_is_physical) {
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351 | 9307c4c1 | bellard | cpu_physical_memory_rw(memaddr, myaddr, length, 0);
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352 | 9307c4c1 | bellard | } else {
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353 | 6a00d601 | bellard | cpu_memory_rw_debug(monitor_disas_env, memaddr,myaddr, length, 0);
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354 | 9307c4c1 | bellard | } |
355 | 9307c4c1 | bellard | return 0; |
356 | 9307c4c1 | bellard | } |
357 | 9307c4c1 | bellard | |
358 | 3d2cfdf1 | bellard | static int monitor_fprintf(FILE *stream, const char *fmt, ...) |
359 | 3d2cfdf1 | bellard | { |
360 | 3d2cfdf1 | bellard | va_list ap; |
361 | 3d2cfdf1 | bellard | va_start(ap, fmt); |
362 | 3d2cfdf1 | bellard | term_vprintf(fmt, ap); |
363 | 3d2cfdf1 | bellard | va_end(ap); |
364 | 3d2cfdf1 | bellard | return 0; |
365 | 3d2cfdf1 | bellard | } |
366 | 3d2cfdf1 | bellard | |
367 | 6a00d601 | bellard | void monitor_disas(CPUState *env,
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368 | 6a00d601 | bellard | target_ulong pc, int nb_insn, int is_physical, int flags) |
369 | 9307c4c1 | bellard | { |
370 | 9307c4c1 | bellard | int count, i;
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371 | 9307c4c1 | bellard | struct disassemble_info disasm_info;
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372 | 9307c4c1 | bellard | int (*print_insn)(bfd_vma pc, disassemble_info *info);
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373 | 9307c4c1 | bellard | |
374 | 3d2cfdf1 | bellard | INIT_DISASSEMBLE_INFO(disasm_info, NULL, monitor_fprintf);
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375 | 9307c4c1 | bellard | |
376 | 6a00d601 | bellard | monitor_disas_env = env; |
377 | 9307c4c1 | bellard | monitor_disas_is_physical = is_physical; |
378 | 9307c4c1 | bellard | disasm_info.read_memory_func = monitor_read_memory; |
379 | 9307c4c1 | bellard | |
380 | 9307c4c1 | bellard | disasm_info.buffer_vma = pc; |
381 | 9307c4c1 | bellard | |
382 | 9307c4c1 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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383 | 9307c4c1 | bellard | disasm_info.endian = BFD_ENDIAN_BIG; |
384 | 9307c4c1 | bellard | #else
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385 | 9307c4c1 | bellard | disasm_info.endian = BFD_ENDIAN_LITTLE; |
386 | 9307c4c1 | bellard | #endif
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387 | 9307c4c1 | bellard | #if defined(TARGET_I386)
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388 | fa15e030 | bellard | if (flags == 2) |
389 | fa15e030 | bellard | disasm_info.mach = bfd_mach_x86_64; |
390 | 5fafdf24 | ths | else if (flags == 1) |
391 | 9307c4c1 | bellard | disasm_info.mach = bfd_mach_i386_i8086; |
392 | fa15e030 | bellard | else
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393 | fa15e030 | bellard | disasm_info.mach = bfd_mach_i386_i386; |
394 | 9307c4c1 | bellard | print_insn = print_insn_i386; |
395 | 9307c4c1 | bellard | #elif defined(TARGET_ARM)
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396 | 9307c4c1 | bellard | print_insn = print_insn_arm; |
397 | cbd669da | ths | #elif defined(TARGET_ALPHA)
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398 | cbd669da | ths | print_insn = print_insn_alpha; |
399 | 9307c4c1 | bellard | #elif defined(TARGET_SPARC)
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400 | 9307c4c1 | bellard | print_insn = print_insn_sparc; |
401 | 682c4f15 | blueswir1 | #ifdef TARGET_SPARC64
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402 | 682c4f15 | blueswir1 | disasm_info.mach = bfd_mach_sparc_v9b; |
403 | 682c4f15 | blueswir1 | #endif
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404 | 9307c4c1 | bellard | #elif defined(TARGET_PPC)
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405 | a2458627 | bellard | #ifdef TARGET_PPC64
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406 | a2458627 | bellard | disasm_info.mach = bfd_mach_ppc64; |
407 | a2458627 | bellard | #else
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408 | a2458627 | bellard | disasm_info.mach = bfd_mach_ppc; |
409 | a2458627 | bellard | #endif
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410 | 9307c4c1 | bellard | print_insn = print_insn_ppc; |
411 | e6e5906b | pbrook | #elif defined(TARGET_M68K)
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412 | e6e5906b | pbrook | print_insn = print_insn_m68k; |
413 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
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414 | 76b3030c | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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415 | 6af0bf9c | bellard | print_insn = print_insn_big_mips; |
416 | 76b3030c | bellard | #else
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417 | 76b3030c | bellard | print_insn = print_insn_little_mips; |
418 | 76b3030c | bellard | #endif
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419 | 9307c4c1 | bellard | #else
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420 | b8076a74 | bellard | term_printf("0x" TARGET_FMT_lx
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421 | b8076a74 | bellard | ": Asm output not supported on this arch\n", pc);
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422 | 9307c4c1 | bellard | return;
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423 | 9307c4c1 | bellard | #endif
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424 | 9307c4c1 | bellard | |
425 | 9307c4c1 | bellard | for(i = 0; i < nb_insn; i++) { |
426 | fa15e030 | bellard | term_printf("0x" TARGET_FMT_lx ": ", pc); |
427 | 9307c4c1 | bellard | count = print_insn(pc, &disasm_info); |
428 | 3d2cfdf1 | bellard | term_printf("\n");
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429 | 9307c4c1 | bellard | if (count < 0) |
430 | 9307c4c1 | bellard | break;
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431 | 9307c4c1 | bellard | pc += count; |
432 | 9307c4c1 | bellard | } |
433 | 9307c4c1 | bellard | } |
434 | 9307c4c1 | bellard | #endif |