| 9 |
9 |
#include "qemu-common.h"
|
| 10 |
10 |
#include "host-utils.h"
|
| 11 |
11 |
|
|
12 |
static uint32_t cortexa9_cp15_c0_c1[8] =
|
|
13 |
{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
|
|
14 |
|
|
15 |
static uint32_t cortexa9_cp15_c0_c2[8] =
|
|
16 |
{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
|
|
17 |
|
| 12 |
18 |
static uint32_t cortexa8_cp15_c0_c1[8] =
|
| 13 |
19 |
{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
|
| 14 |
20 |
|
| ... | ... | |
| 101 |
107 |
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
|
| 102 |
108 |
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
|
| 103 |
109 |
break;
|
|
110 |
case ARM_CPUID_CORTEXA9:
|
|
111 |
set_feature(env, ARM_FEATURE_V6);
|
|
112 |
set_feature(env, ARM_FEATURE_V6K);
|
|
113 |
set_feature(env, ARM_FEATURE_V7);
|
|
114 |
set_feature(env, ARM_FEATURE_AUXCR);
|
|
115 |
set_feature(env, ARM_FEATURE_THUMB2);
|
|
116 |
set_feature(env, ARM_FEATURE_VFP);
|
|
117 |
set_feature(env, ARM_FEATURE_VFP3);
|
|
118 |
set_feature(env, ARM_FEATURE_VFP_FP16);
|
|
119 |
set_feature(env, ARM_FEATURE_NEON);
|
|
120 |
set_feature(env, ARM_FEATURE_THUMB2EE);
|
|
121 |
env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
|
|
122 |
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
|
|
123 |
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
|
|
124 |
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
|
|
125 |
memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
|
|
126 |
env->cp15.c0_cachetype = 0x80038003;
|
|
127 |
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
|
|
128 |
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
|
|
129 |
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
|
|
130 |
break;
|
| 104 |
131 |
case ARM_CPUID_CORTEXM3:
|
| 105 |
132 |
set_feature(env, ARM_FEATURE_V6);
|
| 106 |
133 |
set_feature(env, ARM_FEATURE_THUMB2);
|
| ... | ... | |
| 287 |
314 |
{ ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
|
| 288 |
315 |
{ ARM_CPUID_CORTEXM3, "cortex-m3"},
|
| 289 |
316 |
{ ARM_CPUID_CORTEXA8, "cortex-a8"},
|
|
317 |
{ ARM_CPUID_CORTEXA9, "cortex-a9"},
|
| 290 |
318 |
{ ARM_CPUID_TI925T, "ti925t" },
|
| 291 |
319 |
{ ARM_CPUID_PXA250, "pxa250" },
|
| 292 |
320 |
{ ARM_CPUID_PXA255, "pxa255" },
|
| ... | ... | |
| 1633 |
1661 |
case 3: /* TLB type register. */
|
| 1634 |
1662 |
return 0; /* No lockable TLB entries. */
|
| 1635 |
1663 |
case 5: /* CPU ID */
|
| 1636 |
|
return env->cpu_index;
|
|
1664 |
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
|
|
1665 |
return env->cpu_index | 0x80000900;
|
|
1666 |
} else {
|
|
1667 |
return env->cpu_index;
|
|
1668 |
}
|
| 1637 |
1669 |
default:
|
| 1638 |
1670 |
goto bad_reg;
|
| 1639 |
1671 |
}
|
| ... | ... | |
| 1697 |
1729 |
return 1;
|
| 1698 |
1730 |
case ARM_CPUID_CORTEXA8:
|
| 1699 |
1731 |
return 2;
|
|
1732 |
case ARM_CPUID_CORTEXA9:
|
|
1733 |
return 0;
|
| 1700 |
1734 |
default:
|
| 1701 |
1735 |
goto bad_reg;
|
| 1702 |
1736 |
}
|