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1	7a3f1944	bellard	/*
2	7a3f1944	bellard	SPARC translation
3	7a3f1944	bellard
4	7a3f1944	bellard	Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5	3475187d	bellard	Copyright (C) 2003-2005 Fabrice Bellard
6	7a3f1944	bellard
7	7a3f1944	bellard	This library is free software; you can redistribute it and/or
8	7a3f1944	bellard	modify it under the terms of the GNU Lesser General Public
9	7a3f1944	bellard	License as published by the Free Software Foundation; either
10	7a3f1944	bellard	version 2 of the License, or (at your option) any later version.
11	7a3f1944	bellard
12	7a3f1944	bellard	This library is distributed in the hope that it will be useful,
13	7a3f1944	bellard	but WITHOUT ANY WARRANTY; without even the implied warranty of
14	7a3f1944	bellard	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	7a3f1944	bellard	Lesser General Public License for more details.
16	7a3f1944	bellard
17	7a3f1944	bellard	You should have received a copy of the GNU Lesser General Public
18	7a3f1944	bellard	License along with this library; if not, write to the Free Software
19	7a3f1944	bellard	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20	7a3f1944	bellard	*/
21	7a3f1944	bellard
22	7a3f1944	bellard	#include <stdarg.h>
23	7a3f1944	bellard	#include <stdlib.h>
24	7a3f1944	bellard	#include <stdio.h>
25	7a3f1944	bellard	#include <string.h>
26	7a3f1944	bellard	#include <inttypes.h>
27	7a3f1944	bellard
28	7a3f1944	bellard	#include "cpu.h"
29	7a3f1944	bellard	#include "exec-all.h"
30	7a3f1944	bellard	#include "disas.h"
31	1a2fb1c0	blueswir1	#include "helper.h"
32	57fec1fe	bellard	#include "tcg-op.h"
33	7a3f1944	bellard
34	7a3f1944	bellard	#define DEBUG_DISAS
35	7a3f1944	bellard
36	72cbca10	bellard	#define DYNAMIC_PC 1 /* dynamic pc value */
37	72cbca10	bellard	#define JUMP_PC 2 /* dynamic pc value which takes only two values
38	72cbca10	bellard	according to jump_pc[T2] */
39	72cbca10	bellard
40	1a2fb1c0	blueswir1	/* global register indexes */
41	d987963a	blueswir1	static TCGv cpu_env, cpu_regwptr;
42	77f193da	blueswir1	static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
43	48d5c82b	blueswir1	static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
44	6ae20372	blueswir1	static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
45	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
46	dc99a3f2	blueswir1	static TCGv cpu_xcc;
47	dc99a3f2	blueswir1	#endif
48	1a2fb1c0	blueswir1	/* local register indexes (only used inside old micro ops) */
49	8911f501	blueswir1	static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50	1a2fb1c0	blueswir1
51	2e70f6ef	pbrook	#include "gen-icount.h"
52	2e70f6ef	pbrook
53	7a3f1944	bellard	typedef struct DisasContext {
54	0f8a249a	blueswir1	target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
55	0f8a249a	blueswir1	target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
56	72cbca10	bellard	target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
57	cf495bcf	bellard	int is_br;
58	e8af50a3	bellard	int mem_idx;
59	a80dde08	bellard	int fpu_enabled;
60	2cade6a3	blueswir1	int address_mask_32bit;
61	cf495bcf	bellard	struct TranslationBlock *tb;
62	5578ceab	blueswir1	sparc_def_t *def;
63	7a3f1944	bellard	} DisasContext;
64	7a3f1944	bellard
65	3475187d	bellard	// This function uses non-native bit order
66	7a3f1944	bellard	#define GET_FIELD(X, FROM, TO) \
67	7a3f1944	bellard	((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
68	7a3f1944	bellard
69	3475187d	bellard	// This function uses the order in the manuals, i.e. bit 0 is 2^0
70	3475187d	bellard	#define GET_FIELD_SP(X, FROM, TO) \
71	3475187d	bellard	GET_FIELD(X, 31 - (TO), 31 - (FROM))
72	3475187d	bellard
73	3475187d	bellard	#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
74	46d38ba8	blueswir1	#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
75	3475187d	bellard
76	3475187d	bellard	#ifdef TARGET_SPARC64
77	19f329ad	blueswir1	#define FFPREG(r) (r)
78	0387d928	blueswir1	#define DFPREG(r) (((r & 1) << 5) \| (r & 0x1e))
79	1f587329	blueswir1	#define QFPREG(r) (((r & 1) << 5) \| (r & 0x1c))
80	3475187d	bellard	#else
81	19f329ad	blueswir1	#define FFPREG(r) (r)
82	c185970a	blueswir1	#define DFPREG(r) (r & 0x1e)
83	1f587329	blueswir1	#define QFPREG(r) (r & 0x1c)
84	3475187d	bellard	#endif
85	3475187d	bellard
86	3475187d	bellard	static int sign_extend(int x, int len)
87	3475187d	bellard	{
88	3475187d	bellard	len = 32 - len;
89	3475187d	bellard	return (x << len) >> len;
90	3475187d	bellard	}
91	3475187d	bellard
92	7a3f1944	bellard	#define IS_IMM (insn & (1<<13))
93	7a3f1944	bellard
94	ff07ec83	blueswir1	/* floating point registers moves */
95	ff07ec83	blueswir1	static void gen_op_load_fpr_FT0(unsigned int src)
96	ff07ec83	blueswir1	{
97	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
98	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
99	3475187d	bellard	}
100	ff07ec83	blueswir1
101	ff07ec83	blueswir1	static void gen_op_load_fpr_FT1(unsigned int src)
102	ff07ec83	blueswir1	{
103	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
105	e8af50a3	bellard	}
106	e8af50a3	bellard
107	ff07ec83	blueswir1	static void gen_op_store_FT0_fpr(unsigned int dst)
108	ff07ec83	blueswir1	{
109	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
110	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
111	ff07ec83	blueswir1	}
112	ff07ec83	blueswir1
113	ff07ec83	blueswir1	static void gen_op_load_fpr_DT0(unsigned int src)
114	ff07ec83	blueswir1	{
115	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
116	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
117	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
118	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
119	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
120	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
121	ff07ec83	blueswir1	}
122	ff07ec83	blueswir1
123	ff07ec83	blueswir1	static void gen_op_load_fpr_DT1(unsigned int src)
124	ff07ec83	blueswir1	{
125	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
126	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
128	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
129	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
130	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
131	ff07ec83	blueswir1	}
132	ff07ec83	blueswir1
133	ff07ec83	blueswir1	static void gen_op_store_DT0_fpr(unsigned int dst)
134	ff07ec83	blueswir1	{
135	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136	77f193da	blueswir1	offsetof(CPU_DoubleU, l.upper));
137	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
138	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
139	77f193da	blueswir1	offsetof(CPU_DoubleU, l.lower));
140	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
141	ff07ec83	blueswir1	}
142	ff07ec83	blueswir1
143	ff07ec83	blueswir1	static void gen_op_load_fpr_QT0(unsigned int src)
144	ff07ec83	blueswir1	{
145	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
146	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
148	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
151	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
152	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
154	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
155	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
156	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
157	ff07ec83	blueswir1	}
158	ff07ec83	blueswir1
159	ff07ec83	blueswir1	static void gen_op_load_fpr_QT1(unsigned int src)
160	ff07ec83	blueswir1	{
161	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
162	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
163	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
164	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
165	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
167	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
170	8911f501	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
171	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
172	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
173	ff07ec83	blueswir1	}
174	ff07ec83	blueswir1
175	ff07ec83	blueswir1	static void gen_op_store_QT0_fpr(unsigned int dst)
176	ff07ec83	blueswir1	{
177	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178	77f193da	blueswir1	offsetof(CPU_QuadU, l.upmost));
179	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
180	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181	77f193da	blueswir1	offsetof(CPU_QuadU, l.upper));
182	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
183	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184	77f193da	blueswir1	offsetof(CPU_QuadU, l.lower));
185	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
186	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
187	77f193da	blueswir1	offsetof(CPU_QuadU, l.lowest));
188	8911f501	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
189	ff07ec83	blueswir1	}
190	1f587329	blueswir1
191	81ad8ba2	blueswir1	/* moves */
192	81ad8ba2	blueswir1	#ifdef CONFIG_USER_ONLY
193	3475187d	bellard	#define supervisor(dc) 0
194	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
195	e9ebed4d	blueswir1	#define hypervisor(dc) 0
196	81ad8ba2	blueswir1	#endif
197	3475187d	bellard	#else
198	6f27aba6	blueswir1	#define supervisor(dc) (dc->mem_idx >= 1)
199	81ad8ba2	blueswir1	#ifdef TARGET_SPARC64
200	81ad8ba2	blueswir1	#define hypervisor(dc) (dc->mem_idx == 2)
201	6f27aba6	blueswir1	#else
202	3475187d	bellard	#endif
203	81ad8ba2	blueswir1	#endif
204	81ad8ba2	blueswir1
205	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
206	2cade6a3	blueswir1	#ifndef TARGET_ABI32
207	2cade6a3	blueswir1	#define AM_CHECK(dc) ((dc)->address_mask_32bit)
208	1a2fb1c0	blueswir1	#else
209	2cade6a3	blueswir1	#define AM_CHECK(dc) (1)
210	2cade6a3	blueswir1	#endif
211	1a2fb1c0	blueswir1	#endif
212	3391c818	blueswir1
213	2cade6a3	blueswir1	static inline void gen_address_mask(DisasContext *dc, TCGv addr)
214	2cade6a3	blueswir1	{
215	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
216	2cade6a3	blueswir1	if (AM_CHECK(dc))
217	2cade6a3	blueswir1	tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
218	2cade6a3	blueswir1	#endif
219	2cade6a3	blueswir1	}
220	2cade6a3	blueswir1
221	1a2fb1c0	blueswir1	static inline void gen_movl_reg_TN(int reg, TCGv tn)
222	81ad8ba2	blueswir1	{
223	1a2fb1c0	blueswir1	if (reg == 0)
224	1a2fb1c0	blueswir1	tcg_gen_movi_tl(tn, 0);
225	1a2fb1c0	blueswir1	else if (reg < 8)
226	f5069b26	blueswir1	tcg_gen_mov_tl(tn, cpu_gregs[reg]);
227	1a2fb1c0	blueswir1	else {
228	1a2fb1c0	blueswir1	tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
229	81ad8ba2	blueswir1	}
230	81ad8ba2	blueswir1	}
231	81ad8ba2	blueswir1
232	1a2fb1c0	blueswir1	static inline void gen_movl_TN_reg(int reg, TCGv tn)
233	81ad8ba2	blueswir1	{
234	1a2fb1c0	blueswir1	if (reg == 0)
235	1a2fb1c0	blueswir1	return;
236	1a2fb1c0	blueswir1	else if (reg < 8)
237	f5069b26	blueswir1	tcg_gen_mov_tl(cpu_gregs[reg], tn);
238	1a2fb1c0	blueswir1	else {
239	1a2fb1c0	blueswir1	tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
240	81ad8ba2	blueswir1	}
241	81ad8ba2	blueswir1	}
242	81ad8ba2	blueswir1
243	5fafdf24	ths	static inline void gen_goto_tb(DisasContext *s, int tb_num,
244	6e256c93	bellard	target_ulong pc, target_ulong npc)
245	6e256c93	bellard	{
246	6e256c93	bellard	TranslationBlock *tb;
247	6e256c93	bellard
248	6e256c93	bellard	tb = s->tb;
249	6e256c93	bellard	if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
250	6e256c93	bellard	(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
251	6e256c93	bellard	/* jump to same page: we can use a direct jump */
252	57fec1fe	bellard	tcg_gen_goto_tb(tb_num);
253	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
254	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
255	57fec1fe	bellard	tcg_gen_exit_tb((long)tb + tb_num);
256	6e256c93	bellard	} else {
257	6e256c93	bellard	/* jump to another page: currently not optimized */
258	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, pc);
259	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc);
260	57fec1fe	bellard	tcg_gen_exit_tb(0);
261	6e256c93	bellard	}
262	6e256c93	bellard	}
263	6e256c93	bellard
264	19f329ad	blueswir1	// XXX suboptimal
265	19f329ad	blueswir1	static inline void gen_mov_reg_N(TCGv reg, TCGv src)
266	19f329ad	blueswir1	{
267	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
268	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
269	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
270	19f329ad	blueswir1	}
271	19f329ad	blueswir1
272	19f329ad	blueswir1	static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
273	19f329ad	blueswir1	{
274	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
275	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
276	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
277	19f329ad	blueswir1	}
278	19f329ad	blueswir1
279	19f329ad	blueswir1	static inline void gen_mov_reg_V(TCGv reg, TCGv src)
280	19f329ad	blueswir1	{
281	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
282	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
283	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
284	19f329ad	blueswir1	}
285	19f329ad	blueswir1
286	19f329ad	blueswir1	static inline void gen_mov_reg_C(TCGv reg, TCGv src)
287	19f329ad	blueswir1	{
288	8911f501	blueswir1	tcg_gen_extu_i32_tl(reg, src);
289	4b8b8b76	blueswir1	tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
290	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
291	19f329ad	blueswir1	}
292	19f329ad	blueswir1
293	ce5b3c3d	blueswir1	static inline void gen_cc_clear_icc(void)
294	dc99a3f2	blueswir1	{
295	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_psr, 0);
296	ce5b3c3d	blueswir1	}
297	ce5b3c3d	blueswir1
298	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
299	ce5b3c3d	blueswir1	static inline void gen_cc_clear_xcc(void)
300	ce5b3c3d	blueswir1	{
301	dc99a3f2	blueswir1	tcg_gen_movi_i32(cpu_xcc, 0);
302	dc99a3f2	blueswir1	}
303	ce5b3c3d	blueswir1	#endif
304	dc99a3f2	blueswir1
305	dc99a3f2	blueswir1	/* old op:
306	dc99a3f2	blueswir1	if (!T0)
307	dc99a3f2	blueswir1	env->psr \|= PSR_ZERO;
308	dc99a3f2	blueswir1	if ((int32_t) T0 < 0)
309	dc99a3f2	blueswir1	env->psr \|= PSR_NEG;
310	dc99a3f2	blueswir1	*/
311	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_icc(TCGv dst)
312	dc99a3f2	blueswir1	{
313	8911f501	blueswir1	TCGv r_temp;
314	dc99a3f2	blueswir1	int l1, l2;
315	dc99a3f2	blueswir1
316	dc99a3f2	blueswir1	l1 = gen_new_label();
317	dc99a3f2	blueswir1	l2 = gen_new_label();
318	8911f501	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
319	8911f501	blueswir1	tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
320	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
321	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
322	dc99a3f2	blueswir1	gen_set_label(l1);
323	bdf46ea2	blueswir1	tcg_gen_ext_i32_tl(r_temp, dst);
324	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
325	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
326	dc99a3f2	blueswir1	gen_set_label(l2);
327	2ea815ca	blueswir1	tcg_temp_free(r_temp);
328	ce5b3c3d	blueswir1	}
329	ce5b3c3d	blueswir1
330	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
331	ce5b3c3d	blueswir1	static inline void gen_cc_NZ_xcc(TCGv dst)
332	ce5b3c3d	blueswir1	{
333	ce5b3c3d	blueswir1	int l1, l2;
334	ce5b3c3d	blueswir1
335	ce5b3c3d	blueswir1	l1 = gen_new_label();
336	ce5b3c3d	blueswir1	l2 = gen_new_label();
337	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
338	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339	ce5b3c3d	blueswir1	gen_set_label(l1);
340	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
341	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342	ce5b3c3d	blueswir1	gen_set_label(l2);
343	dc99a3f2	blueswir1	}
344	ce5b3c3d	blueswir1	#endif
345	dc99a3f2	blueswir1
346	dc99a3f2	blueswir1	/* old op:
347	dc99a3f2	blueswir1	if (T0 < src1)
348	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
349	dc99a3f2	blueswir1	*/
350	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
351	dc99a3f2	blueswir1	{
352	2ae72bce	blueswir1	TCGv r_temp1, r_temp2;
353	dc99a3f2	blueswir1	int l1;
354	dc99a3f2	blueswir1
355	dc99a3f2	blueswir1	l1 = gen_new_label();
356	2ae72bce	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
357	2ae72bce	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
358	2ae72bce	blueswir1	tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
359	2ae72bce	blueswir1	tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
360	2ae72bce	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
361	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
362	dc99a3f2	blueswir1	gen_set_label(l1);
363	2ae72bce	blueswir1	tcg_temp_free(r_temp1);
364	2ae72bce	blueswir1	tcg_temp_free(r_temp2);
365	ce5b3c3d	blueswir1	}
366	ce5b3c3d	blueswir1
367	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
368	ce5b3c3d	blueswir1	static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
369	ce5b3c3d	blueswir1	{
370	ce5b3c3d	blueswir1	int l1;
371	dc99a3f2	blueswir1
372	ce5b3c3d	blueswir1	l1 = gen_new_label();
373	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
374	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
375	ce5b3c3d	blueswir1	gen_set_label(l1);
376	dc99a3f2	blueswir1	}
377	ce5b3c3d	blueswir1	#endif
378	dc99a3f2	blueswir1
379	dc99a3f2	blueswir1	/* old op:
380	dc99a3f2	blueswir1	if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
381	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
382	dc99a3f2	blueswir1	*/
383	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
384	dc99a3f2	blueswir1	{
385	0425bee5	blueswir1	TCGv r_temp;
386	dc99a3f2	blueswir1
387	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
388	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
389	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
390	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
391	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
392	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
393	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
394	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
395	2ea815ca	blueswir1	tcg_temp_free(r_temp);
396	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
397	ce5b3c3d	blueswir1	}
398	ce5b3c3d	blueswir1
399	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
400	ce5b3c3d	blueswir1	static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
401	ce5b3c3d	blueswir1	{
402	ce5b3c3d	blueswir1	TCGv r_temp;
403	ce5b3c3d	blueswir1
404	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
405	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
406	ce5b3c3d	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
407	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
408	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
409	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
410	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
411	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
412	2ea815ca	blueswir1	tcg_temp_free(r_temp);
413	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
414	dc99a3f2	blueswir1	}
415	ce5b3c3d	blueswir1	#endif
416	dc99a3f2	blueswir1
417	dc99a3f2	blueswir1	static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
418	dc99a3f2	blueswir1	{
419	2ea815ca	blueswir1	TCGv r_temp, r_const;
420	dc99a3f2	blueswir1	int l1;
421	dc99a3f2	blueswir1
422	dc99a3f2	blueswir1	l1 = gen_new_label();
423	dc99a3f2	blueswir1
424	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
425	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
426	dc99a3f2	blueswir1	tcg_gen_xori_tl(r_temp, r_temp, -1);
427	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
428	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
429	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
430	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
431	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
432	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
433	2ea815ca	blueswir1	tcg_temp_free(r_const);
434	dc99a3f2	blueswir1	gen_set_label(l1);
435	2ea815ca	blueswir1	tcg_temp_free(r_temp);
436	dc99a3f2	blueswir1	}
437	dc99a3f2	blueswir1
438	dc99a3f2	blueswir1	static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
439	dc99a3f2	blueswir1	{
440	dc99a3f2	blueswir1	int l1;
441	dc99a3f2	blueswir1
442	dc99a3f2	blueswir1	l1 = gen_new_label();
443	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
444	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
445	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
446	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
447	dc99a3f2	blueswir1	gen_set_label(l1);
448	dc99a3f2	blueswir1	}
449	dc99a3f2	blueswir1
450	dc99a3f2	blueswir1	static inline void gen_tag_tv(TCGv src1, TCGv src2)
451	dc99a3f2	blueswir1	{
452	dc99a3f2	blueswir1	int l1;
453	2ea815ca	blueswir1	TCGv r_const;
454	dc99a3f2	blueswir1
455	dc99a3f2	blueswir1	l1 = gen_new_label();
456	0425bee5	blueswir1	tcg_gen_or_tl(cpu_tmp0, src1, src2);
457	0425bee5	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
458	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
459	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
460	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
461	2ea815ca	blueswir1	tcg_temp_free(r_const);
462	dc99a3f2	blueswir1	gen_set_label(l1);
463	dc99a3f2	blueswir1	}
464	dc99a3f2	blueswir1
465	4af984a7	blueswir1	static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
466	dc99a3f2	blueswir1	{
467	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
468	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
469	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
470	ce5b3c3d	blueswir1	gen_cc_clear_icc();
471	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
472	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
473	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
474	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
475	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
476	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
477	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
478	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
479	ce5b3c3d	blueswir1	#endif
480	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
481	dc99a3f2	blueswir1	}
482	dc99a3f2	blueswir1
483	4af984a7	blueswir1	static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
484	dc99a3f2	blueswir1	{
485	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
486	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
487	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
488	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
489	ce5b3c3d	blueswir1	gen_cc_clear_icc();
490	5c6a0628	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
491	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
492	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
493	5c6a0628	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
494	ce5b3c3d	blueswir1	#endif
495	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
496	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
497	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
498	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
499	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
500	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
501	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
502	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
503	ce5b3c3d	blueswir1	#endif
504	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
505	dc99a3f2	blueswir1	}
506	dc99a3f2	blueswir1
507	4af984a7	blueswir1	static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
508	dc99a3f2	blueswir1	{
509	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
510	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
511	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
512	ce5b3c3d	blueswir1	gen_cc_clear_icc();
513	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
514	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
515	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
516	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
517	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
518	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
519	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
520	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
521	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
522	ce5b3c3d	blueswir1	#endif
523	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
524	dc99a3f2	blueswir1	}
525	dc99a3f2	blueswir1
526	4af984a7	blueswir1	static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
527	dc99a3f2	blueswir1	{
528	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
529	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
530	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
531	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
532	5c6a0628	blueswir1	gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
533	ce5b3c3d	blueswir1	gen_cc_clear_icc();
534	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
535	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
536	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
537	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
538	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
539	ba28189b	blueswir1	gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
540	ba28189b	blueswir1	gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
541	ce5b3c3d	blueswir1	#endif
542	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
543	dc99a3f2	blueswir1	}
544	dc99a3f2	blueswir1
545	dc99a3f2	blueswir1	/* old op:
546	dc99a3f2	blueswir1	if (src1 < T1)
547	dc99a3f2	blueswir1	env->psr \|= PSR_CARRY;
548	dc99a3f2	blueswir1	*/
549	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
550	dc99a3f2	blueswir1	{
551	8911f501	blueswir1	TCGv r_temp1, r_temp2;
552	dc99a3f2	blueswir1	int l1;
553	dc99a3f2	blueswir1
554	dc99a3f2	blueswir1	l1 = gen_new_label();
555	8911f501	blueswir1	r_temp1 = tcg_temp_new(TCG_TYPE_TL);
556	8911f501	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_TL);
557	8911f501	blueswir1	tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
558	8911f501	blueswir1	tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
559	8911f501	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
560	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
561	dc99a3f2	blueswir1	gen_set_label(l1);
562	2ea815ca	blueswir1	tcg_temp_free(r_temp1);
563	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
564	ce5b3c3d	blueswir1	}
565	ce5b3c3d	blueswir1
566	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
567	ce5b3c3d	blueswir1	static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
568	ce5b3c3d	blueswir1	{
569	ce5b3c3d	blueswir1	int l1;
570	dc99a3f2	blueswir1
571	ce5b3c3d	blueswir1	l1 = gen_new_label();
572	ce5b3c3d	blueswir1	tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
573	ce5b3c3d	blueswir1	tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
574	ce5b3c3d	blueswir1	gen_set_label(l1);
575	dc99a3f2	blueswir1	}
576	ce5b3c3d	blueswir1	#endif
577	dc99a3f2	blueswir1
578	dc99a3f2	blueswir1	/* old op:
579	dc99a3f2	blueswir1	if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
580	dc99a3f2	blueswir1	env->psr \|= PSR_OVF;
581	dc99a3f2	blueswir1	*/
582	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
583	dc99a3f2	blueswir1	{
584	0425bee5	blueswir1	TCGv r_temp;
585	dc99a3f2	blueswir1
586	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
587	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
588	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
591	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
592	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593	653ccb80	blueswir1	tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
594	2ea815ca	blueswir1	tcg_temp_free(r_temp);
595	ce5b3c3d	blueswir1	}
596	ce5b3c3d	blueswir1
597	dc99a3f2	blueswir1	#ifdef TARGET_SPARC64
598	ce5b3c3d	blueswir1	static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
599	ce5b3c3d	blueswir1	{
600	ce5b3c3d	blueswir1	TCGv r_temp;
601	ce5b3c3d	blueswir1
602	ce5b3c3d	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
603	ce5b3c3d	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
604	ce5b3c3d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
605	ce5b3c3d	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
606	ce5b3c3d	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
607	653ccb80	blueswir1	tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
608	653ccb80	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
609	653ccb80	blueswir1	tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
610	2ea815ca	blueswir1	tcg_temp_free(r_temp);
611	dc99a3f2	blueswir1	}
612	ce5b3c3d	blueswir1	#endif
613	dc99a3f2	blueswir1
614	dc99a3f2	blueswir1	static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
615	dc99a3f2	blueswir1	{
616	2ea815ca	blueswir1	TCGv r_temp, r_const;
617	dc99a3f2	blueswir1	int l1;
618	dc99a3f2	blueswir1
619	dc99a3f2	blueswir1	l1 = gen_new_label();
620	dc99a3f2	blueswir1
621	dc99a3f2	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
622	dc99a3f2	blueswir1	tcg_gen_xor_tl(r_temp, src1, src2);
623	0425bee5	blueswir1	tcg_gen_xor_tl(cpu_tmp0, src1, dst);
624	0425bee5	blueswir1	tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
625	dd5e6304	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
626	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
627	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_TOVF);
628	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
629	2ea815ca	blueswir1	tcg_temp_free(r_const);
630	dc99a3f2	blueswir1	gen_set_label(l1);
631	2ea815ca	blueswir1	tcg_temp_free(r_temp);
632	dc99a3f2	blueswir1	}
633	dc99a3f2	blueswir1
634	4af984a7	blueswir1	static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
635	dc99a3f2	blueswir1	{
636	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
637	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
638	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
639	ce5b3c3d	blueswir1	gen_cc_clear_icc();
640	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
641	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
642	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
643	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
644	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
645	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
646	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
647	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
648	ce5b3c3d	blueswir1	#endif
649	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
650	dc99a3f2	blueswir1	}
651	dc99a3f2	blueswir1
652	4af984a7	blueswir1	static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
653	dc99a3f2	blueswir1	{
654	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
655	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
656	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
657	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
658	ce5b3c3d	blueswir1	gen_cc_clear_icc();
659	5c6a0628	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
660	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
661	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
662	5c6a0628	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
663	ce5b3c3d	blueswir1	#endif
664	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
665	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
666	ba28189b	blueswir1	gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
667	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
668	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
669	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
670	ba28189b	blueswir1	gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
671	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
672	ce5b3c3d	blueswir1	#endif
673	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
674	dc99a3f2	blueswir1	}
675	dc99a3f2	blueswir1
676	4af984a7	blueswir1	static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
677	dc99a3f2	blueswir1	{
678	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
679	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
680	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
681	ce5b3c3d	blueswir1	gen_cc_clear_icc();
682	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
683	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
684	ba28189b	blueswir1	gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
685	6f551262	blueswir1	gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
686	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
687	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
688	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
689	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
690	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
691	ce5b3c3d	blueswir1	#endif
692	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
693	dc99a3f2	blueswir1	}
694	dc99a3f2	blueswir1
695	4af984a7	blueswir1	static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
696	dc99a3f2	blueswir1	{
697	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
698	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
699	6f551262	blueswir1	gen_tag_tv(cpu_cc_src, cpu_cc_src2);
700	5c6a0628	blueswir1	tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
701	5c6a0628	blueswir1	gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
702	ce5b3c3d	blueswir1	gen_cc_clear_icc();
703	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
704	6f551262	blueswir1	gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
705	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
706	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
707	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
708	6f551262	blueswir1	gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
709	ba28189b	blueswir1	gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
710	ce5b3c3d	blueswir1	#endif
711	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
712	dc99a3f2	blueswir1	}
713	dc99a3f2	blueswir1
714	4af984a7	blueswir1	static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
715	d9bdab86	blueswir1	{
716	105a1f04	blueswir1	TCGv r_temp;
717	6f551262	blueswir1	int l1;
718	d9bdab86	blueswir1
719	d9bdab86	blueswir1	l1 = gen_new_label();
720	d9bdab86	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
721	d9bdab86	blueswir1
722	d9bdab86	blueswir1	/* old op:
723	d9bdab86	blueswir1	if (!(env->y & 1))
724	d9bdab86	blueswir1	T1 = 0;
725	d9bdab86	blueswir1	*/
726	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
727	105a1f04	blueswir1	tcg_gen_ld_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
728	105a1f04	blueswir1	tcg_gen_andi_tl(r_temp, r_temp, 0x1);
729	4af984a7	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
730	105a1f04	blueswir1	tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
731	d9bdab86	blueswir1	tcg_gen_movi_tl(cpu_cc_src2, 0);
732	6f551262	blueswir1	gen_set_label(l1);
733	d9bdab86	blueswir1
734	d9bdab86	blueswir1	// b2 = T0 & 1;
735	d9bdab86	blueswir1	// env->y = (b2 << 31) \| (env->y >> 1);
736	105a1f04	blueswir1	tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
737	105a1f04	blueswir1	tcg_gen_shli_tl(r_temp, r_temp, 31);
738	105a1f04	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
739	105a1f04	blueswir1	tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 1);
740	105a1f04	blueswir1	tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
741	105a1f04	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
742	d9bdab86	blueswir1
743	d9bdab86	blueswir1	// b1 = N ^ V;
744	d9bdab86	blueswir1	gen_mov_reg_N(cpu_tmp0, cpu_psr);
745	d9bdab86	blueswir1	gen_mov_reg_V(r_temp, cpu_psr);
746	d9bdab86	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
747	2ea815ca	blueswir1	tcg_temp_free(r_temp);
748	d9bdab86	blueswir1
749	d9bdab86	blueswir1	// T0 = (b1 << 31) \| (T0 >> 1);
750	d9bdab86	blueswir1	// src1 = T0;
751	d9bdab86	blueswir1	tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
752	6f551262	blueswir1	tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
753	d9bdab86	blueswir1	tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
754	d9bdab86	blueswir1
755	d9bdab86	blueswir1	/* do addition and update flags */
756	5c6a0628	blueswir1	tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
757	d9bdab86	blueswir1
758	ce5b3c3d	blueswir1	gen_cc_clear_icc();
759	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
760	ba28189b	blueswir1	gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
761	ba28189b	blueswir1	gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
762	5c6a0628	blueswir1	tcg_gen_mov_tl(dst, cpu_cc_dst);
763	d9bdab86	blueswir1	}
764	d9bdab86	blueswir1
765	4af984a7	blueswir1	static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
766	8879d139	blueswir1	{
767	8879d139	blueswir1	TCGv r_temp, r_temp2;
768	8879d139	blueswir1
769	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
770	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
771	8879d139	blueswir1
772	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp, src2);
773	4af984a7	blueswir1	tcg_gen_extu_tl_i64(r_temp2, src1);
774	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
775	8879d139	blueswir1
776	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
777	105a1f04	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
778	2ea815ca	blueswir1	tcg_temp_free(r_temp);
779	105a1f04	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
780	105a1f04	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
781	8879d139	blueswir1	#ifdef TARGET_SPARC64
782	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
783	8879d139	blueswir1	#else
784	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
785	8879d139	blueswir1	#endif
786	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
787	8879d139	blueswir1	}
788	8879d139	blueswir1
789	4af984a7	blueswir1	static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
790	8879d139	blueswir1	{
791	8879d139	blueswir1	TCGv r_temp, r_temp2;
792	8879d139	blueswir1
793	8879d139	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_I64);
794	8879d139	blueswir1	r_temp2 = tcg_temp_new(TCG_TYPE_I64);
795	8879d139	blueswir1
796	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp, src2);
797	4af984a7	blueswir1	tcg_gen_ext_tl_i64(r_temp2, src1);
798	8879d139	blueswir1	tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
799	8879d139	blueswir1
800	8879d139	blueswir1	tcg_gen_shri_i64(r_temp, r_temp2, 32);
801	105a1f04	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
802	2ea815ca	blueswir1	tcg_temp_free(r_temp);
803	105a1f04	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
804	105a1f04	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y));
805	8879d139	blueswir1	#ifdef TARGET_SPARC64
806	4af984a7	blueswir1	tcg_gen_mov_i64(dst, r_temp2);
807	8879d139	blueswir1	#else
808	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, r_temp2);
809	8879d139	blueswir1	#endif
810	2ea815ca	blueswir1	tcg_temp_free(r_temp2);
811	8879d139	blueswir1	}
812	8879d139	blueswir1
813	1a7b60e7	blueswir1	#ifdef TARGET_SPARC64
814	8911f501	blueswir1	static inline void gen_trap_ifdivzero_tl(TCGv divisor)
815	1a7b60e7	blueswir1	{
816	2ea815ca	blueswir1	TCGv r_const;
817	1a7b60e7	blueswir1	int l1;
818	1a7b60e7	blueswir1
819	1a7b60e7	blueswir1	l1 = gen_new_label();
820	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
821	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_DIV_ZERO);
822	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
823	2ea815ca	blueswir1	tcg_temp_free(r_const);
824	1a7b60e7	blueswir1	gen_set_label(l1);
825	1a7b60e7	blueswir1	}
826	1a7b60e7	blueswir1
827	4af984a7	blueswir1	static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
828	1a7b60e7	blueswir1	{
829	1a7b60e7	blueswir1	int l1, l2;
830	1a7b60e7	blueswir1
831	1a7b60e7	blueswir1	l1 = gen_new_label();
832	1a7b60e7	blueswir1	l2 = gen_new_label();
833	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src, src1);
834	6f551262	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, src2);
835	5c6a0628	blueswir1	gen_trap_ifdivzero_tl(cpu_cc_src2);
836	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
837	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
838	4af984a7	blueswir1	tcg_gen_movi_i64(dst, INT64_MIN);
839	06b3e1b3	blueswir1	tcg_gen_br(l2);
840	1a7b60e7	blueswir1	gen_set_label(l1);
841	6f551262	blueswir1	tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
842	1a7b60e7	blueswir1	gen_set_label(l2);
843	1a7b60e7	blueswir1	}
844	1a7b60e7	blueswir1	#endif
845	1a7b60e7	blueswir1
846	4af984a7	blueswir1	static inline void gen_op_div_cc(TCGv dst)
847	dc99a3f2	blueswir1	{
848	dc99a3f2	blueswir1	int l1;
849	dc99a3f2	blueswir1
850	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
851	ce5b3c3d	blueswir1	gen_cc_clear_icc();
852	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
853	dc99a3f2	blueswir1	l1 = gen_new_label();
854	5c6a0628	blueswir1	tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
855	dc99a3f2	blueswir1	tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
856	dc99a3f2	blueswir1	gen_set_label(l1);
857	dc99a3f2	blueswir1	}
858	dc99a3f2	blueswir1
859	4af984a7	blueswir1	static inline void gen_op_logic_cc(TCGv dst)
860	dc99a3f2	blueswir1	{
861	ba28189b	blueswir1	tcg_gen_mov_tl(cpu_cc_dst, dst);
862	ba28189b	blueswir1
863	ce5b3c3d	blueswir1	gen_cc_clear_icc();
864	ba28189b	blueswir1	gen_cc_NZ_icc(cpu_cc_dst);
865	ce5b3c3d	blueswir1	#ifdef TARGET_SPARC64
866	ce5b3c3d	blueswir1	gen_cc_clear_xcc();
867	ba28189b	blueswir1	gen_cc_NZ_xcc(cpu_cc_dst);
868	ce5b3c3d	blueswir1	#endif
869	dc99a3f2	blueswir1	}
870	dc99a3f2	blueswir1
871	19f329ad	blueswir1	// 1
872	19f329ad	blueswir1	static inline void gen_op_eval_ba(TCGv dst)
873	19f329ad	blueswir1	{
874	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 1);
875	19f329ad	blueswir1	}
876	19f329ad	blueswir1
877	19f329ad	blueswir1	// Z
878	19f329ad	blueswir1	static inline void gen_op_eval_be(TCGv dst, TCGv src)
879	19f329ad	blueswir1	{
880	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
881	19f329ad	blueswir1	}
882	19f329ad	blueswir1
883	19f329ad	blueswir1	// Z \| (N ^ V)
884	19f329ad	blueswir1	static inline void gen_op_eval_ble(TCGv dst, TCGv src)
885	19f329ad	blueswir1	{
886	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
887	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
888	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
889	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
890	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
891	19f329ad	blueswir1	}
892	19f329ad	blueswir1
893	19f329ad	blueswir1	// N ^ V
894	19f329ad	blueswir1	static inline void gen_op_eval_bl(TCGv dst, TCGv src)
895	19f329ad	blueswir1	{
896	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
897	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
898	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
899	19f329ad	blueswir1	}
900	19f329ad	blueswir1
901	19f329ad	blueswir1	// C \| Z
902	19f329ad	blueswir1	static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
903	19f329ad	blueswir1	{
904	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
905	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
906	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
907	19f329ad	blueswir1	}
908	19f329ad	blueswir1
909	19f329ad	blueswir1	// C
910	19f329ad	blueswir1	static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
911	19f329ad	blueswir1	{
912	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
913	19f329ad	blueswir1	}
914	19f329ad	blueswir1
915	19f329ad	blueswir1	// V
916	19f329ad	blueswir1	static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
917	19f329ad	blueswir1	{
918	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
919	19f329ad	blueswir1	}
920	19f329ad	blueswir1
921	19f329ad	blueswir1	// 0
922	19f329ad	blueswir1	static inline void gen_op_eval_bn(TCGv dst)
923	19f329ad	blueswir1	{
924	19f329ad	blueswir1	tcg_gen_movi_tl(dst, 0);
925	19f329ad	blueswir1	}
926	19f329ad	blueswir1
927	19f329ad	blueswir1	// N
928	19f329ad	blueswir1	static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
929	19f329ad	blueswir1	{
930	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
931	19f329ad	blueswir1	}
932	19f329ad	blueswir1
933	19f329ad	blueswir1	// !Z
934	19f329ad	blueswir1	static inline void gen_op_eval_bne(TCGv dst, TCGv src)
935	19f329ad	blueswir1	{
936	19f329ad	blueswir1	gen_mov_reg_Z(dst, src);
937	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
938	19f329ad	blueswir1	}
939	19f329ad	blueswir1
940	19f329ad	blueswir1	// !(Z \| (N ^ V))
941	19f329ad	blueswir1	static inline void gen_op_eval_bg(TCGv dst, TCGv src)
942	19f329ad	blueswir1	{
943	0425bee5	blueswir1	gen_mov_reg_N(cpu_tmp0, src);
944	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
945	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
946	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
947	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
948	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
949	19f329ad	blueswir1	}
950	19f329ad	blueswir1
951	19f329ad	blueswir1	// !(N ^ V)
952	19f329ad	blueswir1	static inline void gen_op_eval_bge(TCGv dst, TCGv src)
953	19f329ad	blueswir1	{
954	0425bee5	blueswir1	gen_mov_reg_V(cpu_tmp0, src);
955	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
956	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
957	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
958	19f329ad	blueswir1	}
959	19f329ad	blueswir1
960	19f329ad	blueswir1	// !(C \| Z)
961	19f329ad	blueswir1	static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
962	19f329ad	blueswir1	{
963	0425bee5	blueswir1	gen_mov_reg_Z(cpu_tmp0, src);
964	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
965	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
966	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
967	19f329ad	blueswir1	}
968	19f329ad	blueswir1
969	19f329ad	blueswir1	// !C
970	19f329ad	blueswir1	static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
971	19f329ad	blueswir1	{
972	19f329ad	blueswir1	gen_mov_reg_C(dst, src);
973	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
974	19f329ad	blueswir1	}
975	19f329ad	blueswir1
976	19f329ad	blueswir1	// !N
977	19f329ad	blueswir1	static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
978	19f329ad	blueswir1	{
979	19f329ad	blueswir1	gen_mov_reg_N(dst, src);
980	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
981	19f329ad	blueswir1	}
982	19f329ad	blueswir1
983	19f329ad	blueswir1	// !V
984	19f329ad	blueswir1	static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
985	19f329ad	blueswir1	{
986	19f329ad	blueswir1	gen_mov_reg_V(dst, src);
987	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
988	19f329ad	blueswir1	}
989	19f329ad	blueswir1
990	19f329ad	blueswir1	/*
991	19f329ad	blueswir1	FPSR bit field FCC1 \| FCC0:
992	19f329ad	blueswir1	0 =
993	19f329ad	blueswir1	1 <
994	19f329ad	blueswir1	2 >
995	19f329ad	blueswir1	3 unordered
996	19f329ad	blueswir1	*/
997	19f329ad	blueswir1	static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
998	19f329ad	blueswir1	unsigned int fcc_offset)
999	19f329ad	blueswir1	{
1000	ba6a9d8c	blueswir1	tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
1001	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
1002	19f329ad	blueswir1	}
1003	19f329ad	blueswir1
1004	19f329ad	blueswir1	static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1005	19f329ad	blueswir1	unsigned int fcc_offset)
1006	19f329ad	blueswir1	{
1007	ba6a9d8c	blueswir1	tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
1008	19f329ad	blueswir1	tcg_gen_andi_tl(reg, reg, 0x1);
1009	19f329ad	blueswir1	}
1010	19f329ad	blueswir1
1011	19f329ad	blueswir1	// !0: FCC0 \| FCC1
1012	19f329ad	blueswir1	static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1013	19f329ad	blueswir1	unsigned int fcc_offset)
1014	19f329ad	blueswir1	{
1015	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1016	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1017	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1018	19f329ad	blueswir1	}
1019	19f329ad	blueswir1
1020	19f329ad	blueswir1	// 1 or 2: FCC0 ^ FCC1
1021	19f329ad	blueswir1	static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1022	19f329ad	blueswir1	unsigned int fcc_offset)
1023	19f329ad	blueswir1	{
1024	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1025	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1026	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1027	19f329ad	blueswir1	}
1028	19f329ad	blueswir1
1029	19f329ad	blueswir1	// 1 or 3: FCC0
1030	19f329ad	blueswir1	static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1031	19f329ad	blueswir1	unsigned int fcc_offset)
1032	19f329ad	blueswir1	{
1033	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1034	19f329ad	blueswir1	}
1035	19f329ad	blueswir1
1036	19f329ad	blueswir1	// 1: FCC0 & !FCC1
1037	19f329ad	blueswir1	static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1038	19f329ad	blueswir1	unsigned int fcc_offset)
1039	19f329ad	blueswir1	{
1040	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1041	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1042	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1043	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1044	19f329ad	blueswir1	}
1045	19f329ad	blueswir1
1046	19f329ad	blueswir1	// 2 or 3: FCC1
1047	19f329ad	blueswir1	static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1048	19f329ad	blueswir1	unsigned int fcc_offset)
1049	19f329ad	blueswir1	{
1050	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1051	19f329ad	blueswir1	}
1052	19f329ad	blueswir1
1053	19f329ad	blueswir1	// 2: !FCC0 & FCC1
1054	19f329ad	blueswir1	static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1055	19f329ad	blueswir1	unsigned int fcc_offset)
1056	19f329ad	blueswir1	{
1057	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1058	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1059	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1060	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1061	19f329ad	blueswir1	}
1062	19f329ad	blueswir1
1063	19f329ad	blueswir1	// 3: FCC0 & FCC1
1064	19f329ad	blueswir1	static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1065	19f329ad	blueswir1	unsigned int fcc_offset)
1066	19f329ad	blueswir1	{
1067	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1068	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1069	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1070	19f329ad	blueswir1	}
1071	19f329ad	blueswir1
1072	19f329ad	blueswir1	// 0: !(FCC0 \| FCC1)
1073	19f329ad	blueswir1	static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1074	19f329ad	blueswir1	unsigned int fcc_offset)
1075	19f329ad	blueswir1	{
1076	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1077	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1078	0425bee5	blueswir1	tcg_gen_or_tl(dst, dst, cpu_tmp0);
1079	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1080	19f329ad	blueswir1	}
1081	19f329ad	blueswir1
1082	19f329ad	blueswir1	// 0 or 3: !(FCC0 ^ FCC1)
1083	19f329ad	blueswir1	static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1084	19f329ad	blueswir1	unsigned int fcc_offset)
1085	19f329ad	blueswir1	{
1086	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1087	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1088	0425bee5	blueswir1	tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1089	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1090	19f329ad	blueswir1	}
1091	19f329ad	blueswir1
1092	19f329ad	blueswir1	// 0 or 2: !FCC0
1093	19f329ad	blueswir1	static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1094	19f329ad	blueswir1	unsigned int fcc_offset)
1095	19f329ad	blueswir1	{
1096	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1097	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1098	19f329ad	blueswir1	}
1099	19f329ad	blueswir1
1100	19f329ad	blueswir1	// !1: !(FCC0 & !FCC1)
1101	19f329ad	blueswir1	static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1102	19f329ad	blueswir1	unsigned int fcc_offset)
1103	19f329ad	blueswir1	{
1104	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1105	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1106	0425bee5	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1107	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1108	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1109	19f329ad	blueswir1	}
1110	19f329ad	blueswir1
1111	19f329ad	blueswir1	// 0 or 1: !FCC1
1112	19f329ad	blueswir1	static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1113	19f329ad	blueswir1	unsigned int fcc_offset)
1114	19f329ad	blueswir1	{
1115	19f329ad	blueswir1	gen_mov_reg_FCC1(dst, src, fcc_offset);
1116	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1117	19f329ad	blueswir1	}
1118	19f329ad	blueswir1
1119	19f329ad	blueswir1	// !2: !(!FCC0 & FCC1)
1120	19f329ad	blueswir1	static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1121	19f329ad	blueswir1	unsigned int fcc_offset)
1122	19f329ad	blueswir1	{
1123	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1124	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1125	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1126	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1127	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1128	19f329ad	blueswir1	}
1129	19f329ad	blueswir1
1130	19f329ad	blueswir1	// !3: !(FCC0 & FCC1)
1131	19f329ad	blueswir1	static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1132	19f329ad	blueswir1	unsigned int fcc_offset)
1133	19f329ad	blueswir1	{
1134	19f329ad	blueswir1	gen_mov_reg_FCC0(dst, src, fcc_offset);
1135	0425bee5	blueswir1	gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1136	0425bee5	blueswir1	tcg_gen_and_tl(dst, dst, cpu_tmp0);
1137	19f329ad	blueswir1	tcg_gen_xori_tl(dst, dst, 0x1);
1138	19f329ad	blueswir1	}
1139	19f329ad	blueswir1
1140	46525e1f	blueswir1	static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1141	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1142	83469015	bellard	{
1143	83469015	bellard	int l1;
1144	83469015	bellard
1145	83469015	bellard	l1 = gen_new_label();
1146	83469015	bellard
1147	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1148	83469015	bellard
1149	6e256c93	bellard	gen_goto_tb(dc, 0, pc1, pc1 + 4);
1150	83469015	bellard
1151	83469015	bellard	gen_set_label(l1);
1152	6e256c93	bellard	gen_goto_tb(dc, 1, pc2, pc2 + 4);
1153	83469015	bellard	}
1154	83469015	bellard
1155	46525e1f	blueswir1	static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1156	19f329ad	blueswir1	target_ulong pc2, TCGv r_cond)
1157	83469015	bellard	{
1158	83469015	bellard	int l1;
1159	83469015	bellard
1160	83469015	bellard	l1 = gen_new_label();
1161	83469015	bellard
1162	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1163	83469015	bellard
1164	6e256c93	bellard	gen_goto_tb(dc, 0, pc2, pc1);
1165	83469015	bellard
1166	83469015	bellard	gen_set_label(l1);
1167	6e256c93	bellard	gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1168	83469015	bellard	}
1169	83469015	bellard
1170	19f329ad	blueswir1	static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1171	19f329ad	blueswir1	TCGv r_cond)
1172	83469015	bellard	{
1173	83469015	bellard	int l1, l2;
1174	83469015	bellard
1175	83469015	bellard	l1 = gen_new_label();
1176	83469015	bellard	l2 = gen_new_label();
1177	19f329ad	blueswir1
1178	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1179	83469015	bellard
1180	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc1);
1181	06b3e1b3	blueswir1	tcg_gen_br(l2);
1182	83469015	bellard
1183	83469015	bellard	gen_set_label(l1);
1184	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, npc2);
1185	83469015	bellard	gen_set_label(l2);
1186	83469015	bellard	}
1187	83469015	bellard
1188	4af984a7	blueswir1	/* call this function before using the condition register as it may
1189	4af984a7	blueswir1	have been set for a jump */
1190	4af984a7	blueswir1	static inline void flush_cond(DisasContext *dc, TCGv cond)
1191	83469015	bellard	{
1192	83469015	bellard	if (dc->npc == JUMP_PC) {
1193	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1194	83469015	bellard	dc->npc = DYNAMIC_PC;
1195	83469015	bellard	}
1196	83469015	bellard	}
1197	83469015	bellard
1198	4af984a7	blueswir1	static inline void save_npc(DisasContext *dc, TCGv cond)
1199	72cbca10	bellard	{
1200	72cbca10	bellard	if (dc->npc == JUMP_PC) {
1201	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1202	72cbca10	bellard	dc->npc = DYNAMIC_PC;
1203	72cbca10	bellard	} else if (dc->npc != DYNAMIC_PC) {
1204	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_npc, dc->npc);
1205	72cbca10	bellard	}
1206	72cbca10	bellard	}
1207	72cbca10	bellard
1208	4af984a7	blueswir1	static inline void save_state(DisasContext *dc, TCGv cond)
1209	72cbca10	bellard	{
1210	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
1211	4af984a7	blueswir1	save_npc(dc, cond);
1212	72cbca10	bellard	}
1213	72cbca10	bellard
1214	4af984a7	blueswir1	static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1215	0bee699e	bellard	{
1216	0bee699e	bellard	if (dc->npc == JUMP_PC) {
1217	4af984a7	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1218	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1219	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1220	0bee699e	bellard	} else if (dc->npc == DYNAMIC_PC) {
1221	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1222	0bee699e	bellard	dc->pc = DYNAMIC_PC;
1223	0bee699e	bellard	} else {
1224	0bee699e	bellard	dc->pc = dc->npc;
1225	0bee699e	bellard	}
1226	0bee699e	bellard	}
1227	0bee699e	bellard
1228	38bc628b	blueswir1	static inline void gen_op_next_insn(void)
1229	38bc628b	blueswir1	{
1230	48d5c82b	blueswir1	tcg_gen_mov_tl(cpu_pc, cpu_npc);
1231	48d5c82b	blueswir1	tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1232	38bc628b	blueswir1	}
1233	38bc628b	blueswir1
1234	19f329ad	blueswir1	static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1235	19f329ad	blueswir1	{
1236	19f329ad	blueswir1	TCGv r_src;
1237	3475187d	bellard
1238	3475187d	bellard	#ifdef TARGET_SPARC64
1239	19f329ad	blueswir1	if (cc)
1240	dc99a3f2	blueswir1	r_src = cpu_xcc;
1241	19f329ad	blueswir1	else
1242	dc99a3f2	blueswir1	r_src = cpu_psr;
1243	3475187d	bellard	#else
1244	dc99a3f2	blueswir1	r_src = cpu_psr;
1245	3475187d	bellard	#endif
1246	19f329ad	blueswir1	switch (cond) {
1247	19f329ad	blueswir1	case 0x0:
1248	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1249	19f329ad	blueswir1	break;
1250	19f329ad	blueswir1	case 0x1:
1251	19f329ad	blueswir1	gen_op_eval_be(r_dst, r_src);
1252	19f329ad	blueswir1	break;
1253	19f329ad	blueswir1	case 0x2:
1254	19f329ad	blueswir1	gen_op_eval_ble(r_dst, r_src);
1255	19f329ad	blueswir1	break;
1256	19f329ad	blueswir1	case 0x3:
1257	19f329ad	blueswir1	gen_op_eval_bl(r_dst, r_src);
1258	19f329ad	blueswir1	break;
1259	19f329ad	blueswir1	case 0x4:
1260	19f329ad	blueswir1	gen_op_eval_bleu(r_dst, r_src);
1261	19f329ad	blueswir1	break;
1262	19f329ad	blueswir1	case 0x5:
1263	19f329ad	blueswir1	gen_op_eval_bcs(r_dst, r_src);
1264	19f329ad	blueswir1	break;
1265	19f329ad	blueswir1	case 0x6:
1266	19f329ad	blueswir1	gen_op_eval_bneg(r_dst, r_src);
1267	19f329ad	blueswir1	break;
1268	19f329ad	blueswir1	case 0x7:
1269	19f329ad	blueswir1	gen_op_eval_bvs(r_dst, r_src);
1270	19f329ad	blueswir1	break;
1271	19f329ad	blueswir1	case 0x8:
1272	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1273	19f329ad	blueswir1	break;
1274	19f329ad	blueswir1	case 0x9:
1275	19f329ad	blueswir1	gen_op_eval_bne(r_dst, r_src);
1276	19f329ad	blueswir1	break;
1277	19f329ad	blueswir1	case 0xa:
1278	19f329ad	blueswir1	gen_op_eval_bg(r_dst, r_src);
1279	19f329ad	blueswir1	break;
1280	19f329ad	blueswir1	case 0xb:
1281	19f329ad	blueswir1	gen_op_eval_bge(r_dst, r_src);
1282	19f329ad	blueswir1	break;
1283	19f329ad	blueswir1	case 0xc:
1284	19f329ad	blueswir1	gen_op_eval_bgu(r_dst, r_src);
1285	19f329ad	blueswir1	break;
1286	19f329ad	blueswir1	case 0xd:
1287	19f329ad	blueswir1	gen_op_eval_bcc(r_dst, r_src);
1288	19f329ad	blueswir1	break;
1289	19f329ad	blueswir1	case 0xe:
1290	19f329ad	blueswir1	gen_op_eval_bpos(r_dst, r_src);
1291	19f329ad	blueswir1	break;
1292	19f329ad	blueswir1	case 0xf:
1293	19f329ad	blueswir1	gen_op_eval_bvc(r_dst, r_src);
1294	19f329ad	blueswir1	break;
1295	19f329ad	blueswir1	}
1296	19f329ad	blueswir1	}
1297	7a3f1944	bellard
1298	19f329ad	blueswir1	static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1299	e8af50a3	bellard	{
1300	19f329ad	blueswir1	unsigned int offset;
1301	19f329ad	blueswir1
1302	19f329ad	blueswir1	switch (cc) {
1303	19f329ad	blueswir1	default:
1304	19f329ad	blueswir1	case 0x0:
1305	19f329ad	blueswir1	offset = 0;
1306	19f329ad	blueswir1	break;
1307	19f329ad	blueswir1	case 0x1:
1308	19f329ad	blueswir1	offset = 32 - 10;
1309	19f329ad	blueswir1	break;
1310	19f329ad	blueswir1	case 0x2:
1311	19f329ad	blueswir1	offset = 34 - 10;
1312	19f329ad	blueswir1	break;
1313	19f329ad	blueswir1	case 0x3:
1314	19f329ad	blueswir1	offset = 36 - 10;
1315	19f329ad	blueswir1	break;
1316	19f329ad	blueswir1	}
1317	19f329ad	blueswir1
1318	19f329ad	blueswir1	switch (cond) {
1319	19f329ad	blueswir1	case 0x0:
1320	19f329ad	blueswir1	gen_op_eval_bn(r_dst);
1321	19f329ad	blueswir1	break;
1322	19f329ad	blueswir1	case 0x1:
1323	87e92502	blueswir1	gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1324	19f329ad	blueswir1	break;
1325	19f329ad	blueswir1	case 0x2:
1326	87e92502	blueswir1	gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1327	19f329ad	blueswir1	break;
1328	19f329ad	blueswir1	case 0x3:
1329	87e92502	blueswir1	gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1330	19f329ad	blueswir1	break;
1331	19f329ad	blueswir1	case 0x4:
1332	87e92502	blueswir1	gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1333	19f329ad	blueswir1	break;
1334	19f329ad	blueswir1	case 0x5:
1335	87e92502	blueswir1	gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1336	19f329ad	blueswir1	break;
1337	19f329ad	blueswir1	case 0x6:
1338	87e92502	blueswir1	gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1339	19f329ad	blueswir1	break;
1340	19f329ad	blueswir1	case 0x7:
1341	87e92502	blueswir1	gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1342	19f329ad	blueswir1	break;
1343	19f329ad	blueswir1	case 0x8:
1344	19f329ad	blueswir1	gen_op_eval_ba(r_dst);
1345	19f329ad	blueswir1	break;
1346	19f329ad	blueswir1	case 0x9:
1347	87e92502	blueswir1	gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1348	19f329ad	blueswir1	break;
1349	19f329ad	blueswir1	case 0xa:
1350	87e92502	blueswir1	gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1351	19f329ad	blueswir1	break;
1352	19f329ad	blueswir1	case 0xb:
1353	87e92502	blueswir1	gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1354	19f329ad	blueswir1	break;
1355	19f329ad	blueswir1	case 0xc:
1356	87e92502	blueswir1	gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1357	19f329ad	blueswir1	break;
1358	19f329ad	blueswir1	case 0xd:
1359	87e92502	blueswir1	gen_op_eval_fble(r_dst, cpu_fsr, offset);
1360	19f329ad	blueswir1	break;
1361	19f329ad	blueswir1	case 0xe:
1362	87e92502	blueswir1	gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1363	19f329ad	blueswir1	break;
1364	19f329ad	blueswir1	case 0xf:
1365	87e92502	blueswir1	gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1366	19f329ad	blueswir1	break;
1367	19f329ad	blueswir1	}
1368	e8af50a3	bellard	}
1369	00f219bf	blueswir1
1370	19f329ad	blueswir1	#ifdef TARGET_SPARC64
1371	00f219bf	blueswir1	// Inverted logic
1372	00f219bf	blueswir1	static const int gen_tcg_cond_reg[8] = {
1373	00f219bf	blueswir1	-1,
1374	00f219bf	blueswir1	TCG_COND_NE,
1375	00f219bf	blueswir1	TCG_COND_GT,
1376	00f219bf	blueswir1	TCG_COND_GE,
1377	00f219bf	blueswir1	-1,
1378	00f219bf	blueswir1	TCG_COND_EQ,
1379	00f219bf	blueswir1	TCG_COND_LE,
1380	00f219bf	blueswir1	TCG_COND_LT,
1381	00f219bf	blueswir1	};
1382	19f329ad	blueswir1
1383	4af984a7	blueswir1	static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1384	19f329ad	blueswir1	{
1385	19f329ad	blueswir1	int l1;
1386	19f329ad	blueswir1
1387	19f329ad	blueswir1	l1 = gen_new_label();
1388	0425bee5	blueswir1	tcg_gen_movi_tl(r_dst, 0);
1389	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1390	19f329ad	blueswir1	tcg_gen_movi_tl(r_dst, 1);
1391	19f329ad	blueswir1	gen_set_label(l1);
1392	19f329ad	blueswir1	}
1393	3475187d	bellard	#endif
1394	cf495bcf	bellard
1395	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1396	4af984a7	blueswir1	static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1397	4af984a7	blueswir1	TCGv r_cond)
1398	7a3f1944	bellard	{
1399	cf495bcf	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1400	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1401	5fafdf24	ths
1402	cf495bcf	bellard	if (cond == 0x0) {
1403	0f8a249a	blueswir1	/* unconditional not taken */
1404	0f8a249a	blueswir1	if (a) {
1405	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1406	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1407	0f8a249a	blueswir1	} else {
1408	0f8a249a	blueswir1	dc->pc = dc->npc;
1409	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1410	0f8a249a	blueswir1	}
1411	cf495bcf	bellard	} else if (cond == 0x8) {
1412	0f8a249a	blueswir1	/* unconditional taken */
1413	0f8a249a	blueswir1	if (a) {
1414	0f8a249a	blueswir1	dc->pc = target;
1415	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1416	0f8a249a	blueswir1	} else {
1417	0f8a249a	blueswir1	dc->pc = dc->npc;
1418	0f8a249a	blueswir1	dc->npc = target;
1419	0f8a249a	blueswir1	}
1420	cf495bcf	bellard	} else {
1421	4af984a7	blueswir1	flush_cond(dc, r_cond);
1422	4af984a7	blueswir1	gen_cond(r_cond, cc, cond);
1423	0f8a249a	blueswir1	if (a) {
1424	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1425	cf495bcf	bellard	dc->is_br = 1;
1426	0f8a249a	blueswir1	} else {
1427	cf495bcf	bellard	dc->pc = dc->npc;
1428	72cbca10	bellard	dc->jump_pc[0] = target;
1429	72cbca10	bellard	dc->jump_pc[1] = dc->npc + 4;
1430	72cbca10	bellard	dc->npc = JUMP_PC;
1431	0f8a249a	blueswir1	}
1432	cf495bcf	bellard	}
1433	7a3f1944	bellard	}
1434	7a3f1944	bellard
1435	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
1436	4af984a7	blueswir1	static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1437	4af984a7	blueswir1	TCGv r_cond)
1438	e8af50a3	bellard	{
1439	e8af50a3	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1440	af7bf89b	bellard	target_ulong target = dc->pc + offset;
1441	af7bf89b	bellard
1442	e8af50a3	bellard	if (cond == 0x0) {
1443	0f8a249a	blueswir1	/* unconditional not taken */
1444	0f8a249a	blueswir1	if (a) {
1445	0f8a249a	blueswir1	dc->pc = dc->npc + 4;
1446	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1447	0f8a249a	blueswir1	} else {
1448	0f8a249a	blueswir1	dc->pc = dc->npc;
1449	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1450	0f8a249a	blueswir1	}
1451	e8af50a3	bellard	} else if (cond == 0x8) {
1452	0f8a249a	blueswir1	/* unconditional taken */
1453	0f8a249a	blueswir1	if (a) {
1454	0f8a249a	blueswir1	dc->pc = target;
1455	0f8a249a	blueswir1	dc->npc = dc->pc + 4;
1456	0f8a249a	blueswir1	} else {
1457	0f8a249a	blueswir1	dc->pc = dc->npc;
1458	0f8a249a	blueswir1	dc->npc = target;
1459	0f8a249a	blueswir1	}
1460	e8af50a3	bellard	} else {
1461	4af984a7	blueswir1	flush_cond(dc, r_cond);
1462	4af984a7	blueswir1	gen_fcond(r_cond, cc, cond);
1463	0f8a249a	blueswir1	if (a) {
1464	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1465	e8af50a3	bellard	dc->is_br = 1;
1466	0f8a249a	blueswir1	} else {
1467	e8af50a3	bellard	dc->pc = dc->npc;
1468	e8af50a3	bellard	dc->jump_pc[0] = target;
1469	e8af50a3	bellard	dc->jump_pc[1] = dc->npc + 4;
1470	e8af50a3	bellard	dc->npc = JUMP_PC;
1471	0f8a249a	blueswir1	}
1472	e8af50a3	bellard	}
1473	e8af50a3	bellard	}
1474	e8af50a3	bellard
1475	3475187d	bellard	#ifdef TARGET_SPARC64
1476	3475187d	bellard	/* XXX: potentially incorrect if dynamic npc */
1477	4af984a7	blueswir1	static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1478	4af984a7	blueswir1	TCGv r_cond, TCGv r_reg)
1479	7a3f1944	bellard	{
1480	3475187d	bellard	unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1481	3475187d	bellard	target_ulong target = dc->pc + offset;
1482	3475187d	bellard
1483	4af984a7	blueswir1	flush_cond(dc, r_cond);
1484	4af984a7	blueswir1	gen_cond_reg(r_cond, cond, r_reg);
1485	3475187d	bellard	if (a) {
1486	4af984a7	blueswir1	gen_branch_a(dc, target, dc->npc, r_cond);
1487	0f8a249a	blueswir1	dc->is_br = 1;
1488	3475187d	bellard	} else {
1489	0f8a249a	blueswir1	dc->pc = dc->npc;
1490	0f8a249a	blueswir1	dc->jump_pc[0] = target;
1491	0f8a249a	blueswir1	dc->jump_pc[1] = dc->npc + 4;
1492	0f8a249a	blueswir1	dc->npc = JUMP_PC;
1493	3475187d	bellard	}
1494	7a3f1944	bellard	}
1495	7a3f1944	bellard
1496	3475187d	bellard	static GenOpFunc * const gen_fcmps[4] = {
1497	7e8c2b6c	blueswir1	helper_fcmps,
1498	7e8c2b6c	blueswir1	helper_fcmps_fcc1,
1499	7e8c2b6c	blueswir1	helper_fcmps_fcc2,
1500	7e8c2b6c	blueswir1	helper_fcmps_fcc3,
1501	3475187d	bellard	};
1502	3475187d	bellard
1503	3475187d	bellard	static GenOpFunc * const gen_fcmpd[4] = {
1504	7e8c2b6c	blueswir1	helper_fcmpd,
1505	7e8c2b6c	blueswir1	helper_fcmpd_fcc1,
1506	7e8c2b6c	blueswir1	helper_fcmpd_fcc2,
1507	7e8c2b6c	blueswir1	helper_fcmpd_fcc3,
1508	3475187d	bellard	};
1509	417454b0	blueswir1
1510	1f587329	blueswir1	static GenOpFunc * const gen_fcmpq[4] = {
1511	7e8c2b6c	blueswir1	helper_fcmpq,
1512	7e8c2b6c	blueswir1	helper_fcmpq_fcc1,
1513	7e8c2b6c	blueswir1	helper_fcmpq_fcc2,
1514	7e8c2b6c	blueswir1	helper_fcmpq_fcc3,
1515	1f587329	blueswir1	};
1516	1f587329	blueswir1
1517	417454b0	blueswir1	static GenOpFunc * const gen_fcmpes[4] = {
1518	7e8c2b6c	blueswir1	helper_fcmpes,
1519	7e8c2b6c	blueswir1	helper_fcmpes_fcc1,
1520	7e8c2b6c	blueswir1	helper_fcmpes_fcc2,
1521	7e8c2b6c	blueswir1	helper_fcmpes_fcc3,
1522	417454b0	blueswir1	};
1523	417454b0	blueswir1
1524	417454b0	blueswir1	static GenOpFunc * const gen_fcmped[4] = {
1525	7e8c2b6c	blueswir1	helper_fcmped,
1526	7e8c2b6c	blueswir1	helper_fcmped_fcc1,
1527	7e8c2b6c	blueswir1	helper_fcmped_fcc2,
1528	7e8c2b6c	blueswir1	helper_fcmped_fcc3,
1529	417454b0	blueswir1	};
1530	417454b0	blueswir1
1531	1f587329	blueswir1	static GenOpFunc * const gen_fcmpeq[4] = {
1532	7e8c2b6c	blueswir1	helper_fcmpeq,
1533	7e8c2b6c	blueswir1	helper_fcmpeq_fcc1,
1534	7e8c2b6c	blueswir1	helper_fcmpeq_fcc2,
1535	7e8c2b6c	blueswir1	helper_fcmpeq_fcc3,
1536	1f587329	blueswir1	};
1537	7e8c2b6c	blueswir1
1538	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1539	7e8c2b6c	blueswir1	{
1540	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmps[fccno]);
1541	7e8c2b6c	blueswir1	}
1542	7e8c2b6c	blueswir1
1543	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1544	7e8c2b6c	blueswir1	{
1545	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1546	7e8c2b6c	blueswir1	}
1547	7e8c2b6c	blueswir1
1548	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1549	7e8c2b6c	blueswir1	{
1550	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1551	7e8c2b6c	blueswir1	}
1552	7e8c2b6c	blueswir1
1553	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1554	7e8c2b6c	blueswir1	{
1555	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1556	7e8c2b6c	blueswir1	}
1557	7e8c2b6c	blueswir1
1558	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1559	7e8c2b6c	blueswir1	{
1560	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmped[fccno]);
1561	7e8c2b6c	blueswir1	}
1562	7e8c2b6c	blueswir1
1563	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1564	7e8c2b6c	blueswir1	{
1565	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1566	7e8c2b6c	blueswir1	}
1567	7e8c2b6c	blueswir1
1568	7e8c2b6c	blueswir1	#else
1569	7e8c2b6c	blueswir1
1570	7e8c2b6c	blueswir1	static inline void gen_op_fcmps(int fccno)
1571	7e8c2b6c	blueswir1	{
1572	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmps);
1573	7e8c2b6c	blueswir1	}
1574	7e8c2b6c	blueswir1
1575	7e8c2b6c	blueswir1	static inline void gen_op_fcmpd(int fccno)
1576	7e8c2b6c	blueswir1	{
1577	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpd);
1578	7e8c2b6c	blueswir1	}
1579	7e8c2b6c	blueswir1
1580	7e8c2b6c	blueswir1	static inline void gen_op_fcmpq(int fccno)
1581	7e8c2b6c	blueswir1	{
1582	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpq);
1583	7e8c2b6c	blueswir1	}
1584	7e8c2b6c	blueswir1
1585	7e8c2b6c	blueswir1	static inline void gen_op_fcmpes(int fccno)
1586	7e8c2b6c	blueswir1	{
1587	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpes);
1588	7e8c2b6c	blueswir1	}
1589	7e8c2b6c	blueswir1
1590	7e8c2b6c	blueswir1	static inline void gen_op_fcmped(int fccno)
1591	7e8c2b6c	blueswir1	{
1592	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmped);
1593	7e8c2b6c	blueswir1	}
1594	7e8c2b6c	blueswir1
1595	7e8c2b6c	blueswir1	static inline void gen_op_fcmpeq(int fccno)
1596	7e8c2b6c	blueswir1	{
1597	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq);
1598	7e8c2b6c	blueswir1	}
1599	7e8c2b6c	blueswir1	#endif
1600	7e8c2b6c	blueswir1
1601	134d77a1	blueswir1	static inline void gen_op_fpexception_im(int fsr_flags)
1602	134d77a1	blueswir1	{
1603	2ea815ca	blueswir1	TCGv r_const;
1604	2ea815ca	blueswir1
1605	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1606	87e92502	blueswir1	tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1607	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_FP_EXCP);
1608	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1609	2ea815ca	blueswir1	tcg_temp_free(r_const);
1610	134d77a1	blueswir1	}
1611	134d77a1	blueswir1
1612	4af984a7	blueswir1	static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1613	a80dde08	bellard	{
1614	a80dde08	bellard	#if !defined(CONFIG_USER_ONLY)
1615	a80dde08	bellard	if (!dc->fpu_enabled) {
1616	2ea815ca	blueswir1	TCGv r_const;
1617	2ea815ca	blueswir1
1618	4af984a7	blueswir1	save_state(dc, r_cond);
1619	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NFPU_INSN);
1620	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
1621	2ea815ca	blueswir1	tcg_temp_free(r_const);
1622	a80dde08	bellard	dc->is_br = 1;
1623	a80dde08	bellard	return 1;
1624	a80dde08	bellard	}
1625	a80dde08	bellard	#endif
1626	a80dde08	bellard	return 0;
1627	a80dde08	bellard	}
1628	a80dde08	bellard
1629	7e8c2b6c	blueswir1	static inline void gen_op_clear_ieee_excp_and_FTT(void)
1630	7e8c2b6c	blueswir1	{
1631	87e92502	blueswir1	tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK \| FSR_CEXC_MASK));
1632	7e8c2b6c	blueswir1	}
1633	7e8c2b6c	blueswir1
1634	7e8c2b6c	blueswir1	static inline void gen_clear_float_exceptions(void)
1635	7e8c2b6c	blueswir1	{
1636	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_clear_float_exceptions);
1637	7e8c2b6c	blueswir1	}
1638	7e8c2b6c	blueswir1
1639	1a2fb1c0	blueswir1	/* asi moves */
1640	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
1641	0425bee5	blueswir1	static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1642	1a2fb1c0	blueswir1	{
1643	95f9397c	blueswir1	int asi;
1644	0425bee5	blueswir1	TCGv r_asi;
1645	1a2fb1c0	blueswir1
1646	1a2fb1c0	blueswir1	if (IS_IMM) {
1647	0425bee5	blueswir1	r_asi = tcg_temp_new(TCG_TYPE_I32);
1648	0425bee5	blueswir1	tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1649	1a2fb1c0	blueswir1	} else {
1650	1a2fb1c0	blueswir1	asi = GET_FIELD(insn, 19, 26);
1651	0425bee5	blueswir1	r_asi = tcg_const_i32(asi);
1652	1a2fb1c0	blueswir1	}
1653	0425bee5	blueswir1	return r_asi;
1654	0425bee5	blueswir1	}
1655	0425bee5	blueswir1
1656	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1657	77f193da	blueswir1	int sign)
1658	0425bee5	blueswir1	{
1659	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1660	0425bee5	blueswir1
1661	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1662	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1663	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1664	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1665	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1666	2ea815ca	blueswir1	tcg_temp_free(r_size);
1667	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1668	1a2fb1c0	blueswir1	}
1669	1a2fb1c0	blueswir1
1670	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1671	1a2fb1c0	blueswir1	{
1672	2ea815ca	blueswir1	TCGv r_asi, r_size;
1673	1a2fb1c0	blueswir1
1674	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1675	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1676	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1677	2ea815ca	blueswir1	tcg_temp_free(r_size);
1678	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1679	1a2fb1c0	blueswir1	}
1680	1a2fb1c0	blueswir1
1681	4af984a7	blueswir1	static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1682	1a2fb1c0	blueswir1	{
1683	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1684	1a2fb1c0	blueswir1
1685	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1686	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1687	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1688	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1689	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1690	2ea815ca	blueswir1	tcg_temp_free(r_size);
1691	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1692	1a2fb1c0	blueswir1	}
1693	1a2fb1c0	blueswir1
1694	4af984a7	blueswir1	static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1695	1a2fb1c0	blueswir1	{
1696	2ea815ca	blueswir1	TCGv r_asi, r_size, r_rd;
1697	1a2fb1c0	blueswir1
1698	31741a27	blueswir1	r_asi = gen_get_asi(insn, addr);
1699	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1700	2ea815ca	blueswir1	r_rd = tcg_const_i32(rd);
1701	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1702	2ea815ca	blueswir1	tcg_temp_free(r_rd);
1703	2ea815ca	blueswir1	tcg_temp_free(r_size);
1704	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1705	1a2fb1c0	blueswir1	}
1706	1a2fb1c0	blueswir1
1707	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1708	1a2fb1c0	blueswir1	{
1709	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1710	1a2fb1c0	blueswir1
1711	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1712	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1713	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1714	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1715	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1716	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1717	2ea815ca	blueswir1	tcg_temp_free(r_size);
1718	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1719	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1720	1a2fb1c0	blueswir1	}
1721	1a2fb1c0	blueswir1
1722	db166940	blueswir1	static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1723	1a2fb1c0	blueswir1	{
1724	db166940	blueswir1	TCGv r_asi, r_rd;
1725	1a2fb1c0	blueswir1
1726	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1727	db166940	blueswir1	r_rd = tcg_const_i32(rd);
1728	db166940	blueswir1	tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1729	db166940	blueswir1	tcg_temp_free(r_rd);
1730	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1731	0425bee5	blueswir1	}
1732	0425bee5	blueswir1
1733	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1734	0425bee5	blueswir1	{
1735	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1736	0425bee5	blueswir1
1737	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1738	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1739	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1740	0425bee5	blueswir1	r_temp);
1741	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1742	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1743	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1744	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1745	2ea815ca	blueswir1	tcg_temp_free(r_size);
1746	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1747	1a2fb1c0	blueswir1	}
1748	1a2fb1c0	blueswir1
1749	77f193da	blueswir1	static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1750	77f193da	blueswir1	int rd)
1751	1a2fb1c0	blueswir1	{
1752	1a2fb1c0	blueswir1	TCGv r_val1, r_asi;
1753	1a2fb1c0	blueswir1
1754	ef28fd86	blueswir1	r_val1 = tcg_temp_new(TCG_TYPE_TL);
1755	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd, r_val1);
1756	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1757	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1758	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1759	2ea815ca	blueswir1	tcg_temp_free(r_val1);
1760	1a2fb1c0	blueswir1	}
1761	1a2fb1c0	blueswir1
1762	77f193da	blueswir1	static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1763	77f193da	blueswir1	int rd)
1764	1a2fb1c0	blueswir1	{
1765	8911f501	blueswir1	TCGv r_asi;
1766	1a2fb1c0	blueswir1
1767	8911f501	blueswir1	gen_movl_reg_TN(rd, cpu_tmp64);
1768	4af984a7	blueswir1	r_asi = gen_get_asi(insn, addr);
1769	4af984a7	blueswir1	tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1770	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1771	1a2fb1c0	blueswir1	}
1772	1a2fb1c0	blueswir1
1773	1a2fb1c0	blueswir1	#elif !defined(CONFIG_USER_ONLY)
1774	1a2fb1c0	blueswir1
1775	77f193da	blueswir1	static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1776	77f193da	blueswir1	int sign)
1777	1a2fb1c0	blueswir1	{
1778	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1779	1a2fb1c0	blueswir1
1780	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1781	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1782	2ea815ca	blueswir1	r_sign = tcg_const_i32(sign);
1783	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1784	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1785	2ea815ca	blueswir1	tcg_temp_free(r_size);
1786	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1787	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1788	1a2fb1c0	blueswir1	}
1789	1a2fb1c0	blueswir1
1790	4af984a7	blueswir1	static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1791	1a2fb1c0	blueswir1	{
1792	2ea815ca	blueswir1	TCGv r_asi, r_size;
1793	1a2fb1c0	blueswir1
1794	4af984a7	blueswir1	tcg_gen_extu_tl_i64(cpu_tmp64, src);
1795	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1796	2ea815ca	blueswir1	r_size = tcg_const_i32(size);
1797	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1798	2ea815ca	blueswir1	tcg_temp_free(r_size);
1799	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1800	1a2fb1c0	blueswir1	}
1801	1a2fb1c0	blueswir1
1802	4af984a7	blueswir1	static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1803	1a2fb1c0	blueswir1	{
1804	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1805	1a2fb1c0	blueswir1
1806	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1807	2ea815ca	blueswir1	r_size = tcg_const_i32(4);
1808	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1809	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1810	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1811	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1812	2ea815ca	blueswir1	tcg_temp_free(r_size);
1813	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1814	8d96d209	blueswir1	tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1815	1a2fb1c0	blueswir1	}
1816	1a2fb1c0	blueswir1
1817	db166940	blueswir1	static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1818	1a2fb1c0	blueswir1	{
1819	2ea815ca	blueswir1	TCGv r_asi, r_size, r_sign;
1820	1a2fb1c0	blueswir1
1821	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1822	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1823	2ea815ca	blueswir1	r_sign = tcg_const_i32(0);
1824	2ea815ca	blueswir1	tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1825	2ea815ca	blueswir1	tcg_temp_free(r_sign);
1826	2ea815ca	blueswir1	tcg_temp_free(r_size);
1827	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1828	db166940	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1829	db166940	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
1830	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1831	4af984a7	blueswir1	tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1832	db166940	blueswir1	gen_movl_TN_reg(rd, hi);
1833	0425bee5	blueswir1	}
1834	0425bee5	blueswir1
1835	4af984a7	blueswir1	static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1836	0425bee5	blueswir1	{
1837	2ea815ca	blueswir1	TCGv r_temp, r_asi, r_size;
1838	0425bee5	blueswir1
1839	8d96d209	blueswir1	r_temp = tcg_temp_new(TCG_TYPE_TL);
1840	0425bee5	blueswir1	gen_movl_reg_TN(rd + 1, r_temp);
1841	4af984a7	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1842	2ea815ca	blueswir1	tcg_temp_free(r_temp);
1843	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1844	2ea815ca	blueswir1	r_size = tcg_const_i32(8);
1845	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1846	2ea815ca	blueswir1	tcg_temp_free(r_size);
1847	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1848	1a2fb1c0	blueswir1	}
1849	1a2fb1c0	blueswir1	#endif
1850	1a2fb1c0	blueswir1
1851	1a2fb1c0	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
1852	4af984a7	blueswir1	static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1853	1a2fb1c0	blueswir1	{
1854	2ea815ca	blueswir1	TCGv r_val, r_asi, r_size;
1855	1a2fb1c0	blueswir1
1856	4af984a7	blueswir1	gen_ld_asi(dst, addr, insn, 1, 0);
1857	1a2fb1c0	blueswir1
1858	2ea815ca	blueswir1	r_val = tcg_const_i64(0xffULL);
1859	2ea815ca	blueswir1	r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1860	2ea815ca	blueswir1	r_size = tcg_const_i32(1);
1861	2ea815ca	blueswir1	tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1862	2ea815ca	blueswir1	tcg_temp_free(r_size);
1863	2ea815ca	blueswir1	tcg_temp_free(r_asi);
1864	2ea815ca	blueswir1	tcg_temp_free(r_val);
1865	1a2fb1c0	blueswir1	}
1866	1a2fb1c0	blueswir1	#endif
1867	1a2fb1c0	blueswir1
1868	9322a4bf	blueswir1	static inline TCGv get_src1(unsigned int insn, TCGv def)
1869	9322a4bf	blueswir1	{
1870	9322a4bf	blueswir1	TCGv r_rs1 = def;
1871	9322a4bf	blueswir1	unsigned int rs1;
1872	9322a4bf	blueswir1
1873	9322a4bf	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
1874	9322a4bf	blueswir1	if (rs1 == 0)
1875	5c6a0628	blueswir1	r_rs1 = tcg_const_tl(0); // XXX how to free?
1876	9322a4bf	blueswir1	else if (rs1 < 8)
1877	5c6a0628	blueswir1	r_rs1 = cpu_gregs[rs1];
1878	9322a4bf	blueswir1	else
1879	9322a4bf	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1880	9322a4bf	blueswir1	return r_rs1;
1881	9322a4bf	blueswir1	}
1882	9322a4bf	blueswir1
1883	a49d9390	blueswir1	static inline TCGv get_src2(unsigned int insn, TCGv def)
1884	a49d9390	blueswir1	{
1885	a49d9390	blueswir1	TCGv r_rs2 = def;
1886	a49d9390	blueswir1	unsigned int rs2;
1887	a49d9390	blueswir1
1888	a49d9390	blueswir1	if (IS_IMM) { /* immediate */
1889	a49d9390	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
1890	2ea815ca	blueswir1	r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1891	a49d9390	blueswir1	} else { /* register */
1892	a49d9390	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
1893	a49d9390	blueswir1	if (rs2 == 0)
1894	2ea815ca	blueswir1	r_rs2 = tcg_const_tl(0); // XXX how to free?
1895	a49d9390	blueswir1	else if (rs2 < 8)
1896	a49d9390	blueswir1	r_rs2 = cpu_gregs[rs2];
1897	a49d9390	blueswir1	else
1898	a49d9390	blueswir1	tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1899	a49d9390	blueswir1	}
1900	a49d9390	blueswir1	return r_rs2;
1901	a49d9390	blueswir1	}
1902	a49d9390	blueswir1
1903	64a88d5d	blueswir1	#define CHECK_IU_FEATURE(dc, FEATURE) \
1904	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1905	64a88d5d	blueswir1	goto illegal_insn;
1906	64a88d5d	blueswir1	#define CHECK_FPU_FEATURE(dc, FEATURE) \
1907	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1908	64a88d5d	blueswir1	goto nfpu_insn;
1909	64a88d5d	blueswir1
1910	0bee699e	bellard	/* before an instruction, dc->pc must be static */
1911	cf495bcf	bellard	static void disas_sparc_insn(DisasContext * dc)
1912	cf495bcf	bellard	{
1913	cf495bcf	bellard	unsigned int insn, opc, rs1, rs2, rd;
1914	7a3f1944	bellard
1915	a8c768c0	blueswir1	if (unlikely(loglevel & CPU_LOG_TB_OP))
1916	a8c768c0	blueswir1	tcg_gen_debug_insn_start(dc->pc);
1917	0fa85d43	bellard	insn = ldl_code(dc->pc);
1918	cf495bcf	bellard	opc = GET_FIELD(insn, 0, 1);
1919	7a3f1944	bellard
1920	cf495bcf	bellard	rd = GET_FIELD(insn, 2, 6);
1921	6ae20372	blueswir1
1922	5c6a0628	blueswir1	cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1923	5c6a0628	blueswir1	cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1924	6ae20372	blueswir1
1925	cf495bcf	bellard	switch (opc) {
1926	0f8a249a	blueswir1	case 0: /* branches/sethi */
1927	0f8a249a	blueswir1	{
1928	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 9);
1929	0f8a249a	blueswir1	int32_t target;
1930	0f8a249a	blueswir1	switch (xop) {
1931	3475187d	bellard	#ifdef TARGET_SPARC64
1932	0f8a249a	blueswir1	case 0x1: /* V9 BPcc */
1933	0f8a249a	blueswir1	{
1934	0f8a249a	blueswir1	int cc;
1935	0f8a249a	blueswir1
1936	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1937	0f8a249a	blueswir1	target = sign_extend(target, 18);
1938	0f8a249a	blueswir1	target <<= 2;
1939	0f8a249a	blueswir1	cc = GET_FIELD_SP(insn, 20, 21);
1940	0f8a249a	blueswir1	if (cc == 0)
1941	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1942	0f8a249a	blueswir1	else if (cc == 2)
1943	6ae20372	blueswir1	do_branch(dc, target, insn, 1, cpu_cond);
1944	0f8a249a	blueswir1	else
1945	0f8a249a	blueswir1	goto illegal_insn;
1946	0f8a249a	blueswir1	goto jmp_insn;
1947	0f8a249a	blueswir1	}
1948	0f8a249a	blueswir1	case 0x3: /* V9 BPr */
1949	0f8a249a	blueswir1	{
1950	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 13) \|
1951	13846e70	bellard	(GET_FIELD_SP(insn, 20, 21) << 14);
1952	0f8a249a	blueswir1	target = sign_extend(target, 16);
1953	0f8a249a	blueswir1	target <<= 2;
1954	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
1955	6ae20372	blueswir1	do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1956	0f8a249a	blueswir1	goto jmp_insn;
1957	0f8a249a	blueswir1	}
1958	0f8a249a	blueswir1	case 0x5: /* V9 FBPcc */
1959	0f8a249a	blueswir1	{
1960	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 20, 21);
1961	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1962	a80dde08	bellard	goto jmp_insn;
1963	0f8a249a	blueswir1	target = GET_FIELD_SP(insn, 0, 18);
1964	0f8a249a	blueswir1	target = sign_extend(target, 19);
1965	0f8a249a	blueswir1	target <<= 2;
1966	6ae20372	blueswir1	do_fbranch(dc, target, insn, cc, cpu_cond);
1967	0f8a249a	blueswir1	goto jmp_insn;
1968	0f8a249a	blueswir1	}
1969	a4d17f19	blueswir1	#else
1970	0f8a249a	blueswir1	case 0x7: /* CBN+x */
1971	0f8a249a	blueswir1	{
1972	0f8a249a	blueswir1	goto ncp_insn;
1973	0f8a249a	blueswir1	}
1974	0f8a249a	blueswir1	#endif
1975	0f8a249a	blueswir1	case 0x2: /* BN+x */
1976	0f8a249a	blueswir1	{
1977	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1978	0f8a249a	blueswir1	target = sign_extend(target, 22);
1979	0f8a249a	blueswir1	target <<= 2;
1980	6ae20372	blueswir1	do_branch(dc, target, insn, 0, cpu_cond);
1981	0f8a249a	blueswir1	goto jmp_insn;
1982	0f8a249a	blueswir1	}
1983	0f8a249a	blueswir1	case 0x6: /* FBN+x */
1984	0f8a249a	blueswir1	{
1985	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
1986	a80dde08	bellard	goto jmp_insn;
1987	0f8a249a	blueswir1	target = GET_FIELD(insn, 10, 31);
1988	0f8a249a	blueswir1	target = sign_extend(target, 22);
1989	0f8a249a	blueswir1	target <<= 2;
1990	6ae20372	blueswir1	do_fbranch(dc, target, insn, 0, cpu_cond);
1991	0f8a249a	blueswir1	goto jmp_insn;
1992	0f8a249a	blueswir1	}
1993	0f8a249a	blueswir1	case 0x4: /* SETHI */
1994	0f8a249a	blueswir1	if (rd) { // nop
1995	0f8a249a	blueswir1	uint32_t value = GET_FIELD(insn, 10, 31);
1996	2ea815ca	blueswir1	TCGv r_const;
1997	2ea815ca	blueswir1
1998	2ea815ca	blueswir1	r_const = tcg_const_tl(value << 10);
1999	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2000	2ea815ca	blueswir1	tcg_temp_free(r_const);
2001	0f8a249a	blueswir1	}
2002	0f8a249a	blueswir1	break;
2003	0f8a249a	blueswir1	case 0x0: /* UNIMPL */
2004	0f8a249a	blueswir1	default:
2005	3475187d	bellard	goto illegal_insn;
2006	0f8a249a	blueswir1	}
2007	0f8a249a	blueswir1	break;
2008	0f8a249a	blueswir1	}
2009	0f8a249a	blueswir1	break;
2010	cf495bcf	bellard	case 1:
2011	0f8a249a	blueswir1	/CALL/ {
2012	0f8a249a	blueswir1	target_long target = GET_FIELDs(insn, 2, 31) << 2;
2013	2ea815ca	blueswir1	TCGv r_const;
2014	cf495bcf	bellard
2015	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2016	2ea815ca	blueswir1	gen_movl_TN_reg(15, r_const);
2017	2ea815ca	blueswir1	tcg_temp_free(r_const);
2018	0f8a249a	blueswir1	target += dc->pc;
2019	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
2020	0f8a249a	blueswir1	dc->npc = target;
2021	0f8a249a	blueswir1	}
2022	0f8a249a	blueswir1	goto jmp_insn;
2023	0f8a249a	blueswir1	case 2: /* FPU & Logical Operations */
2024	0f8a249a	blueswir1	{
2025	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
2026	0f8a249a	blueswir1	if (xop == 0x3a) { /* generate trap */
2027	cf495bcf	bellard	int cond;
2028	3475187d	bellard
2029	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2030	0f8a249a	blueswir1	if (IS_IMM) {
2031	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 25, 31);
2032	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2033	cf495bcf	bellard	} else {
2034	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
2035	0f8a249a	blueswir1	if (rs2 != 0) {
2036	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2037	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2038	6f551262	blueswir1	} else
2039	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
2040	cf495bcf	bellard	}
2041	cf495bcf	bellard	cond = GET_FIELD(insn, 3, 6);
2042	cf495bcf	bellard	if (cond == 0x8) {
2043	6ae20372	blueswir1	save_state(dc, cpu_cond);
2044	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_trap, cpu_dst);
2045	af7bf89b	bellard	} else if (cond != 0) {
2046	748b9d8e	blueswir1	TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2047	3475187d	bellard	#ifdef TARGET_SPARC64
2048	0f8a249a	blueswir1	/* V9 icc/xcc */
2049	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
2050	748b9d8e	blueswir1
2051	6ae20372	blueswir1	save_state(dc, cpu_cond);
2052	0f8a249a	blueswir1	if (cc == 0)
2053	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2054	0f8a249a	blueswir1	else if (cc == 2)
2055	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
2056	0f8a249a	blueswir1	else
2057	0f8a249a	blueswir1	goto illegal_insn;
2058	3475187d	bellard	#else
2059	6ae20372	blueswir1	save_state(dc, cpu_cond);
2060	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
2061	3475187d	bellard	#endif
2062	6ae20372	blueswir1	tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2063	2ea815ca	blueswir1	tcg_temp_free(r_cond);
2064	cf495bcf	bellard	}
2065	a80dde08	bellard	gen_op_next_insn();
2066	57fec1fe	bellard	tcg_gen_exit_tb(0);
2067	a80dde08	bellard	dc->is_br = 1;
2068	a80dde08	bellard	goto jmp_insn;
2069	cf495bcf	bellard	} else if (xop == 0x28) {
2070	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2071	cf495bcf	bellard	switch(rs1) {
2072	cf495bcf	bellard	case 0: /* rdy */
2073	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
2074	65fe7b09	blueswir1	case 0x01 ... 0x0e: /* undefined in the SPARCv8
2075	65fe7b09	blueswir1	manual, rdy on the microSPARC
2076	65fe7b09	blueswir1	II */
2077	65fe7b09	blueswir1	case 0x0f: /* stbar in the SPARCv8 manual,
2078	65fe7b09	blueswir1	rdy on the microSPARC II */
2079	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent in the
2080	65fe7b09	blueswir1	SPARCv8 manual, rdy on the
2081	65fe7b09	blueswir1	microSPARC II */
2082	65fe7b09	blueswir1	#endif
2083	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2084	77f193da	blueswir1	offsetof(CPUSPARCState, y));
2085	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2086	cf495bcf	bellard	break;
2087	3475187d	bellard	#ifdef TARGET_SPARC64
2088	0f8a249a	blueswir1	case 0x2: /* V9 rdccr */
2089	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2090	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2091	3475187d	bellard	break;
2092	0f8a249a	blueswir1	case 0x3: /* V9 rdasi */
2093	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2094	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
2095	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2096	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2097	3475187d	bellard	break;
2098	0f8a249a	blueswir1	case 0x4: /* V9 rdtick */
2099	ccd4a219	blueswir1	{
2100	ccd4a219	blueswir1	TCGv r_tickptr;
2101	ccd4a219	blueswir1
2102	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2103	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2104	ccd4a219	blueswir1	offsetof(CPUState, tick));
2105	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2106	ccd4a219	blueswir1	r_tickptr);
2107	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2108	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2109	ccd4a219	blueswir1	}
2110	3475187d	bellard	break;
2111	0f8a249a	blueswir1	case 0x5: /* V9 rdpc */
2112	2ea815ca	blueswir1	{
2113	2ea815ca	blueswir1	TCGv r_const;
2114	2ea815ca	blueswir1
2115	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
2116	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2117	2ea815ca	blueswir1	tcg_temp_free(r_const);
2118	2ea815ca	blueswir1	}
2119	0f8a249a	blueswir1	break;
2120	0f8a249a	blueswir1	case 0x6: /* V9 rdfprs */
2121	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2122	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
2123	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2124	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2125	3475187d	bellard	break;
2126	65fe7b09	blueswir1	case 0xf: /* V9 membar */
2127	65fe7b09	blueswir1	break; /* no effect */
2128	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
2129	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2130	725cb90b	bellard	goto jmp_insn;
2131	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2132	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
2133	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2134	725cb90b	bellard	break;
2135	0f8a249a	blueswir1	case 0x17: /* Tick compare */
2136	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2137	77f193da	blueswir1	offsetof(CPUSPARCState, tick_cmpr));
2138	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2139	83469015	bellard	break;
2140	0f8a249a	blueswir1	case 0x18: /* System tick */
2141	ccd4a219	blueswir1	{
2142	ccd4a219	blueswir1	TCGv r_tickptr;
2143	ccd4a219	blueswir1
2144	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2145	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2146	ccd4a219	blueswir1	offsetof(CPUState, stick));
2147	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2148	ccd4a219	blueswir1	r_tickptr);
2149	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2150	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2151	ccd4a219	blueswir1	}
2152	83469015	bellard	break;
2153	0f8a249a	blueswir1	case 0x19: /* System tick compare */
2154	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2155	77f193da	blueswir1	offsetof(CPUSPARCState, stick_cmpr));
2156	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2157	83469015	bellard	break;
2158	0f8a249a	blueswir1	case 0x10: /* Performance Control */
2159	0f8a249a	blueswir1	case 0x11: /* Performance Instrumentation Counter */
2160	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
2161	0f8a249a	blueswir1	case 0x14: /* Softint set, WO */
2162	0f8a249a	blueswir1	case 0x15: /* Softint clear, WO */
2163	0f8a249a	blueswir1	case 0x16: /* Softint write */
2164	3475187d	bellard	#endif
2165	3475187d	bellard	default:
2166	cf495bcf	bellard	goto illegal_insn;
2167	cf495bcf	bellard	}
2168	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
2169	e9ebed4d	blueswir1	} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2170	3475187d	bellard	#ifndef TARGET_SPARC64
2171	0f8a249a	blueswir1	if (!supervisor(dc))
2172	0f8a249a	blueswir1	goto priv_insn;
2173	6ae20372	blueswir1	tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2174	e9ebed4d	blueswir1	#else
2175	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
2176	e9ebed4d	blueswir1	if (!hypervisor(dc))
2177	e9ebed4d	blueswir1	goto priv_insn;
2178	e9ebed4d	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
2179	e9ebed4d	blueswir1	switch (rs1) {
2180	e9ebed4d	blueswir1	case 0: // hpstate
2181	e9ebed4d	blueswir1	// gen_op_rdhpstate();
2182	e9ebed4d	blueswir1	break;
2183	e9ebed4d	blueswir1	case 1: // htstate
2184	e9ebed4d	blueswir1	// gen_op_rdhtstate();
2185	e9ebed4d	blueswir1	break;
2186	e9ebed4d	blueswir1	case 3: // hintp
2187	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2188	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
2189	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2190	e9ebed4d	blueswir1	break;
2191	e9ebed4d	blueswir1	case 5: // htba
2192	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2193	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
2194	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2195	e9ebed4d	blueswir1	break;
2196	e9ebed4d	blueswir1	case 6: // hver
2197	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2198	77f193da	blueswir1	offsetof(CPUSPARCState, hver));
2199	6ae20372	blueswir1	tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2200	e9ebed4d	blueswir1	break;
2201	e9ebed4d	blueswir1	case 31: // hstick_cmpr
2202	8d7d8c4b	blueswir1	tcg_gen_ld_tl(cpu_dst, cpu_env,
2203	8d7d8c4b	blueswir1	offsetof(CPUSPARCState, hstick_cmpr));
2204	e9ebed4d	blueswir1	break;
2205	e9ebed4d	blueswir1	default:
2206	e9ebed4d	blueswir1	goto illegal_insn;
2207	e9ebed4d	blueswir1	}
2208	e9ebed4d	blueswir1	#endif
2209	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2210	e8af50a3	bellard	break;
2211	3475187d	bellard	} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2212	0f8a249a	blueswir1	if (!supervisor(dc))
2213	0f8a249a	blueswir1	goto priv_insn;
2214	3475187d	bellard	#ifdef TARGET_SPARC64
2215	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
2216	0f8a249a	blueswir1	switch (rs1) {
2217	0f8a249a	blueswir1	case 0: // tpc
2218	375ee38b	blueswir1	{
2219	375ee38b	blueswir1	TCGv r_tsptr;
2220	375ee38b	blueswir1
2221	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2222	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2223	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2224	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2225	375ee38b	blueswir1	offsetof(trap_state, tpc));
2226	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2227	375ee38b	blueswir1	}
2228	0f8a249a	blueswir1	break;
2229	0f8a249a	blueswir1	case 1: // tnpc
2230	375ee38b	blueswir1	{
2231	375ee38b	blueswir1	TCGv r_tsptr;
2232	375ee38b	blueswir1
2233	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2234	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2235	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2236	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2237	375ee38b	blueswir1	offsetof(trap_state, tnpc));
2238	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2239	375ee38b	blueswir1	}
2240	0f8a249a	blueswir1	break;
2241	0f8a249a	blueswir1	case 2: // tstate
2242	375ee38b	blueswir1	{
2243	375ee38b	blueswir1	TCGv r_tsptr;
2244	375ee38b	blueswir1
2245	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2246	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2247	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2248	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2249	375ee38b	blueswir1	offsetof(trap_state, tstate));
2250	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2251	375ee38b	blueswir1	}
2252	0f8a249a	blueswir1	break;
2253	0f8a249a	blueswir1	case 3: // tt
2254	375ee38b	blueswir1	{
2255	375ee38b	blueswir1	TCGv r_tsptr;
2256	375ee38b	blueswir1
2257	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2258	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
2259	375ee38b	blueswir1	offsetof(CPUState, tsptr));
2260	ece43b8d	blueswir1	tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2261	375ee38b	blueswir1	offsetof(trap_state, tt));
2262	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
2263	375ee38b	blueswir1	}
2264	0f8a249a	blueswir1	break;
2265	0f8a249a	blueswir1	case 4: // tick
2266	ccd4a219	blueswir1	{
2267	ccd4a219	blueswir1	TCGv r_tickptr;
2268	ccd4a219	blueswir1
2269	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2270	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
2271	ccd4a219	blueswir1	offsetof(CPUState, tick));
2272	ece43b8d	blueswir1	tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2273	ccd4a219	blueswir1	r_tickptr);
2274	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2275	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
2276	ccd4a219	blueswir1	}
2277	0f8a249a	blueswir1	break;
2278	0f8a249a	blueswir1	case 5: // tba
2279	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2280	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
2281	0f8a249a	blueswir1	break;
2282	0f8a249a	blueswir1	case 6: // pstate
2283	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2284	77f193da	blueswir1	offsetof(CPUSPARCState, pstate));
2285	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2286	0f8a249a	blueswir1	break;
2287	0f8a249a	blueswir1	case 7: // tl
2288	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2289	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
2290	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2291	0f8a249a	blueswir1	break;
2292	0f8a249a	blueswir1	case 8: // pil
2293	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2294	77f193da	blueswir1	offsetof(CPUSPARCState, psrpil));
2295	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2296	0f8a249a	blueswir1	break;
2297	0f8a249a	blueswir1	case 9: // cwp
2298	ece43b8d	blueswir1	tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2299	0f8a249a	blueswir1	break;
2300	0f8a249a	blueswir1	case 10: // cansave
2301	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2302	77f193da	blueswir1	offsetof(CPUSPARCState, cansave));
2303	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2304	0f8a249a	blueswir1	break;
2305	0f8a249a	blueswir1	case 11: // canrestore
2306	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2307	77f193da	blueswir1	offsetof(CPUSPARCState, canrestore));
2308	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2309	0f8a249a	blueswir1	break;
2310	0f8a249a	blueswir1	case 12: // cleanwin
2311	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2312	77f193da	blueswir1	offsetof(CPUSPARCState, cleanwin));
2313	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2314	0f8a249a	blueswir1	break;
2315	0f8a249a	blueswir1	case 13: // otherwin
2316	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2317	77f193da	blueswir1	offsetof(CPUSPARCState, otherwin));
2318	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2319	0f8a249a	blueswir1	break;
2320	0f8a249a	blueswir1	case 14: // wstate
2321	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2322	77f193da	blueswir1	offsetof(CPUSPARCState, wstate));
2323	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2324	0f8a249a	blueswir1	break;
2325	e9ebed4d	blueswir1	case 16: // UA2005 gl
2326	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, GL);
2327	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2328	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
2329	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2330	e9ebed4d	blueswir1	break;
2331	e9ebed4d	blueswir1	case 26: // UA2005 strand status
2332	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
2333	e9ebed4d	blueswir1	if (!hypervisor(dc))
2334	e9ebed4d	blueswir1	goto priv_insn;
2335	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2336	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
2337	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2338	e9ebed4d	blueswir1	break;
2339	0f8a249a	blueswir1	case 31: // ver
2340	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2341	77f193da	blueswir1	offsetof(CPUSPARCState, version));
2342	0f8a249a	blueswir1	break;
2343	0f8a249a	blueswir1	case 15: // fq
2344	0f8a249a	blueswir1	default:
2345	0f8a249a	blueswir1	goto illegal_insn;
2346	0f8a249a	blueswir1	}
2347	3475187d	bellard	#else
2348	77f193da	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2349	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
2350	ece43b8d	blueswir1	tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2351	3475187d	bellard	#endif
2352	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2353	e8af50a3	bellard	break;
2354	3475187d	bellard	} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2355	3475187d	bellard	#ifdef TARGET_SPARC64
2356	c5f2f668	blueswir1	save_state(dc, cpu_cond);
2357	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_flushw);
2358	3475187d	bellard	#else
2359	0f8a249a	blueswir1	if (!supervisor(dc))
2360	0f8a249a	blueswir1	goto priv_insn;
2361	ece43b8d	blueswir1	tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2362	ece43b8d	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
2363	3475187d	bellard	#endif
2364	e8af50a3	bellard	break;
2365	e8af50a3	bellard	#endif
2366	0f8a249a	blueswir1	} else if (xop == 0x34) { /* FPU Operations */
2367	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2368	a80dde08	bellard	goto jmp_insn;
2369	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2370	e8af50a3	bellard	rs1 = GET_FIELD(insn, 13, 17);
2371	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2372	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2373	0f8a249a	blueswir1	switch (xop) {
2374	0f8a249a	blueswir1	case 0x1: /* fmovs */
2375	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs2);
2376	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2377	0f8a249a	blueswir1	break;
2378	0f8a249a	blueswir1	case 0x5: /* fnegs */
2379	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2380	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegs);
2381	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2382	0f8a249a	blueswir1	break;
2383	0f8a249a	blueswir1	case 0x9: /* fabss */
2384	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2385	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabss);
2386	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2387	0f8a249a	blueswir1	break;
2388	0f8a249a	blueswir1	case 0x29: /* fsqrts */
2389	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2390	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2391	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2392	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrts);
2393	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2394	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2395	0f8a249a	blueswir1	break;
2396	0f8a249a	blueswir1	case 0x2a: /* fsqrtd */
2397	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FSQRT);
2398	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2399	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2400	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtd);
2401	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2402	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2403	0f8a249a	blueswir1	break;
2404	0f8a249a	blueswir1	case 0x2b: /* fsqrtq */
2405	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2406	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2407	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2408	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fsqrtq);
2409	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2410	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2411	1f587329	blueswir1	break;
2412	0f8a249a	blueswir1	case 0x41:
2413	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2414	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2415	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2416	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fadds);
2417	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2418	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2419	0f8a249a	blueswir1	break;
2420	0f8a249a	blueswir1	case 0x42:
2421	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2422	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2423	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2424	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddd);
2425	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2426	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2427	0f8a249a	blueswir1	break;
2428	0f8a249a	blueswir1	case 0x43: /* faddq */
2429	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2430	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2431	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2432	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2433	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faddq);
2434	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2435	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2436	1f587329	blueswir1	break;
2437	0f8a249a	blueswir1	case 0x45:
2438	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2439	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2440	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2441	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubs);
2442	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2444	0f8a249a	blueswir1	break;
2445	0f8a249a	blueswir1	case 0x46:
2446	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2447	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2448	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2449	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubd);
2450	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2452	0f8a249a	blueswir1	break;
2453	0f8a249a	blueswir1	case 0x47: /* fsubq */
2454	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2455	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2456	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2457	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2458	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsubq);
2459	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2460	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2461	1f587329	blueswir1	break;
2462	64a88d5d	blueswir1	case 0x49: /* fmuls */
2463	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2464	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2465	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2466	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2467	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuls);
2468	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2469	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2470	0f8a249a	blueswir1	break;
2471	64a88d5d	blueswir1	case 0x4a: /* fmuld */
2472	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2473	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2474	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2475	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2476	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld);
2477	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2478	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2479	0f8a249a	blueswir1	break;
2480	0f8a249a	blueswir1	case 0x4b: /* fmulq */
2481	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2482	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FMUL);
2483	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2484	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2485	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2486	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmulq);
2487	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2488	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2489	1f587329	blueswir1	break;
2490	0f8a249a	blueswir1	case 0x4d:
2491	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2492	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2493	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2494	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivs);
2495	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2496	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2497	0f8a249a	blueswir1	break;
2498	0f8a249a	blueswir1	case 0x4e:
2499	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2500	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2501	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2502	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivd);
2503	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2504	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2505	0f8a249a	blueswir1	break;
2506	0f8a249a	blueswir1	case 0x4f: /* fdivq */
2507	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2508	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2509	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2510	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2511	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdivq);
2512	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2513	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2514	1f587329	blueswir1	break;
2515	0f8a249a	blueswir1	case 0x69:
2516	e30b4678	blueswir1	CHECK_FPU_FEATURE(dc, FSMULD);
2517	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2518	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2519	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2520	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fsmuld);
2521	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2522	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2523	0f8a249a	blueswir1	break;
2524	0f8a249a	blueswir1	case 0x6e: /* fdmulq */
2525	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2526	1f587329	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2527	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2528	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2529	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdmulq);
2530	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2531	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2532	1f587329	blueswir1	break;
2533	0f8a249a	blueswir1	case 0xc4:
2534	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2535	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2536	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitos);
2537	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2538	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2539	0f8a249a	blueswir1	break;
2540	0f8a249a	blueswir1	case 0xc6:
2541	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2542	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2543	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtos);
2544	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2545	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2546	0f8a249a	blueswir1	break;
2547	0f8a249a	blueswir1	case 0xc7: /* fqtos */
2548	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2549	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2550	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2551	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtos);
2552	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2553	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2554	1f587329	blueswir1	break;
2555	0f8a249a	blueswir1	case 0xc8:
2556	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2557	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitod);
2558	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2559	0f8a249a	blueswir1	break;
2560	0f8a249a	blueswir1	case 0xc9:
2561	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2562	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstod);
2563	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2564	0f8a249a	blueswir1	break;
2565	0f8a249a	blueswir1	case 0xcb: /* fqtod */
2566	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2567	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2568	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2569	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtod);
2570	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2571	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2572	1f587329	blueswir1	break;
2573	0f8a249a	blueswir1	case 0xcc: /* fitoq */
2574	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2575	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2576	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fitoq);
2577	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2578	1f587329	blueswir1	break;
2579	0f8a249a	blueswir1	case 0xcd: /* fstoq */
2580	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2581	1f587329	blueswir1	gen_op_load_fpr_FT1(rs2);
2582	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoq);
2583	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2584	1f587329	blueswir1	break;
2585	0f8a249a	blueswir1	case 0xce: /* fdtoq */
2586	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2587	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2588	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoq);
2589	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2590	1f587329	blueswir1	break;
2591	0f8a249a	blueswir1	case 0xd1:
2592	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2593	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2594	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstoi);
2595	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2596	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2597	0f8a249a	blueswir1	break;
2598	0f8a249a	blueswir1	case 0xd2:
2599	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2600	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2601	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtoi);
2602	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2603	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2604	0f8a249a	blueswir1	break;
2605	0f8a249a	blueswir1	case 0xd3: /* fqtoi */
2606	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2607	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2608	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2609	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtoi);
2610	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2611	1f587329	blueswir1	gen_op_store_FT0_fpr(rd);
2612	1f587329	blueswir1	break;
2613	3475187d	bellard	#ifdef TARGET_SPARC64
2614	0f8a249a	blueswir1	case 0x2: /* V9 fmovd */
2615	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2616	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2617	0f8a249a	blueswir1	break;
2618	1f587329	blueswir1	case 0x3: /* V9 fmovq */
2619	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2620	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2621	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2622	1f587329	blueswir1	break;
2623	0f8a249a	blueswir1	case 0x6: /* V9 fnegd */
2624	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2625	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegd);
2626	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2627	0f8a249a	blueswir1	break;
2628	1f587329	blueswir1	case 0x7: /* V9 fnegq */
2629	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2630	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2631	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnegq);
2632	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2633	1f587329	blueswir1	break;
2634	0f8a249a	blueswir1	case 0xa: /* V9 fabsd */
2635	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2636	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsd);
2637	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2638	0f8a249a	blueswir1	break;
2639	1f587329	blueswir1	case 0xb: /* V9 fabsq */
2640	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2641	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2642	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_fabsq);
2643	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2644	1f587329	blueswir1	break;
2645	0f8a249a	blueswir1	case 0x81: /* V9 fstox */
2646	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2647	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2648	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fstox);
2649	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2650	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2651	0f8a249a	blueswir1	break;
2652	0f8a249a	blueswir1	case 0x82: /* V9 fdtox */
2653	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2654	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2655	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fdtox);
2656	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2657	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2658	0f8a249a	blueswir1	break;
2659	1f587329	blueswir1	case 0x83: /* V9 fqtox */
2660	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2661	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2662	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2663	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fqtox);
2664	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2665	1f587329	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2666	1f587329	blueswir1	break;
2667	0f8a249a	blueswir1	case 0x84: /* V9 fxtos */
2668	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2669	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2670	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtos);
2671	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2672	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2673	0f8a249a	blueswir1	break;
2674	0f8a249a	blueswir1	case 0x88: /* V9 fxtod */
2675	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2676	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2677	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtod);
2678	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2679	0f8a249a	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2680	0f8a249a	blueswir1	break;
2681	0f8a249a	blueswir1	case 0x8c: /* V9 fxtoq */
2682	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2683	1f587329	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2684	7e8c2b6c	blueswir1	gen_clear_float_exceptions();
2685	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxtoq);
2686	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2687	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2688	1f587329	blueswir1	break;
2689	1f587329	blueswir1	#endif
2690	0f8a249a	blueswir1	default:
2691	0f8a249a	blueswir1	goto illegal_insn;
2692	0f8a249a	blueswir1	}
2693	0f8a249a	blueswir1	} else if (xop == 0x35) { /* FPU Operations */
2694	3475187d	bellard	#ifdef TARGET_SPARC64
2695	0f8a249a	blueswir1	int cond;
2696	3475187d	bellard	#endif
2697	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
2698	a80dde08	bellard	goto jmp_insn;
2699	0f8a249a	blueswir1	gen_op_clear_ieee_excp_and_FTT();
2700	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2701	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2702	0f8a249a	blueswir1	xop = GET_FIELD(insn, 18, 26);
2703	3475187d	bellard	#ifdef TARGET_SPARC64
2704	0f8a249a	blueswir1	if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2705	dcf24905	blueswir1	int l1;
2706	dcf24905	blueswir1
2707	dcf24905	blueswir1	l1 = gen_new_label();
2708	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2709	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2710	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2711	cb63669a	pbrook	0, l1);
2712	19f329ad	blueswir1	gen_op_load_fpr_FT0(rs2);
2713	0f8a249a	blueswir1	gen_op_store_FT0_fpr(rd);
2714	dcf24905	blueswir1	gen_set_label(l1);
2715	0f8a249a	blueswir1	break;
2716	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2717	dcf24905	blueswir1	int l1;
2718	dcf24905	blueswir1
2719	dcf24905	blueswir1	l1 = gen_new_label();
2720	0f8a249a	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2721	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2722	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2723	cb63669a	pbrook	0, l1);
2724	19f329ad	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
2725	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
2726	dcf24905	blueswir1	gen_set_label(l1);
2727	0f8a249a	blueswir1	break;
2728	0f8a249a	blueswir1	} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2729	dcf24905	blueswir1	int l1;
2730	dcf24905	blueswir1
2731	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2732	dcf24905	blueswir1	l1 = gen_new_label();
2733	1f587329	blueswir1	cond = GET_FIELD_SP(insn, 14, 17);
2734	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2735	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2736	cb63669a	pbrook	0, l1);
2737	19f329ad	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs2));
2738	1f587329	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
2739	dcf24905	blueswir1	gen_set_label(l1);
2740	1f587329	blueswir1	break;
2741	0f8a249a	blueswir1	}
2742	0f8a249a	blueswir1	#endif
2743	0f8a249a	blueswir1	switch (xop) {
2744	3475187d	bellard	#ifdef TARGET_SPARC64
2745	19f329ad	blueswir1	#define FMOVCC(size_FDQ, fcc) \
2746	19f329ad	blueswir1	{ \
2747	0425bee5	blueswir1	TCGv r_cond; \
2748	19f329ad	blueswir1	int l1; \
2749	19f329ad	blueswir1	\
2750	19f329ad	blueswir1	l1 = gen_new_label(); \
2751	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2752	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2753	19f329ad	blueswir1	gen_fcond(r_cond, fcc, cond); \
2754	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2755	cb63669a	pbrook	0, l1); \
2756	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2757	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2758	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2759	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2760	19f329ad	blueswir1	gen_set_label(l1); \
2761	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2762	19f329ad	blueswir1	}
2763	0f8a249a	blueswir1	case 0x001: /* V9 fmovscc %fcc0 */
2764	19f329ad	blueswir1	FMOVCC(F, 0);
2765	0f8a249a	blueswir1	break;
2766	0f8a249a	blueswir1	case 0x002: /* V9 fmovdcc %fcc0 */
2767	19f329ad	blueswir1	FMOVCC(D, 0);
2768	0f8a249a	blueswir1	break;
2769	0f8a249a	blueswir1	case 0x003: /* V9 fmovqcc %fcc0 */
2770	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2771	19f329ad	blueswir1	FMOVCC(Q, 0);
2772	1f587329	blueswir1	break;
2773	0f8a249a	blueswir1	case 0x041: /* V9 fmovscc %fcc1 */
2774	19f329ad	blueswir1	FMOVCC(F, 1);
2775	0f8a249a	blueswir1	break;
2776	0f8a249a	blueswir1	case 0x042: /* V9 fmovdcc %fcc1 */
2777	19f329ad	blueswir1	FMOVCC(D, 1);
2778	0f8a249a	blueswir1	break;
2779	0f8a249a	blueswir1	case 0x043: /* V9 fmovqcc %fcc1 */
2780	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2781	19f329ad	blueswir1	FMOVCC(Q, 1);
2782	1f587329	blueswir1	break;
2783	0f8a249a	blueswir1	case 0x081: /* V9 fmovscc %fcc2 */
2784	19f329ad	blueswir1	FMOVCC(F, 2);
2785	0f8a249a	blueswir1	break;
2786	0f8a249a	blueswir1	case 0x082: /* V9 fmovdcc %fcc2 */
2787	19f329ad	blueswir1	FMOVCC(D, 2);
2788	0f8a249a	blueswir1	break;
2789	0f8a249a	blueswir1	case 0x083: /* V9 fmovqcc %fcc2 */
2790	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2791	19f329ad	blueswir1	FMOVCC(Q, 2);
2792	1f587329	blueswir1	break;
2793	0f8a249a	blueswir1	case 0x0c1: /* V9 fmovscc %fcc3 */
2794	19f329ad	blueswir1	FMOVCC(F, 3);
2795	0f8a249a	blueswir1	break;
2796	0f8a249a	blueswir1	case 0x0c2: /* V9 fmovdcc %fcc3 */
2797	19f329ad	blueswir1	FMOVCC(D, 3);
2798	0f8a249a	blueswir1	break;
2799	0f8a249a	blueswir1	case 0x0c3: /* V9 fmovqcc %fcc3 */
2800	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2801	19f329ad	blueswir1	FMOVCC(Q, 3);
2802	1f587329	blueswir1	break;
2803	19f329ad	blueswir1	#undef FMOVCC
2804	19f329ad	blueswir1	#define FMOVCC(size_FDQ, icc) \
2805	19f329ad	blueswir1	{ \
2806	0425bee5	blueswir1	TCGv r_cond; \
2807	19f329ad	blueswir1	int l1; \
2808	19f329ad	blueswir1	\
2809	19f329ad	blueswir1	l1 = gen_new_label(); \
2810	19f329ad	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL); \
2811	19f329ad	blueswir1	cond = GET_FIELD_SP(insn, 14, 17); \
2812	19f329ad	blueswir1	gen_cond(r_cond, icc, cond); \
2813	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2814	cb63669a	pbrook	0, l1); \
2815	77f193da	blueswir1	glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2816	77f193da	blueswir1	(glue(size_FDQ, FPREG(rs2))); \
2817	77f193da	blueswir1	glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2818	77f193da	blueswir1	(glue(size_FDQ, FPREG(rd))); \
2819	19f329ad	blueswir1	gen_set_label(l1); \
2820	2ea815ca	blueswir1	tcg_temp_free(r_cond); \
2821	19f329ad	blueswir1	}
2822	19f329ad	blueswir1
2823	0f8a249a	blueswir1	case 0x101: /* V9 fmovscc %icc */
2824	19f329ad	blueswir1	FMOVCC(F, 0);
2825	0f8a249a	blueswir1	break;
2826	0f8a249a	blueswir1	case 0x102: /* V9 fmovdcc %icc */
2827	19f329ad	blueswir1	FMOVCC(D, 0);
2828	0f8a249a	blueswir1	case 0x103: /* V9 fmovqcc %icc */
2829	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2830	64a88d5d	blueswir1	FMOVCC(Q, 0);
2831	1f587329	blueswir1	break;
2832	0f8a249a	blueswir1	case 0x181: /* V9 fmovscc %xcc */
2833	19f329ad	blueswir1	FMOVCC(F, 1);
2834	0f8a249a	blueswir1	break;
2835	0f8a249a	blueswir1	case 0x182: /* V9 fmovdcc %xcc */
2836	19f329ad	blueswir1	FMOVCC(D, 1);
2837	0f8a249a	blueswir1	break;
2838	0f8a249a	blueswir1	case 0x183: /* V9 fmovqcc %xcc */
2839	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2840	19f329ad	blueswir1	FMOVCC(Q, 1);
2841	1f587329	blueswir1	break;
2842	19f329ad	blueswir1	#undef FMOVCC
2843	1f587329	blueswir1	#endif
2844	1f587329	blueswir1	case 0x51: /* fcmps, V9 %fcc */
2845	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2846	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2847	7e8c2b6c	blueswir1	gen_op_fcmps(rd & 3);
2848	0f8a249a	blueswir1	break;
2849	1f587329	blueswir1	case 0x52: /* fcmpd, V9 %fcc */
2850	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2851	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2852	7e8c2b6c	blueswir1	gen_op_fcmpd(rd & 3);
2853	0f8a249a	blueswir1	break;
2854	1f587329	blueswir1	case 0x53: /* fcmpq, V9 %fcc */
2855	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2856	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2857	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2858	7e8c2b6c	blueswir1	gen_op_fcmpq(rd & 3);
2859	1f587329	blueswir1	break;
2860	0f8a249a	blueswir1	case 0x55: /* fcmpes, V9 %fcc */
2861	0f8a249a	blueswir1	gen_op_load_fpr_FT0(rs1);
2862	0f8a249a	blueswir1	gen_op_load_fpr_FT1(rs2);
2863	7e8c2b6c	blueswir1	gen_op_fcmpes(rd & 3);
2864	0f8a249a	blueswir1	break;
2865	0f8a249a	blueswir1	case 0x56: /* fcmped, V9 %fcc */
2866	0f8a249a	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
2867	0f8a249a	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
2868	7e8c2b6c	blueswir1	gen_op_fcmped(rd & 3);
2869	0f8a249a	blueswir1	break;
2870	1f587329	blueswir1	case 0x57: /* fcmpeq, V9 %fcc */
2871	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
2872	1f587329	blueswir1	gen_op_load_fpr_QT0(QFPREG(rs1));
2873	1f587329	blueswir1	gen_op_load_fpr_QT1(QFPREG(rs2));
2874	7e8c2b6c	blueswir1	gen_op_fcmpeq(rd & 3);
2875	1f587329	blueswir1	break;
2876	0f8a249a	blueswir1	default:
2877	0f8a249a	blueswir1	goto illegal_insn;
2878	0f8a249a	blueswir1	}
2879	0f8a249a	blueswir1	} else if (xop == 0x2) {
2880	0f8a249a	blueswir1	// clr/mov shortcut
2881	e80cfcfc	bellard
2882	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
2883	0f8a249a	blueswir1	if (rs1 == 0) {
2884	1a2fb1c0	blueswir1	// or %g0, x, y -> mov T0, x; mov y, T0
2885	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2886	2ea815ca	blueswir1	TCGv r_const;
2887	2ea815ca	blueswir1
2888	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2889	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
2890	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
2891	2ea815ca	blueswir1	tcg_temp_free(r_const);
2892	0f8a249a	blueswir1	} else { /* register */
2893	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2894	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_dst);
2895	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2896	0f8a249a	blueswir1	}
2897	0f8a249a	blueswir1	} else {
2898	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2899	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2900	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
2901	6ae20372	blueswir1	tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2902	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2903	0f8a249a	blueswir1	} else { /* register */
2904	0f8a249a	blueswir1	// or x, %g0, y -> mov T1, x; mov y, T1
2905	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2906	0f8a249a	blueswir1	if (rs2 != 0) {
2907	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2908	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2909	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2910	6f551262	blueswir1	} else
2911	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_src1);
2912	0f8a249a	blueswir1	}
2913	0f8a249a	blueswir1	}
2914	83469015	bellard	#ifdef TARGET_SPARC64
2915	0f8a249a	blueswir1	} else if (xop == 0x25) { /* sll, V9 sllx */
2916	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2917	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2918	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2919	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2920	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2921	1a2fb1c0	blueswir1	} else {
2922	01b1fa6d	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
2923	1a2fb1c0	blueswir1	}
2924	0f8a249a	blueswir1	} else { /* register */
2925	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2926	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2927	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2928	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2929	1a2fb1c0	blueswir1	} else {
2930	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2931	1a2fb1c0	blueswir1	}
2932	01b1fa6d	blueswir1	tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2933	83469015	bellard	}
2934	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2935	0f8a249a	blueswir1	} else if (xop == 0x26) { /* srl, V9 srlx */
2936	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2937	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2938	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2939	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2940	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2941	1a2fb1c0	blueswir1	} else {
2942	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2943	6ae20372	blueswir1	tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2944	1a2fb1c0	blueswir1	}
2945	0f8a249a	blueswir1	} else { /* register */
2946	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2947	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2948	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2949	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2950	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2951	1a2fb1c0	blueswir1	} else {
2952	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2953	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2954	6ae20372	blueswir1	tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2955	1a2fb1c0	blueswir1	}
2956	83469015	bellard	}
2957	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2958	0f8a249a	blueswir1	} else if (xop == 0x27) { /* sra, V9 srax */
2959	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2960	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
2961	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
2962	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2963	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2964	1a2fb1c0	blueswir1	} else {
2965	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2966	6ae20372	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2967	6ae20372	blueswir1	tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2968	1a2fb1c0	blueswir1	}
2969	0f8a249a	blueswir1	} else { /* register */
2970	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
2971	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
2972	1a2fb1c0	blueswir1	if (insn & (1 << 12)) {
2973	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2974	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2975	1a2fb1c0	blueswir1	} else {
2976	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2977	6ae20372	blueswir1	tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2978	01b1fa6d	blueswir1	tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2979	6ae20372	blueswir1	tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2980	1a2fb1c0	blueswir1	}
2981	83469015	bellard	}
2982	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
2983	83469015	bellard	#endif
2984	fcc72045	blueswir1	} else if (xop < 0x36) {
2985	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
2986	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
2987	cf495bcf	bellard	if (xop < 0x20) {
2988	cf495bcf	bellard	switch (xop & ~0x10) {
2989	cf495bcf	bellard	case 0x0:
2990	cf495bcf	bellard	if (xop & 0x10)
2991	6ae20372	blueswir1	gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2992	cf495bcf	bellard	else
2993	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2994	cf495bcf	bellard	break;
2995	cf495bcf	bellard	case 0x1:
2996	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2997	cf495bcf	bellard	if (xop & 0x10)
2998	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
2999	cf495bcf	bellard	break;
3000	cf495bcf	bellard	case 0x2:
3001	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3002	0f8a249a	blueswir1	if (xop & 0x10)
3003	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3004	0f8a249a	blueswir1	break;
3005	cf495bcf	bellard	case 0x3:
3006	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3007	cf495bcf	bellard	if (xop & 0x10)
3008	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3009	cf495bcf	bellard	break;
3010	cf495bcf	bellard	case 0x4:
3011	cf495bcf	bellard	if (xop & 0x10)
3012	6ae20372	blueswir1	gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3013	cf495bcf	bellard	else
3014	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3015	cf495bcf	bellard	break;
3016	cf495bcf	bellard	case 0x5:
3017	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3018	6ae20372	blueswir1	tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3019	cf495bcf	bellard	if (xop & 0x10)
3020	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3021	cf495bcf	bellard	break;
3022	cf495bcf	bellard	case 0x6:
3023	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3024	6ae20372	blueswir1	tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3025	cf495bcf	bellard	if (xop & 0x10)
3026	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3027	cf495bcf	bellard	break;
3028	cf495bcf	bellard	case 0x7:
3029	6ae20372	blueswir1	tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3030	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3031	cf495bcf	bellard	if (xop & 0x10)
3032	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3033	cf495bcf	bellard	break;
3034	cf495bcf	bellard	case 0x8:
3035	cf495bcf	bellard	if (xop & 0x10)
3036	6ae20372	blueswir1	gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3037	38bc628b	blueswir1	else {
3038	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3039	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3040	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3041	38bc628b	blueswir1	}
3042	cf495bcf	bellard	break;
3043	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3044	0f8a249a	blueswir1	case 0x9: /* V9 mulx */
3045	6ae20372	blueswir1	tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3046	ded3ab80	pbrook	break;
3047	ded3ab80	pbrook	#endif
3048	cf495bcf	bellard	case 0xa:
3049	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3050	6ae20372	blueswir1	gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3051	cf495bcf	bellard	if (xop & 0x10)
3052	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3053	cf495bcf	bellard	break;
3054	cf495bcf	bellard	case 0xb:
3055	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, MUL);
3056	6ae20372	blueswir1	gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3057	cf495bcf	bellard	if (xop & 0x10)
3058	6ae20372	blueswir1	gen_op_logic_cc(cpu_dst);
3059	cf495bcf	bellard	break;
3060	cf495bcf	bellard	case 0xc:
3061	cf495bcf	bellard	if (xop & 0x10)
3062	6ae20372	blueswir1	gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3063	38bc628b	blueswir1	else {
3064	dc99a3f2	blueswir1	gen_mov_reg_C(cpu_tmp0, cpu_psr);
3065	6ae20372	blueswir1	tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3066	6ae20372	blueswir1	tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3067	38bc628b	blueswir1	}
3068	cf495bcf	bellard	break;
3069	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3070	0f8a249a	blueswir1	case 0xd: /* V9 udivx */
3071	07bf2857	blueswir1	tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3072	07bf2857	blueswir1	tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3073	07bf2857	blueswir1	gen_trap_ifdivzero_tl(cpu_cc_src2);
3074	07bf2857	blueswir1	tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3075	ded3ab80	pbrook	break;
3076	ded3ab80	pbrook	#endif
3077	cf495bcf	bellard	case 0xe:
3078	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3079	77f193da	blueswir1	tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3080	77f193da	blueswir1	cpu_src2);
3081	cf495bcf	bellard	if (xop & 0x10)
3082	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3083	cf495bcf	bellard	break;
3084	cf495bcf	bellard	case 0xf:
3085	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, DIV);
3086	77f193da	blueswir1	tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3087	77f193da	blueswir1	cpu_src2);
3088	cf495bcf	bellard	if (xop & 0x10)
3089	6ae20372	blueswir1	gen_op_div_cc(cpu_dst);
3090	cf495bcf	bellard	break;
3091	cf495bcf	bellard	default:
3092	cf495bcf	bellard	goto illegal_insn;
3093	cf495bcf	bellard	}
3094	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3095	cf495bcf	bellard	} else {
3096	cf495bcf	bellard	switch (xop) {
3097	0f8a249a	blueswir1	case 0x20: /* taddcc */
3098	6ae20372	blueswir1	gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3099	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3100	0f8a249a	blueswir1	break;
3101	0f8a249a	blueswir1	case 0x21: /* tsubcc */
3102	6ae20372	blueswir1	gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3103	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3104	0f8a249a	blueswir1	break;
3105	0f8a249a	blueswir1	case 0x22: /* taddcctv */
3106	6ae20372	blueswir1	save_state(dc, cpu_cond);
3107	6ae20372	blueswir1	gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3108	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3109	0f8a249a	blueswir1	break;
3110	0f8a249a	blueswir1	case 0x23: /* tsubcctv */
3111	6ae20372	blueswir1	save_state(dc, cpu_cond);
3112	6ae20372	blueswir1	gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3113	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3114	0f8a249a	blueswir1	break;
3115	cf495bcf	bellard	case 0x24: /* mulscc */
3116	6ae20372	blueswir1	gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3117	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3118	cf495bcf	bellard	break;
3119	83469015	bellard	#ifndef TARGET_SPARC64
3120	0f8a249a	blueswir1	case 0x25: /* sll */
3121	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3122	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3123	e35298cd	blueswir1	tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3124	e35298cd	blueswir1	} else { /* register */
3125	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3126	e35298cd	blueswir1	tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3127	e35298cd	blueswir1	}
3128	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3129	cf495bcf	bellard	break;
3130	83469015	bellard	case 0x26: /* srl */
3131	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3132	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3133	e35298cd	blueswir1	tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3134	e35298cd	blueswir1	} else { /* register */
3135	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3136	e35298cd	blueswir1	tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3137	e35298cd	blueswir1	}
3138	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3139	cf495bcf	bellard	break;
3140	83469015	bellard	case 0x27: /* sra */
3141	e35298cd	blueswir1	if (IS_IMM) { /* immediate */
3142	e35298cd	blueswir1	rs2 = GET_FIELDs(insn, 20, 31);
3143	e35298cd	blueswir1	tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3144	e35298cd	blueswir1	} else { /* register */
3145	e35298cd	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3146	e35298cd	blueswir1	tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3147	e35298cd	blueswir1	}
3148	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3149	cf495bcf	bellard	break;
3150	83469015	bellard	#endif
3151	cf495bcf	bellard	case 0x30:
3152	cf495bcf	bellard	{
3153	cf495bcf	bellard	switch(rd) {
3154	3475187d	bellard	case 0: /* wry */
3155	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3156	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3157	77f193da	blueswir1	offsetof(CPUSPARCState, y));
3158	cf495bcf	bellard	break;
3159	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
3160	65fe7b09	blueswir1	case 0x01 ... 0x0f: /* undefined in the
3161	65fe7b09	blueswir1	SPARCv8 manual, nop
3162	65fe7b09	blueswir1	on the microSPARC
3163	65fe7b09	blueswir1	II */
3164	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent
3165	65fe7b09	blueswir1	in the SPARCv8
3166	65fe7b09	blueswir1	manual, nop on the
3167	65fe7b09	blueswir1	microSPARC II */
3168	65fe7b09	blueswir1	break;
3169	65fe7b09	blueswir1	#else
3170	0f8a249a	blueswir1	case 0x2: /* V9 wrccr */
3171	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3172	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3173	0f8a249a	blueswir1	break;
3174	0f8a249a	blueswir1	case 0x3: /* V9 wrasi */
3175	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3176	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3177	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3178	77f193da	blueswir1	offsetof(CPUSPARCState, asi));
3179	0f8a249a	blueswir1	break;
3180	0f8a249a	blueswir1	case 0x6: /* V9 wrfprs */
3181	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3182	6ae20372	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3183	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3184	77f193da	blueswir1	offsetof(CPUSPARCState, fprs));
3185	6ae20372	blueswir1	save_state(dc, cpu_cond);
3186	3299908c	blueswir1	gen_op_next_insn();
3187	57fec1fe	bellard	tcg_gen_exit_tb(0);
3188	3299908c	blueswir1	dc->is_br = 1;
3189	0f8a249a	blueswir1	break;
3190	0f8a249a	blueswir1	case 0xf: /* V9 sir, nop if user */
3191	3475187d	bellard	#if !defined(CONFIG_USER_ONLY)
3192	0f8a249a	blueswir1	if (supervisor(dc))
3193	1a2fb1c0	blueswir1	; // XXX
3194	3475187d	bellard	#endif
3195	0f8a249a	blueswir1	break;
3196	0f8a249a	blueswir1	case 0x13: /* Graphics Status */
3197	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3198	725cb90b	bellard	goto jmp_insn;
3199	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3200	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3201	77f193da	blueswir1	offsetof(CPUSPARCState, gsr));
3202	0f8a249a	blueswir1	break;
3203	0f8a249a	blueswir1	case 0x17: /* Tick compare */
3204	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3205	0f8a249a	blueswir1	if (!supervisor(dc))
3206	0f8a249a	blueswir1	goto illegal_insn;
3207	83469015	bellard	#endif
3208	ccd4a219	blueswir1	{
3209	ccd4a219	blueswir1	TCGv r_tickptr;
3210	ccd4a219	blueswir1
3211	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3212	6ae20372	blueswir1	cpu_src2);
3213	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3214	77f193da	blueswir1	offsetof(CPUSPARCState,
3215	77f193da	blueswir1	tick_cmpr));
3216	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3217	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3218	ccd4a219	blueswir1	offsetof(CPUState, tick));
3219	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3220	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3221	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3222	ccd4a219	blueswir1	}
3223	0f8a249a	blueswir1	break;
3224	0f8a249a	blueswir1	case 0x18: /* System tick */
3225	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3226	0f8a249a	blueswir1	if (!supervisor(dc))
3227	0f8a249a	blueswir1	goto illegal_insn;
3228	83469015	bellard	#endif
3229	ccd4a219	blueswir1	{
3230	ccd4a219	blueswir1	TCGv r_tickptr;
3231	ccd4a219	blueswir1
3232	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1,
3233	6ae20372	blueswir1	cpu_src2);
3234	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3235	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3236	ccd4a219	blueswir1	offsetof(CPUState, stick));
3237	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3238	6ae20372	blueswir1	r_tickptr, cpu_dst);
3239	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3240	ccd4a219	blueswir1	}
3241	0f8a249a	blueswir1	break;
3242	0f8a249a	blueswir1	case 0x19: /* System tick compare */
3243	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
3244	0f8a249a	blueswir1	if (!supervisor(dc))
3245	0f8a249a	blueswir1	goto illegal_insn;
3246	3475187d	bellard	#endif
3247	ccd4a219	blueswir1	{
3248	ccd4a219	blueswir1	TCGv r_tickptr;
3249	ccd4a219	blueswir1
3250	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3251	6ae20372	blueswir1	cpu_src2);
3252	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3253	77f193da	blueswir1	offsetof(CPUSPARCState,
3254	77f193da	blueswir1	stick_cmpr));
3255	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3256	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3257	ccd4a219	blueswir1	offsetof(CPUState, stick));
3258	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3259	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3260	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3261	ccd4a219	blueswir1	}
3262	0f8a249a	blueswir1	break;
3263	83469015	bellard
3264	0f8a249a	blueswir1	case 0x10: /* Performance Control */
3265	77f193da	blueswir1	case 0x11: /* Performance Instrumentation
3266	77f193da	blueswir1	Counter */
3267	0f8a249a	blueswir1	case 0x12: /* Dispatch Control */
3268	0f8a249a	blueswir1	case 0x14: /* Softint set */
3269	0f8a249a	blueswir1	case 0x15: /* Softint clear */
3270	0f8a249a	blueswir1	case 0x16: /* Softint write */
3271	83469015	bellard	#endif
3272	3475187d	bellard	default:
3273	cf495bcf	bellard	goto illegal_insn;
3274	cf495bcf	bellard	}
3275	cf495bcf	bellard	}
3276	cf495bcf	bellard	break;
3277	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
3278	af7bf89b	bellard	case 0x31: /* wrpsr, V9 saved, restored */
3279	e8af50a3	bellard	{
3280	0f8a249a	blueswir1	if (!supervisor(dc))
3281	0f8a249a	blueswir1	goto priv_insn;
3282	3475187d	bellard	#ifdef TARGET_SPARC64
3283	0f8a249a	blueswir1	switch (rd) {
3284	0f8a249a	blueswir1	case 0:
3285	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_saved);
3286	0f8a249a	blueswir1	break;
3287	0f8a249a	blueswir1	case 1:
3288	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restored);
3289	0f8a249a	blueswir1	break;
3290	e9ebed4d	blueswir1	case 2: /* UA2005 allclean */
3291	e9ebed4d	blueswir1	case 3: /* UA2005 otherw */
3292	e9ebed4d	blueswir1	case 4: /* UA2005 normalw */
3293	e9ebed4d	blueswir1	case 5: /* UA2005 invalw */
3294	e9ebed4d	blueswir1	// XXX
3295	0f8a249a	blueswir1	default:
3296	3475187d	bellard	goto illegal_insn;
3297	3475187d	bellard	}
3298	3475187d	bellard	#else
3299	6ae20372	blueswir1	tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3300	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3301	6ae20372	blueswir1	save_state(dc, cpu_cond);
3302	9e61bde5	bellard	gen_op_next_insn();
3303	57fec1fe	bellard	tcg_gen_exit_tb(0);
3304	0f8a249a	blueswir1	dc->is_br = 1;
3305	3475187d	bellard	#endif
3306	e8af50a3	bellard	}
3307	e8af50a3	bellard	break;
3308	af7bf89b	bellard	case 0x32: /* wrwim, V9 wrpr */
3309	e8af50a3	bellard	{
3310	0f8a249a	blueswir1	if (!supervisor(dc))
3311	0f8a249a	blueswir1	goto priv_insn;
3312	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3313	3475187d	bellard	#ifdef TARGET_SPARC64
3314	0f8a249a	blueswir1	switch (rd) {
3315	0f8a249a	blueswir1	case 0: // tpc
3316	375ee38b	blueswir1	{
3317	375ee38b	blueswir1	TCGv r_tsptr;
3318	375ee38b	blueswir1
3319	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3320	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3321	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3322	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3323	375ee38b	blueswir1	offsetof(trap_state, tpc));
3324	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3325	375ee38b	blueswir1	}
3326	0f8a249a	blueswir1	break;
3327	0f8a249a	blueswir1	case 1: // tnpc
3328	375ee38b	blueswir1	{
3329	375ee38b	blueswir1	TCGv r_tsptr;
3330	375ee38b	blueswir1
3331	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3332	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3333	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3334	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3335	375ee38b	blueswir1	offsetof(trap_state, tnpc));
3336	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3337	375ee38b	blueswir1	}
3338	0f8a249a	blueswir1	break;
3339	0f8a249a	blueswir1	case 2: // tstate
3340	375ee38b	blueswir1	{
3341	375ee38b	blueswir1	TCGv r_tsptr;
3342	375ee38b	blueswir1
3343	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3344	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3345	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3346	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3347	77f193da	blueswir1	offsetof(trap_state,
3348	77f193da	blueswir1	tstate));
3349	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3350	375ee38b	blueswir1	}
3351	0f8a249a	blueswir1	break;
3352	0f8a249a	blueswir1	case 3: // tt
3353	375ee38b	blueswir1	{
3354	375ee38b	blueswir1	TCGv r_tsptr;
3355	375ee38b	blueswir1
3356	375ee38b	blueswir1	r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3357	375ee38b	blueswir1	tcg_gen_ld_ptr(r_tsptr, cpu_env,
3358	375ee38b	blueswir1	offsetof(CPUState, tsptr));
3359	ece43b8d	blueswir1	tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3360	375ee38b	blueswir1	offsetof(trap_state, tt));
3361	2ea815ca	blueswir1	tcg_temp_free(r_tsptr);
3362	375ee38b	blueswir1	}
3363	0f8a249a	blueswir1	break;
3364	0f8a249a	blueswir1	case 4: // tick
3365	ccd4a219	blueswir1	{
3366	ccd4a219	blueswir1	TCGv r_tickptr;
3367	ccd4a219	blueswir1
3368	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3369	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3370	ccd4a219	blueswir1	offsetof(CPUState, tick));
3371	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_count,
3372	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3373	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3374	ccd4a219	blueswir1	}
3375	0f8a249a	blueswir1	break;
3376	0f8a249a	blueswir1	case 5: // tba
3377	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3378	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3379	0f8a249a	blueswir1	break;
3380	0f8a249a	blueswir1	case 6: // pstate
3381	6ae20372	blueswir1	save_state(dc, cpu_cond);
3382	ece43b8d	blueswir1	tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3383	ded3ab80	pbrook	gen_op_next_insn();
3384	57fec1fe	bellard	tcg_gen_exit_tb(0);
3385	ded3ab80	pbrook	dc->is_br = 1;
3386	0f8a249a	blueswir1	break;
3387	0f8a249a	blueswir1	case 7: // tl
3388	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3389	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3390	77f193da	blueswir1	offsetof(CPUSPARCState, tl));
3391	0f8a249a	blueswir1	break;
3392	0f8a249a	blueswir1	case 8: // pil
3393	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3394	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3395	77f193da	blueswir1	offsetof(CPUSPARCState,
3396	77f193da	blueswir1	psrpil));
3397	0f8a249a	blueswir1	break;
3398	0f8a249a	blueswir1	case 9: // cwp
3399	ece43b8d	blueswir1	tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3400	0f8a249a	blueswir1	break;
3401	0f8a249a	blueswir1	case 10: // cansave
3402	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3403	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3404	77f193da	blueswir1	offsetof(CPUSPARCState,
3405	77f193da	blueswir1	cansave));
3406	0f8a249a	blueswir1	break;
3407	0f8a249a	blueswir1	case 11: // canrestore
3408	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3409	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3410	77f193da	blueswir1	offsetof(CPUSPARCState,
3411	77f193da	blueswir1	canrestore));
3412	0f8a249a	blueswir1	break;
3413	0f8a249a	blueswir1	case 12: // cleanwin
3414	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3415	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3416	77f193da	blueswir1	offsetof(CPUSPARCState,
3417	77f193da	blueswir1	cleanwin));
3418	0f8a249a	blueswir1	break;
3419	0f8a249a	blueswir1	case 13: // otherwin
3420	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3421	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3422	77f193da	blueswir1	offsetof(CPUSPARCState,
3423	77f193da	blueswir1	otherwin));
3424	0f8a249a	blueswir1	break;
3425	0f8a249a	blueswir1	case 14: // wstate
3426	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3427	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3428	77f193da	blueswir1	offsetof(CPUSPARCState,
3429	77f193da	blueswir1	wstate));
3430	0f8a249a	blueswir1	break;
3431	e9ebed4d	blueswir1	case 16: // UA2005 gl
3432	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, GL);
3433	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3434	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3435	77f193da	blueswir1	offsetof(CPUSPARCState, gl));
3436	e9ebed4d	blueswir1	break;
3437	e9ebed4d	blueswir1	case 26: // UA2005 strand status
3438	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
3439	e9ebed4d	blueswir1	if (!hypervisor(dc))
3440	e9ebed4d	blueswir1	goto priv_insn;
3441	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3442	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3443	77f193da	blueswir1	offsetof(CPUSPARCState, ssr));
3444	e9ebed4d	blueswir1	break;
3445	0f8a249a	blueswir1	default:
3446	0f8a249a	blueswir1	goto illegal_insn;
3447	0f8a249a	blueswir1	}
3448	3475187d	bellard	#else
3449	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3450	c93e7817	blueswir1	if (dc->def->nwindows != 32)
3451	c93e7817	blueswir1	tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3452	c93e7817	blueswir1	(1 << dc->def->nwindows) - 1);
3453	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3454	77f193da	blueswir1	offsetof(CPUSPARCState, wim));
3455	3475187d	bellard	#endif
3456	e8af50a3	bellard	}
3457	e8af50a3	bellard	break;
3458	e9ebed4d	blueswir1	case 0x33: /* wrtbr, UA2005 wrhpr */
3459	e8af50a3	bellard	{
3460	e9ebed4d	blueswir1	#ifndef TARGET_SPARC64
3461	0f8a249a	blueswir1	if (!supervisor(dc))
3462	0f8a249a	blueswir1	goto priv_insn;
3463	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3464	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3465	77f193da	blueswir1	offsetof(CPUSPARCState, tbr));
3466	e9ebed4d	blueswir1	#else
3467	fb79ceb9	blueswir1	CHECK_IU_FEATURE(dc, HYPV);
3468	e9ebed4d	blueswir1	if (!hypervisor(dc))
3469	e9ebed4d	blueswir1	goto priv_insn;
3470	ece43b8d	blueswir1	tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3471	e9ebed4d	blueswir1	switch (rd) {
3472	e9ebed4d	blueswir1	case 0: // hpstate
3473	e9ebed4d	blueswir1	// XXX gen_op_wrhpstate();
3474	6ae20372	blueswir1	save_state(dc, cpu_cond);
3475	e9ebed4d	blueswir1	gen_op_next_insn();
3476	57fec1fe	bellard	tcg_gen_exit_tb(0);
3477	e9ebed4d	blueswir1	dc->is_br = 1;
3478	e9ebed4d	blueswir1	break;
3479	e9ebed4d	blueswir1	case 1: // htstate
3480	e9ebed4d	blueswir1	// XXX gen_op_wrhtstate();
3481	e9ebed4d	blueswir1	break;
3482	e9ebed4d	blueswir1	case 3: // hintp
3483	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3484	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3485	77f193da	blueswir1	offsetof(CPUSPARCState, hintp));
3486	e9ebed4d	blueswir1	break;
3487	e9ebed4d	blueswir1	case 5: // htba
3488	ece43b8d	blueswir1	tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3489	77f193da	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
3490	77f193da	blueswir1	offsetof(CPUSPARCState, htba));
3491	e9ebed4d	blueswir1	break;
3492	e9ebed4d	blueswir1	case 31: // hstick_cmpr
3493	ccd4a219	blueswir1	{
3494	ccd4a219	blueswir1	TCGv r_tickptr;
3495	ccd4a219	blueswir1
3496	ece43b8d	blueswir1	tcg_gen_st_tl(cpu_tmp0, cpu_env,
3497	77f193da	blueswir1	offsetof(CPUSPARCState,
3498	77f193da	blueswir1	hstick_cmpr));
3499	ccd4a219	blueswir1	r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3500	ccd4a219	blueswir1	tcg_gen_ld_ptr(r_tickptr, cpu_env,
3501	ccd4a219	blueswir1	offsetof(CPUState, hstick));
3502	ccd4a219	blueswir1	tcg_gen_helper_0_2(helper_tick_set_limit,
3503	ece43b8d	blueswir1	r_tickptr, cpu_tmp0);
3504	2ea815ca	blueswir1	tcg_temp_free(r_tickptr);
3505	ccd4a219	blueswir1	}
3506	e9ebed4d	blueswir1	break;
3507	e9ebed4d	blueswir1	case 6: // hver readonly
3508	e9ebed4d	blueswir1	default:
3509	e9ebed4d	blueswir1	goto illegal_insn;
3510	e9ebed4d	blueswir1	}
3511	e9ebed4d	blueswir1	#endif
3512	e8af50a3	bellard	}
3513	e8af50a3	bellard	break;
3514	e8af50a3	bellard	#endif
3515	3475187d	bellard	#ifdef TARGET_SPARC64
3516	0f8a249a	blueswir1	case 0x2c: /* V9 movcc */
3517	0f8a249a	blueswir1	{
3518	0f8a249a	blueswir1	int cc = GET_FIELD_SP(insn, 11, 12);
3519	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 14, 17);
3520	748b9d8e	blueswir1	TCGv r_cond;
3521	00f219bf	blueswir1	int l1;
3522	00f219bf	blueswir1
3523	748b9d8e	blueswir1	r_cond = tcg_temp_new(TCG_TYPE_TL);
3524	0f8a249a	blueswir1	if (insn & (1 << 18)) {
3525	0f8a249a	blueswir1	if (cc == 0)
3526	748b9d8e	blueswir1	gen_cond(r_cond, 0, cond);
3527	0f8a249a	blueswir1	else if (cc == 2)
3528	748b9d8e	blueswir1	gen_cond(r_cond, 1, cond);
3529	0f8a249a	blueswir1	else
3530	0f8a249a	blueswir1	goto illegal_insn;
3531	0f8a249a	blueswir1	} else {
3532	748b9d8e	blueswir1	gen_fcond(r_cond, cc, cond);
3533	0f8a249a	blueswir1	}
3534	00f219bf	blueswir1
3535	00f219bf	blueswir1	l1 = gen_new_label();
3536	00f219bf	blueswir1
3537	cb63669a	pbrook	tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3538	00f219bf	blueswir1	if (IS_IMM) { /* immediate */
3539	2ea815ca	blueswir1	TCGv r_const;
3540	2ea815ca	blueswir1
3541	00f219bf	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 10);
3542	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3543	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3544	2ea815ca	blueswir1	tcg_temp_free(r_const);
3545	00f219bf	blueswir1	} else {
3546	00f219bf	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3547	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3548	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3549	00f219bf	blueswir1	}
3550	00f219bf	blueswir1	gen_set_label(l1);
3551	2ea815ca	blueswir1	tcg_temp_free(r_cond);
3552	0f8a249a	blueswir1	break;
3553	0f8a249a	blueswir1	}
3554	0f8a249a	blueswir1	case 0x2d: /* V9 sdivx */
3555	6ae20372	blueswir1	gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3556	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3557	0f8a249a	blueswir1	break;
3558	0f8a249a	blueswir1	case 0x2e: /* V9 popc */
3559	0f8a249a	blueswir1	{
3560	a49d9390	blueswir1	cpu_src2 = get_src2(insn, cpu_src2);
3561	6ae20372	blueswir1	tcg_gen_helper_1_1(helper_popc, cpu_dst,
3562	6ae20372	blueswir1	cpu_src2);
3563	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3564	0f8a249a	blueswir1	}
3565	0f8a249a	blueswir1	case 0x2f: /* V9 movr */
3566	0f8a249a	blueswir1	{
3567	0f8a249a	blueswir1	int cond = GET_FIELD_SP(insn, 10, 12);
3568	00f219bf	blueswir1	int l1;
3569	00f219bf	blueswir1
3570	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3571	00f219bf	blueswir1
3572	00f219bf	blueswir1	l1 = gen_new_label();
3573	00f219bf	blueswir1
3574	cb63669a	pbrook	tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3575	cb63669a	pbrook	cpu_src1, 0, l1);
3576	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
3577	2ea815ca	blueswir1	TCGv r_const;
3578	2ea815ca	blueswir1
3579	0f8a249a	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 9);
3580	2ea815ca	blueswir1	r_const = tcg_const_tl((int)rs2);
3581	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
3582	2ea815ca	blueswir1	tcg_temp_free(r_const);
3583	00f219bf	blueswir1	} else {
3584	0f8a249a	blueswir1	rs2 = GET_FIELD_SP(insn, 0, 4);
3585	9c6c6662	blueswir1	gen_movl_reg_TN(rs2, cpu_tmp0);
3586	9c6c6662	blueswir1	gen_movl_TN_reg(rd, cpu_tmp0);
3587	0f8a249a	blueswir1	}
3588	00f219bf	blueswir1	gen_set_label(l1);
3589	0f8a249a	blueswir1	break;
3590	0f8a249a	blueswir1	}
3591	0f8a249a	blueswir1	#endif
3592	0f8a249a	blueswir1	default:
3593	0f8a249a	blueswir1	goto illegal_insn;
3594	0f8a249a	blueswir1	}
3595	0f8a249a	blueswir1	}
3596	3299908c	blueswir1	} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3597	3299908c	blueswir1	#ifdef TARGET_SPARC64
3598	3299908c	blueswir1	int opf = GET_FIELD_SP(insn, 5, 13);
3599	3299908c	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
3600	3299908c	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
3601	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
3602	e9ebed4d	blueswir1	goto jmp_insn;
3603	3299908c	blueswir1
3604	3299908c	blueswir1	switch (opf) {
3605	e9ebed4d	blueswir1	case 0x000: /* VIS I edge8cc */
3606	e9ebed4d	blueswir1	case 0x001: /* VIS II edge8n */
3607	e9ebed4d	blueswir1	case 0x002: /* VIS I edge8lcc */
3608	e9ebed4d	blueswir1	case 0x003: /* VIS II edge8ln */
3609	e9ebed4d	blueswir1	case 0x004: /* VIS I edge16cc */
3610	e9ebed4d	blueswir1	case 0x005: /* VIS II edge16n */
3611	e9ebed4d	blueswir1	case 0x006: /* VIS I edge16lcc */
3612	e9ebed4d	blueswir1	case 0x007: /* VIS II edge16ln */
3613	e9ebed4d	blueswir1	case 0x008: /* VIS I edge32cc */
3614	e9ebed4d	blueswir1	case 0x009: /* VIS II edge32n */
3615	e9ebed4d	blueswir1	case 0x00a: /* VIS I edge32lcc */
3616	e9ebed4d	blueswir1	case 0x00b: /* VIS II edge32ln */
3617	e9ebed4d	blueswir1	// XXX
3618	e9ebed4d	blueswir1	goto illegal_insn;
3619	e9ebed4d	blueswir1	case 0x010: /* VIS I array8 */
3620	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3621	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3622	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3623	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3624	6ae20372	blueswir1	cpu_src2);
3625	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3626	e9ebed4d	blueswir1	break;
3627	e9ebed4d	blueswir1	case 0x012: /* VIS I array16 */
3628	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3629	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3630	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3631	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3632	6ae20372	blueswir1	cpu_src2);
3633	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3634	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3635	e9ebed4d	blueswir1	break;
3636	e9ebed4d	blueswir1	case 0x014: /* VIS I array32 */
3637	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3638	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3639	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3640	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3641	6ae20372	blueswir1	cpu_src2);
3642	6ae20372	blueswir1	tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3643	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3644	e9ebed4d	blueswir1	break;
3645	3299908c	blueswir1	case 0x018: /* VIS I alignaddr */
3646	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3647	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
3648	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
3649	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3650	6ae20372	blueswir1	cpu_src2);
3651	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
3652	3299908c	blueswir1	break;
3653	e9ebed4d	blueswir1	case 0x019: /* VIS II bmask */
3654	3299908c	blueswir1	case 0x01a: /* VIS I alignaddrl */
3655	3299908c	blueswir1	// XXX
3656	e9ebed4d	blueswir1	goto illegal_insn;
3657	e9ebed4d	blueswir1	case 0x020: /* VIS I fcmple16 */
3658	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3659	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3660	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3661	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple16);
3662	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3663	e9ebed4d	blueswir1	break;
3664	e9ebed4d	blueswir1	case 0x022: /* VIS I fcmpne16 */
3665	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3666	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3667	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3668	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne16);
3669	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3670	3299908c	blueswir1	break;
3671	e9ebed4d	blueswir1	case 0x024: /* VIS I fcmple32 */
3672	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3673	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3674	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3675	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmple32);
3676	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3677	e9ebed4d	blueswir1	break;
3678	e9ebed4d	blueswir1	case 0x026: /* VIS I fcmpne32 */
3679	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3680	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3681	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3682	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpne32);
3683	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3684	e9ebed4d	blueswir1	break;
3685	e9ebed4d	blueswir1	case 0x028: /* VIS I fcmpgt16 */
3686	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3687	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3688	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3689	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt16);
3690	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3691	e9ebed4d	blueswir1	break;
3692	e9ebed4d	blueswir1	case 0x02a: /* VIS I fcmpeq16 */
3693	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3694	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3695	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3696	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq16);
3697	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3698	e9ebed4d	blueswir1	break;
3699	e9ebed4d	blueswir1	case 0x02c: /* VIS I fcmpgt32 */
3700	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3701	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3702	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3703	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpgt32);
3704	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3705	e9ebed4d	blueswir1	break;
3706	e9ebed4d	blueswir1	case 0x02e: /* VIS I fcmpeq32 */
3707	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3708	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3709	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3710	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fcmpeq32);
3711	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3712	e9ebed4d	blueswir1	break;
3713	e9ebed4d	blueswir1	case 0x031: /* VIS I fmul8x16 */
3714	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3715	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3716	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3717	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16);
3718	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3719	e9ebed4d	blueswir1	break;
3720	e9ebed4d	blueswir1	case 0x033: /* VIS I fmul8x16au */
3721	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3722	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3723	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3724	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16au);
3725	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3726	e9ebed4d	blueswir1	break;
3727	e9ebed4d	blueswir1	case 0x035: /* VIS I fmul8x16al */
3728	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3729	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3730	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3731	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8x16al);
3732	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3733	e9ebed4d	blueswir1	break;
3734	e9ebed4d	blueswir1	case 0x036: /* VIS I fmul8sux16 */
3735	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3736	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3737	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3738	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8sux16);
3739	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3740	e9ebed4d	blueswir1	break;
3741	e9ebed4d	blueswir1	case 0x037: /* VIS I fmul8ulx16 */
3742	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3743	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3744	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3745	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmul8ulx16);
3746	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3747	e9ebed4d	blueswir1	break;
3748	e9ebed4d	blueswir1	case 0x038: /* VIS I fmuld8sux16 */
3749	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3750	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3751	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3752	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8sux16);
3753	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3754	e9ebed4d	blueswir1	break;
3755	e9ebed4d	blueswir1	case 0x039: /* VIS I fmuld8ulx16 */
3756	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3757	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3758	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3759	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fmuld8ulx16);
3760	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3761	e9ebed4d	blueswir1	break;
3762	e9ebed4d	blueswir1	case 0x03a: /* VIS I fpack32 */
3763	e9ebed4d	blueswir1	case 0x03b: /* VIS I fpack16 */
3764	e9ebed4d	blueswir1	case 0x03d: /* VIS I fpackfix */
3765	e9ebed4d	blueswir1	case 0x03e: /* VIS I pdist */
3766	e9ebed4d	blueswir1	// XXX
3767	e9ebed4d	blueswir1	goto illegal_insn;
3768	3299908c	blueswir1	case 0x048: /* VIS I faligndata */
3769	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3770	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3771	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3772	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_faligndata);
3773	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3774	3299908c	blueswir1	break;
3775	e9ebed4d	blueswir1	case 0x04b: /* VIS I fpmerge */
3776	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3777	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3778	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3779	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpmerge);
3780	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3781	e9ebed4d	blueswir1	break;
3782	e9ebed4d	blueswir1	case 0x04c: /* VIS II bshuffle */
3783	e9ebed4d	blueswir1	// XXX
3784	e9ebed4d	blueswir1	goto illegal_insn;
3785	e9ebed4d	blueswir1	case 0x04d: /* VIS I fexpand */
3786	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3787	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3788	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3789	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fexpand);
3790	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3791	e9ebed4d	blueswir1	break;
3792	e9ebed4d	blueswir1	case 0x050: /* VIS I fpadd16 */
3793	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3794	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3795	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3796	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16);
3797	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3798	e9ebed4d	blueswir1	break;
3799	e9ebed4d	blueswir1	case 0x051: /* VIS I fpadd16s */
3800	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3801	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3802	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3803	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd16s);
3804	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3805	e9ebed4d	blueswir1	break;
3806	e9ebed4d	blueswir1	case 0x052: /* VIS I fpadd32 */
3807	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3808	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3809	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3810	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3811	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3812	e9ebed4d	blueswir1	break;
3813	e9ebed4d	blueswir1	case 0x053: /* VIS I fpadd32s */
3814	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3815	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3816	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3817	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32s);
3818	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3819	e9ebed4d	blueswir1	break;
3820	e9ebed4d	blueswir1	case 0x054: /* VIS I fpsub16 */
3821	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3822	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3823	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3824	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16);
3825	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3826	e9ebed4d	blueswir1	break;
3827	e9ebed4d	blueswir1	case 0x055: /* VIS I fpsub16s */
3828	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3829	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3830	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3831	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub16s);
3832	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3833	e9ebed4d	blueswir1	break;
3834	e9ebed4d	blueswir1	case 0x056: /* VIS I fpsub32 */
3835	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3836	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3837	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3838	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpadd32);
3839	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3840	e9ebed4d	blueswir1	break;
3841	e9ebed4d	blueswir1	case 0x057: /* VIS I fpsub32s */
3842	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3843	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3844	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3845	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fpsub32s);
3846	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3847	e9ebed4d	blueswir1	break;
3848	3299908c	blueswir1	case 0x060: /* VIS I fzero */
3849	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3850	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_0);
3851	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3852	3299908c	blueswir1	break;
3853	3299908c	blueswir1	case 0x061: /* VIS I fzeros */
3854	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3855	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_0);
3856	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3857	3299908c	blueswir1	break;
3858	e9ebed4d	blueswir1	case 0x062: /* VIS I fnor */
3859	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3860	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3861	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3862	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnor);
3863	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3864	e9ebed4d	blueswir1	break;
3865	e9ebed4d	blueswir1	case 0x063: /* VIS I fnors */
3866	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3867	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3868	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3869	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnors);
3870	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3871	e9ebed4d	blueswir1	break;
3872	e9ebed4d	blueswir1	case 0x064: /* VIS I fandnot2 */
3873	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3874	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3875	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3876	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3877	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3878	e9ebed4d	blueswir1	break;
3879	e9ebed4d	blueswir1	case 0x065: /* VIS I fandnot2s */
3880	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3881	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3882	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
3883	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3884	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3885	e9ebed4d	blueswir1	break;
3886	e9ebed4d	blueswir1	case 0x066: /* VIS I fnot2 */
3887	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3888	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3889	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3890	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3891	e9ebed4d	blueswir1	break;
3892	e9ebed4d	blueswir1	case 0x067: /* VIS I fnot2s */
3893	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3894	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3895	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3896	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3897	e9ebed4d	blueswir1	break;
3898	e9ebed4d	blueswir1	case 0x068: /* VIS I fandnot1 */
3899	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3900	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3901	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3902	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnot);
3903	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3904	e9ebed4d	blueswir1	break;
3905	e9ebed4d	blueswir1	case 0x069: /* VIS I fandnot1s */
3906	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3907	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3908	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3909	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fandnots);
3910	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3911	e9ebed4d	blueswir1	break;
3912	e9ebed4d	blueswir1	case 0x06a: /* VIS I fnot1 */
3913	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3914	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3915	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3916	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3917	e9ebed4d	blueswir1	break;
3918	e9ebed4d	blueswir1	case 0x06b: /* VIS I fnot1s */
3919	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3920	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
3921	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnot);
3922	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3923	e9ebed4d	blueswir1	break;
3924	e9ebed4d	blueswir1	case 0x06c: /* VIS I fxor */
3925	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3926	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3927	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3928	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxor);
3929	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3930	e9ebed4d	blueswir1	break;
3931	e9ebed4d	blueswir1	case 0x06d: /* VIS I fxors */
3932	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3933	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3934	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3935	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxors);
3936	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3937	e9ebed4d	blueswir1	break;
3938	e9ebed4d	blueswir1	case 0x06e: /* VIS I fnand */
3939	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3940	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3941	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3942	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnand);
3943	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3944	e9ebed4d	blueswir1	break;
3945	e9ebed4d	blueswir1	case 0x06f: /* VIS I fnands */
3946	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3947	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3948	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3949	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fnands);
3950	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3951	e9ebed4d	blueswir1	break;
3952	e9ebed4d	blueswir1	case 0x070: /* VIS I fand */
3953	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3954	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3955	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3956	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fand);
3957	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3958	e9ebed4d	blueswir1	break;
3959	e9ebed4d	blueswir1	case 0x071: /* VIS I fands */
3960	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3961	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3962	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3963	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fands);
3964	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3965	e9ebed4d	blueswir1	break;
3966	e9ebed4d	blueswir1	case 0x072: /* VIS I fxnor */
3967	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3968	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3969	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
3970	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnor);
3971	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3972	e9ebed4d	blueswir1	break;
3973	e9ebed4d	blueswir1	case 0x073: /* VIS I fxnors */
3974	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3975	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
3976	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
3977	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fxnors);
3978	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
3979	e9ebed4d	blueswir1	break;
3980	3299908c	blueswir1	case 0x074: /* VIS I fsrc1 */
3981	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3982	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
3983	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3984	3299908c	blueswir1	break;
3985	3299908c	blueswir1	case 0x075: /* VIS I fsrc1s */
3986	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3987	3299908c	blueswir1	gen_op_load_fpr_FT0(rs1);
3988	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
3989	3299908c	blueswir1	break;
3990	e9ebed4d	blueswir1	case 0x076: /* VIS I fornot2 */
3991	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3992	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs1));
3993	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
3994	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
3995	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
3996	e9ebed4d	blueswir1	break;
3997	e9ebed4d	blueswir1	case 0x077: /* VIS I fornot2s */
3998	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
3999	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
4000	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
4001	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4002	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4003	e9ebed4d	blueswir1	break;
4004	3299908c	blueswir1	case 0x078: /* VIS I fsrc2 */
4005	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4006	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs2));
4007	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4008	3299908c	blueswir1	break;
4009	3299908c	blueswir1	case 0x079: /* VIS I fsrc2s */
4010	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4011	3299908c	blueswir1	gen_op_load_fpr_FT0(rs2);
4012	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4013	3299908c	blueswir1	break;
4014	e9ebed4d	blueswir1	case 0x07a: /* VIS I fornot1 */
4015	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4016	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4017	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4018	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornot);
4019	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4020	e9ebed4d	blueswir1	break;
4021	e9ebed4d	blueswir1	case 0x07b: /* VIS I fornot1s */
4022	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4023	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4024	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4025	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fornots);
4026	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4027	e9ebed4d	blueswir1	break;
4028	e9ebed4d	blueswir1	case 0x07c: /* VIS I for */
4029	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4030	2382dc6b	blueswir1	gen_op_load_fpr_DT0(DFPREG(rs1));
4031	2382dc6b	blueswir1	gen_op_load_fpr_DT1(DFPREG(rs2));
4032	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_for);
4033	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4034	e9ebed4d	blueswir1	break;
4035	e9ebed4d	blueswir1	case 0x07d: /* VIS I fors */
4036	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4037	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
4038	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
4039	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_fors);
4040	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
4041	e9ebed4d	blueswir1	break;
4042	3299908c	blueswir1	case 0x07e: /* VIS I fone */
4043	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4044	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_DT0_1);
4045	2382dc6b	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4046	3299908c	blueswir1	break;
4047	3299908c	blueswir1	case 0x07f: /* VIS I fones */
4048	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, VIS1);
4049	44e7757c	blueswir1	tcg_gen_helper_0_0(helper_movl_FT0_1);
4050	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
4051	3299908c	blueswir1	break;
4052	e9ebed4d	blueswir1	case 0x080: /* VIS I shutdown */
4053	e9ebed4d	blueswir1	case 0x081: /* VIS II siam */
4054	e9ebed4d	blueswir1	// XXX
4055	e9ebed4d	blueswir1	goto illegal_insn;
4056	3299908c	blueswir1	default:
4057	3299908c	blueswir1	goto illegal_insn;
4058	3299908c	blueswir1	}
4059	3299908c	blueswir1	#else
4060	0f8a249a	blueswir1	goto ncp_insn;
4061	3299908c	blueswir1	#endif
4062	3299908c	blueswir1	} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4063	fcc72045	blueswir1	#ifdef TARGET_SPARC64
4064	0f8a249a	blueswir1	goto illegal_insn;
4065	fcc72045	blueswir1	#else
4066	0f8a249a	blueswir1	goto ncp_insn;
4067	fcc72045	blueswir1	#endif
4068	3475187d	bellard	#ifdef TARGET_SPARC64
4069	0f8a249a	blueswir1	} else if (xop == 0x39) { /* V9 return */
4070	2ea815ca	blueswir1	TCGv r_const;
4071	2ea815ca	blueswir1
4072	6ae20372	blueswir1	save_state(dc, cpu_cond);
4073	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4074	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4075	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4076	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4077	0f8a249a	blueswir1	} else { /* register */
4078	3475187d	bellard	rs2 = GET_FIELD(insn, 27, 31);
4079	0f8a249a	blueswir1	if (rs2) {
4080	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4081	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4082	6f551262	blueswir1	} else
4083	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4084	3475187d	bellard	}
4085	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4086	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4087	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4088	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4089	2ea815ca	blueswir1	tcg_temp_free(r_const);
4090	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4091	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4092	0f8a249a	blueswir1	goto jmp_insn;
4093	3475187d	bellard	#endif
4094	0f8a249a	blueswir1	} else {
4095	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4096	0f8a249a	blueswir1	if (IS_IMM) { /* immediate */
4097	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4098	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4099	0f8a249a	blueswir1	} else { /* register */
4100	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
4101	0f8a249a	blueswir1	if (rs2) {
4102	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4103	6ae20372	blueswir1	tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4104	6f551262	blueswir1	} else
4105	6f551262	blueswir1	tcg_gen_mov_tl(cpu_dst, cpu_src1);
4106	cf495bcf	bellard	}
4107	0f8a249a	blueswir1	switch (xop) {
4108	0f8a249a	blueswir1	case 0x38: /* jmpl */
4109	0f8a249a	blueswir1	{
4110	2ea815ca	blueswir1	TCGv r_const;
4111	2ea815ca	blueswir1
4112	2ea815ca	blueswir1	r_const = tcg_const_tl(dc->pc);
4113	2ea815ca	blueswir1	gen_movl_TN_reg(rd, r_const);
4114	2ea815ca	blueswir1	tcg_temp_free(r_const);
4115	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4116	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4117	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4118	2ea815ca	blueswir1	r_const);
4119	2ea815ca	blueswir1	tcg_temp_free(r_const);
4120	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4121	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4122	0f8a249a	blueswir1	}
4123	0f8a249a	blueswir1	goto jmp_insn;
4124	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4125	0f8a249a	blueswir1	case 0x39: /* rett, V9 return */
4126	0f8a249a	blueswir1	{
4127	2ea815ca	blueswir1	TCGv r_const;
4128	2ea815ca	blueswir1
4129	0f8a249a	blueswir1	if (!supervisor(dc))
4130	0f8a249a	blueswir1	goto priv_insn;
4131	6ae20372	blueswir1	gen_mov_pc_npc(dc, cpu_cond);
4132	2ea815ca	blueswir1	r_const = tcg_const_i32(3);
4133	77f193da	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4134	2ea815ca	blueswir1	r_const);
4135	2ea815ca	blueswir1	tcg_temp_free(r_const);
4136	6ae20372	blueswir1	tcg_gen_mov_tl(cpu_npc, cpu_dst);
4137	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4138	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_rett);
4139	0f8a249a	blueswir1	}
4140	0f8a249a	blueswir1	goto jmp_insn;
4141	0f8a249a	blueswir1	#endif
4142	0f8a249a	blueswir1	case 0x3b: /* flush */
4143	5578ceab	blueswir1	if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4144	64a88d5d	blueswir1	goto unimp_flush;
4145	6ae20372	blueswir1	tcg_gen_helper_0_1(helper_flush, cpu_dst);
4146	0f8a249a	blueswir1	break;
4147	0f8a249a	blueswir1	case 0x3c: /* save */
4148	6ae20372	blueswir1	save_state(dc, cpu_cond);
4149	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_save);
4150	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4151	0f8a249a	blueswir1	break;
4152	0f8a249a	blueswir1	case 0x3d: /* restore */
4153	6ae20372	blueswir1	save_state(dc, cpu_cond);
4154	72a9747b	blueswir1	tcg_gen_helper_0_0(helper_restore);
4155	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_dst);
4156	0f8a249a	blueswir1	break;
4157	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4158	0f8a249a	blueswir1	case 0x3e: /* V9 done/retry */
4159	0f8a249a	blueswir1	{
4160	0f8a249a	blueswir1	switch (rd) {
4161	0f8a249a	blueswir1	case 0:
4162	0f8a249a	blueswir1	if (!supervisor(dc))
4163	0f8a249a	blueswir1	goto priv_insn;
4164	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4165	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4166	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_done);
4167	0f8a249a	blueswir1	goto jmp_insn;
4168	0f8a249a	blueswir1	case 1:
4169	0f8a249a	blueswir1	if (!supervisor(dc))
4170	0f8a249a	blueswir1	goto priv_insn;
4171	0f8a249a	blueswir1	dc->npc = DYNAMIC_PC;
4172	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4173	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_retry);
4174	0f8a249a	blueswir1	goto jmp_insn;
4175	0f8a249a	blueswir1	default:
4176	0f8a249a	blueswir1	goto illegal_insn;
4177	0f8a249a	blueswir1	}
4178	0f8a249a	blueswir1	}
4179	0f8a249a	blueswir1	break;
4180	0f8a249a	blueswir1	#endif
4181	0f8a249a	blueswir1	default:
4182	0f8a249a	blueswir1	goto illegal_insn;
4183	0f8a249a	blueswir1	}
4184	cf495bcf	bellard	}
4185	0f8a249a	blueswir1	break;
4186	0f8a249a	blueswir1	}
4187	0f8a249a	blueswir1	break;
4188	0f8a249a	blueswir1	case 3: /* load/store instructions */
4189	0f8a249a	blueswir1	{
4190	0f8a249a	blueswir1	unsigned int xop = GET_FIELD(insn, 7, 12);
4191	9322a4bf	blueswir1
4192	9322a4bf	blueswir1	cpu_src1 = get_src1(insn, cpu_src1);
4193	71817e48	blueswir1	if (xop == 0x3c \|\| xop == 0x3e) { // V9 casa/casxa
4194	81ad8ba2	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4195	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4196	71817e48	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4197	71817e48	blueswir1	} else if (IS_IMM) { /* immediate */
4198	0f8a249a	blueswir1	rs2 = GET_FIELDs(insn, 19, 31);
4199	6ae20372	blueswir1	tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4200	0f8a249a	blueswir1	} else { /* register */
4201	0f8a249a	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
4202	0f8a249a	blueswir1	if (rs2 != 0) {
4203	6ae20372	blueswir1	gen_movl_reg_TN(rs2, cpu_src2);
4204	6ae20372	blueswir1	tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4205	6f551262	blueswir1	} else
4206	6f551262	blueswir1	tcg_gen_mov_tl(cpu_addr, cpu_src1);
4207	0f8a249a	blueswir1	}
4208	2f2ecb83	blueswir1	if (xop < 4 \|\| (xop > 7 && xop < 0x14 && xop != 0x0e) \|\|
4209	2f2ecb83	blueswir1	(xop > 0x17 && xop <= 0x1d ) \|\|
4210	2f2ecb83	blueswir1	(xop > 0x2c && xop <= 0x33) \|\| xop == 0x1f \|\| xop == 0x3d) {
4211	0f8a249a	blueswir1	switch (xop) {
4212	1a2fb1c0	blueswir1	case 0x0: /* load unsigned word */
4213	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4214	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4215	0f8a249a	blueswir1	break;
4216	0f8a249a	blueswir1	case 0x1: /* load unsigned byte */
4217	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4218	6ae20372	blueswir1	tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4219	0f8a249a	blueswir1	break;
4220	0f8a249a	blueswir1	case 0x2: /* load unsigned halfword */
4221	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4222	6ae20372	blueswir1	tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4223	0f8a249a	blueswir1	break;
4224	0f8a249a	blueswir1	case 0x3: /* load double word */
4225	0f8a249a	blueswir1	if (rd & 1)
4226	d4218d99	blueswir1	goto illegal_insn;
4227	1a2fb1c0	blueswir1	else {
4228	2ea815ca	blueswir1	TCGv r_const;
4229	2ea815ca	blueswir1
4230	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4231	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4232	d987963a	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4233	2ea815ca	blueswir1	r_const); // XXX remove
4234	2ea815ca	blueswir1	tcg_temp_free(r_const);
4235	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4236	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4237	32b6c812	blueswir1	tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4238	32b6c812	blueswir1	tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4239	32b6c812	blueswir1	gen_movl_TN_reg(rd + 1, cpu_tmp0);
4240	8911f501	blueswir1	tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4241	6ae20372	blueswir1	tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4242	6ae20372	blueswir1	tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4243	1a2fb1c0	blueswir1	}
4244	0f8a249a	blueswir1	break;
4245	0f8a249a	blueswir1	case 0x9: /* load signed byte */
4246	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4247	6ae20372	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4248	0f8a249a	blueswir1	break;
4249	0f8a249a	blueswir1	case 0xa: /* load signed halfword */
4250	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4251	6ae20372	blueswir1	tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4252	0f8a249a	blueswir1	break;
4253	0f8a249a	blueswir1	case 0xd: /* ldstub -- XXX: should be atomically */
4254	2ea815ca	blueswir1	{
4255	2ea815ca	blueswir1	TCGv r_const;
4256	2ea815ca	blueswir1
4257	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4258	2ea815ca	blueswir1	tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4259	2ea815ca	blueswir1	r_const = tcg_const_tl(0xff);
4260	2ea815ca	blueswir1	tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4261	2ea815ca	blueswir1	tcg_temp_free(r_const);
4262	2ea815ca	blueswir1	}
4263	0f8a249a	blueswir1	break;
4264	77f193da	blueswir1	case 0x0f: /* swap register with memory. Also
4265	77f193da	blueswir1	atomically */
4266	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4267	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4268	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4269	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4270	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4271	6ae20372	blueswir1	tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4272	0f8a249a	blueswir1	break;
4273	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4274	0f8a249a	blueswir1	case 0x10: /* load word alternate */
4275	3475187d	bellard	#ifndef TARGET_SPARC64
4276	0f8a249a	blueswir1	if (IS_IMM)
4277	0f8a249a	blueswir1	goto illegal_insn;
4278	0f8a249a	blueswir1	if (!supervisor(dc))
4279	0f8a249a	blueswir1	goto priv_insn;
4280	6ea4a6c8	blueswir1	#endif
4281	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4282	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4283	0f8a249a	blueswir1	break;
4284	0f8a249a	blueswir1	case 0x11: /* load unsigned byte alternate */
4285	3475187d	bellard	#ifndef TARGET_SPARC64
4286	0f8a249a	blueswir1	if (IS_IMM)
4287	0f8a249a	blueswir1	goto illegal_insn;
4288	0f8a249a	blueswir1	if (!supervisor(dc))
4289	0f8a249a	blueswir1	goto priv_insn;
4290	0f8a249a	blueswir1	#endif
4291	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4292	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4293	0f8a249a	blueswir1	break;
4294	0f8a249a	blueswir1	case 0x12: /* load unsigned halfword alternate */
4295	3475187d	bellard	#ifndef TARGET_SPARC64
4296	0f8a249a	blueswir1	if (IS_IMM)
4297	0f8a249a	blueswir1	goto illegal_insn;
4298	0f8a249a	blueswir1	if (!supervisor(dc))
4299	0f8a249a	blueswir1	goto priv_insn;
4300	6ea4a6c8	blueswir1	#endif
4301	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4302	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4303	0f8a249a	blueswir1	break;
4304	0f8a249a	blueswir1	case 0x13: /* load double word alternate */
4305	3475187d	bellard	#ifndef TARGET_SPARC64
4306	0f8a249a	blueswir1	if (IS_IMM)
4307	0f8a249a	blueswir1	goto illegal_insn;
4308	0f8a249a	blueswir1	if (!supervisor(dc))
4309	0f8a249a	blueswir1	goto priv_insn;
4310	3475187d	bellard	#endif
4311	0f8a249a	blueswir1	if (rd & 1)
4312	d4218d99	blueswir1	goto illegal_insn;
4313	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4314	db166940	blueswir1	gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4315	db166940	blueswir1	goto skip_move;
4316	0f8a249a	blueswir1	case 0x19: /* load signed byte alternate */
4317	3475187d	bellard	#ifndef TARGET_SPARC64
4318	0f8a249a	blueswir1	if (IS_IMM)
4319	0f8a249a	blueswir1	goto illegal_insn;
4320	0f8a249a	blueswir1	if (!supervisor(dc))
4321	0f8a249a	blueswir1	goto priv_insn;
4322	0f8a249a	blueswir1	#endif
4323	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4324	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4325	0f8a249a	blueswir1	break;
4326	0f8a249a	blueswir1	case 0x1a: /* load signed halfword alternate */
4327	3475187d	bellard	#ifndef TARGET_SPARC64
4328	0f8a249a	blueswir1	if (IS_IMM)
4329	0f8a249a	blueswir1	goto illegal_insn;
4330	0f8a249a	blueswir1	if (!supervisor(dc))
4331	0f8a249a	blueswir1	goto priv_insn;
4332	6ea4a6c8	blueswir1	#endif
4333	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4334	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4335	0f8a249a	blueswir1	break;
4336	0f8a249a	blueswir1	case 0x1d: /* ldstuba -- XXX: should be atomically */
4337	3475187d	bellard	#ifndef TARGET_SPARC64
4338	0f8a249a	blueswir1	if (IS_IMM)
4339	0f8a249a	blueswir1	goto illegal_insn;
4340	0f8a249a	blueswir1	if (!supervisor(dc))
4341	0f8a249a	blueswir1	goto priv_insn;
4342	0f8a249a	blueswir1	#endif
4343	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4344	6ae20372	blueswir1	gen_ldstub_asi(cpu_val, cpu_addr, insn);
4345	0f8a249a	blueswir1	break;
4346	77f193da	blueswir1	case 0x1f: /* swap reg with alt. memory. Also
4347	77f193da	blueswir1	atomically */
4348	64a88d5d	blueswir1	CHECK_IU_FEATURE(dc, SWAP);
4349	3475187d	bellard	#ifndef TARGET_SPARC64
4350	0f8a249a	blueswir1	if (IS_IMM)
4351	0f8a249a	blueswir1	goto illegal_insn;
4352	0f8a249a	blueswir1	if (!supervisor(dc))
4353	0f8a249a	blueswir1	goto priv_insn;
4354	6ea4a6c8	blueswir1	#endif
4355	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4356	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4357	6ae20372	blueswir1	gen_swap_asi(cpu_val, cpu_addr, insn);
4358	0f8a249a	blueswir1	break;
4359	3475187d	bellard
4360	3475187d	bellard	#ifndef TARGET_SPARC64
4361	0f8a249a	blueswir1	case 0x30: /* ldc */
4362	0f8a249a	blueswir1	case 0x31: /* ldcsr */
4363	0f8a249a	blueswir1	case 0x33: /* lddc */
4364	0f8a249a	blueswir1	goto ncp_insn;
4365	3475187d	bellard	#endif
4366	3475187d	bellard	#endif
4367	3475187d	bellard	#ifdef TARGET_SPARC64
4368	0f8a249a	blueswir1	case 0x08: /* V9 ldsw */
4369	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4370	6ae20372	blueswir1	tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4371	0f8a249a	blueswir1	break;
4372	0f8a249a	blueswir1	case 0x0b: /* V9 ldx */
4373	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4374	6ae20372	blueswir1	tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4375	0f8a249a	blueswir1	break;
4376	0f8a249a	blueswir1	case 0x18: /* V9 ldswa */
4377	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4378	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4379	0f8a249a	blueswir1	break;
4380	0f8a249a	blueswir1	case 0x1b: /* V9 ldxa */
4381	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4382	6ae20372	blueswir1	gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4383	0f8a249a	blueswir1	break;
4384	0f8a249a	blueswir1	case 0x2d: /* V9 prefetch, no effect */
4385	0f8a249a	blueswir1	goto skip_move;
4386	0f8a249a	blueswir1	case 0x30: /* V9 ldfa */
4387	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4388	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 4, rd);
4389	81ad8ba2	blueswir1	goto skip_move;
4390	0f8a249a	blueswir1	case 0x33: /* V9 lddfa */
4391	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4392	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4393	81ad8ba2	blueswir1	goto skip_move;
4394	0f8a249a	blueswir1	case 0x3d: /* V9 prefetcha, no effect */
4395	0f8a249a	blueswir1	goto skip_move;
4396	0f8a249a	blueswir1	case 0x32: /* V9 ldqfa */
4397	64a88d5d	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4398	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4399	6ae20372	blueswir1	gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4400	1f587329	blueswir1	goto skip_move;
4401	1f587329	blueswir1	#endif
4402	0f8a249a	blueswir1	default:
4403	0f8a249a	blueswir1	goto illegal_insn;
4404	0f8a249a	blueswir1	}
4405	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4406	db166940	blueswir1	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4407	0f8a249a	blueswir1	skip_move: ;
4408	3475187d	bellard	#endif
4409	0f8a249a	blueswir1	} else if (xop >= 0x20 && xop < 0x24) {
4410	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4411	a80dde08	bellard	goto jmp_insn;
4412	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4413	0f8a249a	blueswir1	switch (xop) {
4414	0f8a249a	blueswir1	case 0x20: /* load fpreg */
4415	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4416	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4417	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4418	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4419	0f8a249a	blueswir1	break;
4420	0f8a249a	blueswir1	case 0x21: /* load fsr */
4421	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4422	6ae20372	blueswir1	tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4423	ce8536e2	blueswir1	tcg_gen_st_i32(cpu_tmp32, cpu_env,
4424	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4425	7e8c2b6c	blueswir1	tcg_gen_helper_0_0(helper_ldfsr);
4426	0f8a249a	blueswir1	break;
4427	0f8a249a	blueswir1	case 0x22: /* load quad fpreg */
4428	2ea815ca	blueswir1	{
4429	2ea815ca	blueswir1	TCGv r_const;
4430	2ea815ca	blueswir1
4431	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4432	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4433	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4434	2ea815ca	blueswir1	tcg_temp_free(r_const);
4435	2ea815ca	blueswir1	gen_op_store_QT0_fpr(QFPREG(rd));
4436	2ea815ca	blueswir1	}
4437	1f587329	blueswir1	break;
4438	0f8a249a	blueswir1	case 0x23: /* load double fpreg */
4439	2ea815ca	blueswir1	{
4440	2ea815ca	blueswir1	TCGv r_const;
4441	2ea815ca	blueswir1
4442	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4443	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4444	2ea815ca	blueswir1	tcg_temp_free(r_const);
4445	2ea815ca	blueswir1	gen_op_store_DT0_fpr(DFPREG(rd));
4446	2ea815ca	blueswir1	}
4447	0f8a249a	blueswir1	break;
4448	0f8a249a	blueswir1	default:
4449	0f8a249a	blueswir1	goto illegal_insn;
4450	0f8a249a	blueswir1	}
4451	0f8a249a	blueswir1	} else if (xop < 8 \|\| (xop >= 0x14 && xop < 0x18) \|\| \
4452	0f8a249a	blueswir1	xop == 0xe \|\| xop == 0x1e) {
4453	6ae20372	blueswir1	gen_movl_reg_TN(rd, cpu_val);
4454	0f8a249a	blueswir1	switch (xop) {
4455	1a2fb1c0	blueswir1	case 0x4: /* store word */
4456	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4457	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4458	0f8a249a	blueswir1	break;
4459	1a2fb1c0	blueswir1	case 0x5: /* store byte */
4460	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4461	6ae20372	blueswir1	tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4462	0f8a249a	blueswir1	break;
4463	1a2fb1c0	blueswir1	case 0x6: /* store halfword */
4464	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4465	6ae20372	blueswir1	tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4466	0f8a249a	blueswir1	break;
4467	1a2fb1c0	blueswir1	case 0x7: /* store double word */
4468	0f8a249a	blueswir1	if (rd & 1)
4469	d4218d99	blueswir1	goto illegal_insn;
4470	1a2fb1c0	blueswir1	else {
4471	2ea815ca	blueswir1	TCGv r_low, r_const;
4472	1a2fb1c0	blueswir1
4473	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4474	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4475	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4476	c2bc0e38	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4477	2ea815ca	blueswir1	r_const); // XXX remove
4478	2ea815ca	blueswir1	tcg_temp_free(r_const);
4479	8d96d209	blueswir1	r_low = tcg_temp_new(TCG_TYPE_TL);
4480	1a2fb1c0	blueswir1	gen_movl_reg_TN(rd + 1, r_low);
4481	6ae20372	blueswir1	tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4482	1a2fb1c0	blueswir1	r_low);
4483	2ea815ca	blueswir1	tcg_temp_free(r_low);
4484	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4485	7fa76c0b	blueswir1	}
4486	0f8a249a	blueswir1	break;
4487	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
4488	1a2fb1c0	blueswir1	case 0x14: /* store word alternate */
4489	3475187d	bellard	#ifndef TARGET_SPARC64
4490	0f8a249a	blueswir1	if (IS_IMM)
4491	0f8a249a	blueswir1	goto illegal_insn;
4492	0f8a249a	blueswir1	if (!supervisor(dc))
4493	0f8a249a	blueswir1	goto priv_insn;
4494	3475187d	bellard	#endif
4495	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4496	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 4);
4497	d39c0b99	bellard	break;
4498	1a2fb1c0	blueswir1	case 0x15: /* store byte alternate */
4499	3475187d	bellard	#ifndef TARGET_SPARC64
4500	0f8a249a	blueswir1	if (IS_IMM)
4501	0f8a249a	blueswir1	goto illegal_insn;
4502	0f8a249a	blueswir1	if (!supervisor(dc))
4503	0f8a249a	blueswir1	goto priv_insn;
4504	3475187d	bellard	#endif
4505	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4506	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 1);
4507	d39c0b99	bellard	break;
4508	1a2fb1c0	blueswir1	case 0x16: /* store halfword alternate */
4509	3475187d	bellard	#ifndef TARGET_SPARC64
4510	0f8a249a	blueswir1	if (IS_IMM)
4511	0f8a249a	blueswir1	goto illegal_insn;
4512	0f8a249a	blueswir1	if (!supervisor(dc))
4513	0f8a249a	blueswir1	goto priv_insn;
4514	3475187d	bellard	#endif
4515	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4516	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 2);
4517	d39c0b99	bellard	break;
4518	1a2fb1c0	blueswir1	case 0x17: /* store double word alternate */
4519	3475187d	bellard	#ifndef TARGET_SPARC64
4520	0f8a249a	blueswir1	if (IS_IMM)
4521	0f8a249a	blueswir1	goto illegal_insn;
4522	0f8a249a	blueswir1	if (!supervisor(dc))
4523	0f8a249a	blueswir1	goto priv_insn;
4524	3475187d	bellard	#endif
4525	0f8a249a	blueswir1	if (rd & 1)
4526	d4218d99	blueswir1	goto illegal_insn;
4527	1a2fb1c0	blueswir1	else {
4528	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4529	6ae20372	blueswir1	gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4530	1a2fb1c0	blueswir1	}
4531	d39c0b99	bellard	break;
4532	e80cfcfc	bellard	#endif
4533	3475187d	bellard	#ifdef TARGET_SPARC64
4534	0f8a249a	blueswir1	case 0x0e: /* V9 stx */
4535	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4536	6ae20372	blueswir1	tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4537	0f8a249a	blueswir1	break;
4538	0f8a249a	blueswir1	case 0x1e: /* V9 stxa */
4539	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4540	6ae20372	blueswir1	gen_st_asi(cpu_val, cpu_addr, insn, 8);
4541	0f8a249a	blueswir1	break;
4542	3475187d	bellard	#endif
4543	0f8a249a	blueswir1	default:
4544	0f8a249a	blueswir1	goto illegal_insn;
4545	0f8a249a	blueswir1	}
4546	0f8a249a	blueswir1	} else if (xop > 0x23 && xop < 0x28) {
4547	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4548	a80dde08	bellard	goto jmp_insn;
4549	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4550	0f8a249a	blueswir1	switch (xop) {
4551	ce8536e2	blueswir1	case 0x24: /* store fpreg */
4552	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4553	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4554	ce8536e2	blueswir1	offsetof(CPUState, fpr[rd]));
4555	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4556	0f8a249a	blueswir1	break;
4557	0f8a249a	blueswir1	case 0x25: /* stfsr, V9 stxfsr */
4558	2cade6a3	blueswir1	gen_address_mask(dc, cpu_addr);
4559	bb5529bb	blueswir1	tcg_gen_helper_0_0(helper_stfsr);
4560	ce8536e2	blueswir1	tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4561	ce8536e2	blueswir1	offsetof(CPUState, ft0));
4562	6ae20372	blueswir1	tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4563	0f8a249a	blueswir1	break;
4564	1f587329	blueswir1	case 0x26:
4565	1f587329	blueswir1	#ifdef TARGET_SPARC64
4566	1f587329	blueswir1	/* V9 stqf, store quad fpreg */
4567	2ea815ca	blueswir1	{
4568	2ea815ca	blueswir1	TCGv r_const;
4569	2ea815ca	blueswir1
4570	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4571	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4572	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4573	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4574	2ea815ca	blueswir1	tcg_temp_free(r_const);
4575	2ea815ca	blueswir1	}
4576	1f587329	blueswir1	break;
4577	1f587329	blueswir1	#else /* !TARGET_SPARC64 */
4578	1f587329	blueswir1	/* stdfq, store floating point queue */
4579	1f587329	blueswir1	#if defined(CONFIG_USER_ONLY)
4580	1f587329	blueswir1	goto illegal_insn;
4581	1f587329	blueswir1	#else
4582	0f8a249a	blueswir1	if (!supervisor(dc))
4583	0f8a249a	blueswir1	goto priv_insn;
4584	6ae20372	blueswir1	if (gen_trap_ifnofpu(dc, cpu_cond))
4585	0f8a249a	blueswir1	goto jmp_insn;
4586	0f8a249a	blueswir1	goto nfq_insn;
4587	0f8a249a	blueswir1	#endif
4588	1f587329	blueswir1	#endif
4589	7fa76c0b	blueswir1	case 0x27: /* store double fpreg */
4590	2ea815ca	blueswir1	{
4591	2ea815ca	blueswir1	TCGv r_const;
4592	2ea815ca	blueswir1
4593	2ea815ca	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4594	2ea815ca	blueswir1	r_const = tcg_const_i32(dc->mem_idx);
4595	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4596	2ea815ca	blueswir1	tcg_temp_free(r_const);
4597	2ea815ca	blueswir1	}
4598	0f8a249a	blueswir1	break;
4599	0f8a249a	blueswir1	default:
4600	0f8a249a	blueswir1	goto illegal_insn;
4601	0f8a249a	blueswir1	}
4602	0f8a249a	blueswir1	} else if (xop > 0x33 && xop < 0x3f) {
4603	c2bc0e38	blueswir1	save_state(dc, cpu_cond);
4604	0f8a249a	blueswir1	switch (xop) {
4605	a4d17f19	blueswir1	#ifdef TARGET_SPARC64
4606	0f8a249a	blueswir1	case 0x34: /* V9 stfa */
4607	3391c818	blueswir1	gen_op_load_fpr_FT0(rd);
4608	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 4, rd);
4609	0f8a249a	blueswir1	break;
4610	1f587329	blueswir1	case 0x36: /* V9 stqfa */
4611	2ea815ca	blueswir1	{
4612	2ea815ca	blueswir1	TCGv r_const;
4613	2ea815ca	blueswir1
4614	2ea815ca	blueswir1	CHECK_FPU_FEATURE(dc, FLOAT128);
4615	2ea815ca	blueswir1	r_const = tcg_const_i32(7);
4616	2ea815ca	blueswir1	tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4617	2ea815ca	blueswir1	r_const);
4618	2ea815ca	blueswir1	tcg_temp_free(r_const);
4619	2ea815ca	blueswir1	gen_op_load_fpr_QT0(QFPREG(rd));
4620	2ea815ca	blueswir1	gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4621	2ea815ca	blueswir1	}
4622	1f587329	blueswir1	break;
4623	0f8a249a	blueswir1	case 0x37: /* V9 stdfa */
4624	3391c818	blueswir1	gen_op_load_fpr_DT0(DFPREG(rd));
4625	6ae20372	blueswir1	gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4626	0f8a249a	blueswir1	break;
4627	0f8a249a	blueswir1	case 0x3c: /* V9 casa */
4628	71817e48	blueswir1	gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4629	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4630	0f8a249a	blueswir1	break;
4631	0f8a249a	blueswir1	case 0x3e: /* V9 casxa */
4632	71817e48	blueswir1	gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4633	6ae20372	blueswir1	gen_movl_TN_reg(rd, cpu_val);
4634	0f8a249a	blueswir1	break;
4635	a4d17f19	blueswir1	#else
4636	0f8a249a	blueswir1	case 0x34: /* stc */
4637	0f8a249a	blueswir1	case 0x35: /* stcsr */
4638	0f8a249a	blueswir1	case 0x36: /* stdcq */
4639	0f8a249a	blueswir1	case 0x37: /* stdc */
4640	0f8a249a	blueswir1	goto ncp_insn;
4641	0f8a249a	blueswir1	#endif
4642	0f8a249a	blueswir1	default:
4643	0f8a249a	blueswir1	goto illegal_insn;
4644	0f8a249a	blueswir1	}
4645	e8af50a3	bellard	}
4646	0f8a249a	blueswir1	else
4647	0f8a249a	blueswir1	goto illegal_insn;
4648	0f8a249a	blueswir1	}
4649	0f8a249a	blueswir1	break;
4650	cf495bcf	bellard	}
4651	cf495bcf	bellard	/* default case for non jump instructions */
4652	72cbca10	bellard	if (dc->npc == DYNAMIC_PC) {
4653	0f8a249a	blueswir1	dc->pc = DYNAMIC_PC;
4654	0f8a249a	blueswir1	gen_op_next_insn();
4655	72cbca10	bellard	} else if (dc->npc == JUMP_PC) {
4656	72cbca10	bellard	/* we can do a static jump */
4657	6ae20372	blueswir1	gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4658	72cbca10	bellard	dc->is_br = 1;
4659	72cbca10	bellard	} else {
4660	0f8a249a	blueswir1	dc->pc = dc->npc;
4661	0f8a249a	blueswir1	dc->npc = dc->npc + 4;
4662	cf495bcf	bellard	}
4663	e80cfcfc	bellard	jmp_insn:
4664	cf495bcf	bellard	return;
4665	cf495bcf	bellard	illegal_insn:
4666	2ea815ca	blueswir1	{
4667	2ea815ca	blueswir1	TCGv r_const;
4668	2ea815ca	blueswir1
4669	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4670	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_ILL_INSN);
4671	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4672	2ea815ca	blueswir1	tcg_temp_free(r_const);
4673	2ea815ca	blueswir1	dc->is_br = 1;
4674	2ea815ca	blueswir1	}
4675	e8af50a3	bellard	return;
4676	64a88d5d	blueswir1	unimp_flush:
4677	2ea815ca	blueswir1	{
4678	2ea815ca	blueswir1	TCGv r_const;
4679	2ea815ca	blueswir1
4680	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4681	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4682	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4683	2ea815ca	blueswir1	tcg_temp_free(r_const);
4684	2ea815ca	blueswir1	dc->is_br = 1;
4685	2ea815ca	blueswir1	}
4686	64a88d5d	blueswir1	return;
4687	e80cfcfc	bellard	#if !defined(CONFIG_USER_ONLY)
4688	e8af50a3	bellard	priv_insn:
4689	2ea815ca	blueswir1	{
4690	2ea815ca	blueswir1	TCGv r_const;
4691	2ea815ca	blueswir1
4692	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4693	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_PRIV_INSN);
4694	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4695	2ea815ca	blueswir1	tcg_temp_free(r_const);
4696	2ea815ca	blueswir1	dc->is_br = 1;
4697	2ea815ca	blueswir1	}
4698	e80cfcfc	bellard	return;
4699	64a88d5d	blueswir1	#endif
4700	e80cfcfc	bellard	nfpu_insn:
4701	6ae20372	blueswir1	save_state(dc, cpu_cond);
4702	e80cfcfc	bellard	gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4703	e80cfcfc	bellard	dc->is_br = 1;
4704	fcc72045	blueswir1	return;
4705	64a88d5d	blueswir1	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4706	9143e598	blueswir1	nfq_insn:
4707	6ae20372	blueswir1	save_state(dc, cpu_cond);
4708	9143e598	blueswir1	gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4709	9143e598	blueswir1	dc->is_br = 1;
4710	9143e598	blueswir1	return;
4711	9143e598	blueswir1	#endif
4712	fcc72045	blueswir1	#ifndef TARGET_SPARC64
4713	fcc72045	blueswir1	ncp_insn:
4714	2ea815ca	blueswir1	{
4715	2ea815ca	blueswir1	TCGv r_const;
4716	2ea815ca	blueswir1
4717	2ea815ca	blueswir1	save_state(dc, cpu_cond);
4718	2ea815ca	blueswir1	r_const = tcg_const_i32(TT_NCP_INSN);
4719	2ea815ca	blueswir1	tcg_gen_helper_0_1(raise_exception, r_const);
4720	2ea815ca	blueswir1	tcg_temp_free(r_const);
4721	2ea815ca	blueswir1	dc->is_br = 1;
4722	2ea815ca	blueswir1	}
4723	fcc72045	blueswir1	return;
4724	fcc72045	blueswir1	#endif
4725	7a3f1944	bellard	}
4726	7a3f1944	bellard
4727	2cfc5f17	ths	static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4728	2cfc5f17	ths	int spc, CPUSPARCState *env)
4729	7a3f1944	bellard	{
4730	72cbca10	bellard	target_ulong pc_start, last_pc;
4731	cf495bcf	bellard	uint16_t *gen_opc_end;
4732	cf495bcf	bellard	DisasContext dc1, *dc = &dc1;
4733	e8af50a3	bellard	int j, lj = -1;
4734	2e70f6ef	pbrook	int num_insns;
4735	2e70f6ef	pbrook	int max_insns;
4736	cf495bcf	bellard
4737	cf495bcf	bellard	memset(dc, 0, sizeof(DisasContext));
4738	cf495bcf	bellard	dc->tb = tb;
4739	72cbca10	bellard	pc_start = tb->pc;
4740	cf495bcf	bellard	dc->pc = pc_start;
4741	e80cfcfc	bellard	last_pc = dc->pc;
4742	72cbca10	bellard	dc->npc = (target_ulong) tb->cs_base;
4743	6f27aba6	blueswir1	dc->mem_idx = cpu_mmu_index(env);
4744	5578ceab	blueswir1	dc->def = env->def;
4745	5578ceab	blueswir1	if ((dc->def->features & CPU_FEATURE_FLOAT))
4746	64a88d5d	blueswir1	dc->fpu_enabled = cpu_fpu_enabled(env);
4747	5578ceab	blueswir1	else
4748	64a88d5d	blueswir1	dc->fpu_enabled = 0;
4749	2cade6a3	blueswir1	#ifdef TARGET_SPARC64
4750	2cade6a3	blueswir1	dc->address_mask_32bit = env->pstate & PS_AM;
4751	2cade6a3	blueswir1	#endif
4752	cf495bcf	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4753	cf495bcf	bellard
4754	1a2fb1c0	blueswir1	cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4755	8911f501	blueswir1	cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4756	8911f501	blueswir1	cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4757	d987963a	blueswir1
4758	d987963a	blueswir1	cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4759	d987963a	blueswir1
4760	d987963a	blueswir1	// loads and stores
4761	3f0436fe	blueswir1	cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4762	d987963a	blueswir1	cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4763	1a2fb1c0	blueswir1
4764	2e70f6ef	pbrook	num_insns = 0;
4765	2e70f6ef	pbrook	max_insns = tb->cflags & CF_COUNT_MASK;
4766	2e70f6ef	pbrook	if (max_insns == 0)
4767	2e70f6ef	pbrook	max_insns = CF_COUNT_MASK;
4768	2e70f6ef	pbrook	gen_icount_start();
4769	cf495bcf	bellard	do {
4770	e8af50a3	bellard	if (env->nb_breakpoints > 0) {
4771	e8af50a3	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
4772	e8af50a3	bellard	if (env->breakpoints[j] == dc->pc) {
4773	0f8a249a	blueswir1	if (dc->pc != pc_start)
4774	6ae20372	blueswir1	save_state(dc, cpu_cond);
4775	1a2fb1c0	blueswir1	tcg_gen_helper_0_0(helper_debug);
4776	57fec1fe	bellard	tcg_gen_exit_tb(0);
4777	0f8a249a	blueswir1	dc->is_br = 1;
4778	e80cfcfc	bellard	goto exit_gen_loop;
4779	e8af50a3	bellard	}
4780	e8af50a3	bellard	}
4781	e8af50a3	bellard	}
4782	e8af50a3	bellard	if (spc) {
4783	e8af50a3	bellard	if (loglevel > 0)
4784	e8af50a3	bellard	fprintf(logfile, "Search PC...\n");
4785	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4786	e8af50a3	bellard	if (lj < j) {
4787	e8af50a3	bellard	lj++;
4788	e8af50a3	bellard	while (lj < j)
4789	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4790	e8af50a3	bellard	gen_opc_pc[lj] = dc->pc;
4791	e8af50a3	bellard	gen_opc_npc[lj] = dc->npc;
4792	e8af50a3	bellard	gen_opc_instr_start[lj] = 1;
4793	2e70f6ef	pbrook	gen_opc_icount[lj] = num_insns;
4794	e8af50a3	bellard	}
4795	e8af50a3	bellard	}
4796	2e70f6ef	pbrook	if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4797	2e70f6ef	pbrook	gen_io_start();
4798	0f8a249a	blueswir1	last_pc = dc->pc;
4799	0f8a249a	blueswir1	disas_sparc_insn(dc);
4800	2e70f6ef	pbrook	num_insns++;
4801	0f8a249a	blueswir1
4802	0f8a249a	blueswir1	if (dc->is_br)
4803	0f8a249a	blueswir1	break;
4804	0f8a249a	blueswir1	/* if the next PC is different, we abort now */
4805	0f8a249a	blueswir1	if (dc->pc != (last_pc + 4))
4806	0f8a249a	blueswir1	break;
4807	d39c0b99	bellard	/* if we reach a page boundary, we stop generation so that the
4808	d39c0b99	bellard	PC of a TT_TFAULT exception is always in the right page */
4809	d39c0b99	bellard	if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4810	d39c0b99	bellard	break;
4811	e80cfcfc	bellard	/* if single step mode, we generate only one instruction and
4812	e80cfcfc	bellard	generate an exception */
4813	e80cfcfc	bellard	if (env->singlestep_enabled) {
4814	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4815	57fec1fe	bellard	tcg_gen_exit_tb(0);
4816	e80cfcfc	bellard	break;
4817	e80cfcfc	bellard	}
4818	cf495bcf	bellard	} while ((gen_opc_ptr < gen_opc_end) &&
4819	2e70f6ef	pbrook	(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4820	2e70f6ef	pbrook	num_insns < max_insns);
4821	e80cfcfc	bellard
4822	e80cfcfc	bellard	exit_gen_loop:
4823	d987963a	blueswir1	tcg_temp_free(cpu_addr);
4824	3f0436fe	blueswir1	tcg_temp_free(cpu_val);
4825	d987963a	blueswir1	tcg_temp_free(cpu_dst);
4826	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp64);
4827	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp32);
4828	2ea815ca	blueswir1	tcg_temp_free(cpu_tmp0);
4829	2e70f6ef	pbrook	if (tb->cflags & CF_LAST_IO)
4830	2e70f6ef	pbrook	gen_io_end();
4831	72cbca10	bellard	if (!dc->is_br) {
4832	5fafdf24	ths	if (dc->pc != DYNAMIC_PC &&
4833	72cbca10	bellard	(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4834	72cbca10	bellard	/* static PC and NPC: we can use direct chaining */
4835	2f5680ee	blueswir1	gen_goto_tb(dc, 0, dc->pc, dc->npc);
4836	72cbca10	bellard	} else {
4837	72cbca10	bellard	if (dc->pc != DYNAMIC_PC)
4838	2f5680ee	blueswir1	tcg_gen_movi_tl(cpu_pc, dc->pc);
4839	6ae20372	blueswir1	save_npc(dc, cpu_cond);
4840	57fec1fe	bellard	tcg_gen_exit_tb(0);
4841	72cbca10	bellard	}
4842	72cbca10	bellard	}
4843	2e70f6ef	pbrook	gen_icount_end(tb, num_insns);
4844	cf495bcf	bellard	*gen_opc_ptr = INDEX_op_end;
4845	e8af50a3	bellard	if (spc) {
4846	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
4847	e8af50a3	bellard	lj++;
4848	e8af50a3	bellard	while (lj <= j)
4849	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
4850	e8af50a3	bellard	#if 0
4851	e8af50a3	bellard	if (loglevel > 0) {
4852	e8af50a3	bellard	page_dump(logfile);
4853	e8af50a3	bellard	}
4854	e8af50a3	bellard	#endif
4855	c3278b7b	bellard	gen_opc_jump_pc[0] = dc->jump_pc[0];
4856	c3278b7b	bellard	gen_opc_jump_pc[1] = dc->jump_pc[1];
4857	e8af50a3	bellard	} else {
4858	e80cfcfc	bellard	tb->size = last_pc + 4 - pc_start;
4859	2e70f6ef	pbrook	tb->icount = num_insns;
4860	e8af50a3	bellard	}
4861	7a3f1944	bellard	#ifdef DEBUG_DISAS
4862	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
4863	0f8a249a	blueswir1	fprintf(logfile, "--------------\n");
4864	0f8a249a	blueswir1	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4865	0f8a249a	blueswir1	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4866	0f8a249a	blueswir1	fprintf(logfile, "\n");
4867	cf495bcf	bellard	}
4868	7a3f1944	bellard	#endif
4869	7a3f1944	bellard	}
4870	7a3f1944	bellard
4871	2cfc5f17	ths	void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4872	7a3f1944	bellard	{
4873	2cfc5f17	ths	gen_intermediate_code_internal(tb, 0, env);
4874	7a3f1944	bellard	}
4875	7a3f1944	bellard
4876	2cfc5f17	ths	void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4877	7a3f1944	bellard	{
4878	2cfc5f17	ths	gen_intermediate_code_internal(tb, 1, env);
4879	7a3f1944	bellard	}
4880	7a3f1944	bellard
4881	c48fcb47	blueswir1	void gen_intermediate_code_init(CPUSPARCState *env)
4882	e80cfcfc	bellard	{
4883	f5069b26	blueswir1	unsigned int i;
4884	c48fcb47	blueswir1	static int inited;
4885	f5069b26	blueswir1	static const char * const gregnames[8] = {
4886	f5069b26	blueswir1	NULL, // g0 not used
4887	f5069b26	blueswir1	"g1",
4888	f5069b26	blueswir1	"g2",
4889	f5069b26	blueswir1	"g3",
4890	f5069b26	blueswir1	"g4",
4891	f5069b26	blueswir1	"g5",
4892	f5069b26	blueswir1	"g6",
4893	f5069b26	blueswir1	"g7",
4894	f5069b26	blueswir1	};
4895	aaed909a	bellard
4896	1a2fb1c0	blueswir1	/* init various static tables */
4897	1a2fb1c0	blueswir1	if (!inited) {
4898	1a2fb1c0	blueswir1	inited = 1;
4899	1a2fb1c0	blueswir1
4900	1a2fb1c0	blueswir1	cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4901	db4a4ea4	blueswir1	cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4902	db4a4ea4	blueswir1	offsetof(CPUState, regwptr),
4903	db4a4ea4	blueswir1	"regwptr");
4904	1a2fb1c0	blueswir1	#ifdef TARGET_SPARC64
4905	dc99a3f2	blueswir1	cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4906	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, xcc),
4907	dc99a3f2	blueswir1	"xcc");
4908	1a2fb1c0	blueswir1	#endif
4909	7c60cc4b	bellard	cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4910	77f193da	blueswir1	TCG_AREG0, offsetof(CPUState, cond),
4911	77f193da	blueswir1	"cond");
4912	dc99a3f2	blueswir1	cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4913	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_src),
4914	dc99a3f2	blueswir1	"cc_src");
4915	d9bdab86	blueswir1	cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4916	d9bdab86	blueswir1	offsetof(CPUState, cc_src2),
4917	d9bdab86	blueswir1	"cc_src2");
4918	dc99a3f2	blueswir1	cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4919	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, cc_dst),
4920	dc99a3f2	blueswir1	"cc_dst");
4921	dc99a3f2	blueswir1	cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4922	dc99a3f2	blueswir1	TCG_AREG0, offsetof(CPUState, psr),
4923	dc99a3f2	blueswir1	"psr");
4924	87e92502	blueswir1	cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4925	87e92502	blueswir1	TCG_AREG0, offsetof(CPUState, fsr),
4926	87e92502	blueswir1	"fsr");
4927	48d5c82b	blueswir1	cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4928	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, pc),
4929	48d5c82b	blueswir1	"pc");
4930	48d5c82b	blueswir1	cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4931	48d5c82b	blueswir1	TCG_AREG0, offsetof(CPUState, npc),
4932	48d5c82b	blueswir1	"npc");
4933	f5069b26	blueswir1	for (i = 1; i < 8; i++)
4934	f5069b26	blueswir1	cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4935	f5069b26	blueswir1	offsetof(CPUState, gregs[i]),
4936	f5069b26	blueswir1	gregnames[i]);
4937	c9e03d8f	blueswir1	/* register helpers */
4938	c9e03d8f	blueswir1
4939	c9e03d8f	blueswir1	#undef DEF_HELPER
4940	c9e03d8f	blueswir1	#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
4941	c9e03d8f	blueswir1	#include "helper.h"
4942	1a2fb1c0	blueswir1	}
4943	658138bc	bellard	}
4944	d2856f1a	aurel32
4945	d2856f1a	aurel32	void gen_pc_load(CPUState env, TranslationBlock tb,
4946	d2856f1a	aurel32	unsigned long searched_pc, int pc_pos, void *puc)
4947	d2856f1a	aurel32	{
4948	d2856f1a	aurel32	target_ulong npc;
4949	d2856f1a	aurel32	env->pc = gen_opc_pc[pc_pos];
4950	d2856f1a	aurel32	npc = gen_opc_npc[pc_pos];
4951	d2856f1a	aurel32	if (npc == 1) {
4952	d2856f1a	aurel32	/* dynamic NPC: already stored */
4953	d2856f1a	aurel32	} else if (npc == 2) {
4954	d2856f1a	aurel32	target_ulong t2 = (target_ulong)(unsigned long)puc;
4955	d2856f1a	aurel32	/* jump PC: use T2 and the jump targets of the translation */
4956	d2856f1a	aurel32	if (t2)
4957	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[0];
4958	d2856f1a	aurel32	else
4959	d2856f1a	aurel32	env->npc = gen_opc_jump_pc[1];
4960	d2856f1a	aurel32	} else {
4961	d2856f1a	aurel32	env->npc = npc;
4962	d2856f1a	aurel32	}
4963	d2856f1a	aurel32	}

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