Revision 105a1f04
| b/target-sparc/translate.c | ||
|---|---|---|
| 713 | 713 |
|
| 714 | 714 |
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
| 715 | 715 |
{
|
| 716 |
TCGv r_temp, r_temp2;
|
|
| 716 |
TCGv r_temp; |
|
| 717 | 717 |
int l1; |
| 718 | 718 |
|
| 719 | 719 |
l1 = gen_new_label(); |
| 720 | 720 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
| 721 |
r_temp2 = tcg_temp_new(TCG_TYPE_I32); |
|
| 722 | 721 |
|
| 723 | 722 |
/* old op: |
| 724 | 723 |
if (!(env->y & 1)) |
| 725 | 724 |
T1 = 0; |
| 726 | 725 |
*/ |
| 727 | 726 |
tcg_gen_mov_tl(cpu_cc_src, src1); |
| 728 |
tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 729 |
tcg_gen_trunc_tl_i32(r_temp2, r_temp); |
|
| 730 |
tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); |
|
| 727 |
tcg_gen_ld_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 728 |
tcg_gen_andi_tl(r_temp, r_temp, 0x1); |
|
| 731 | 729 |
tcg_gen_mov_tl(cpu_cc_src2, src2); |
| 732 |
tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
|
|
| 730 |
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
|
| 733 | 731 |
tcg_gen_movi_tl(cpu_cc_src2, 0); |
| 734 | 732 |
gen_set_label(l1); |
| 735 | 733 |
|
| 736 | 734 |
// b2 = T0 & 1; |
| 737 | 735 |
// env->y = (b2 << 31) | (env->y >> 1); |
| 738 |
tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src); |
|
| 739 |
tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); |
|
| 740 |
tcg_gen_shli_i32(r_temp2, r_temp2, 31); |
|
| 741 |
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 742 |
tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1); |
|
| 743 |
tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2); |
|
| 744 |
tcg_temp_free(r_temp2); |
|
| 745 |
tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 736 |
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); |
|
| 737 |
tcg_gen_shli_tl(r_temp, r_temp, 31); |
|
| 738 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 739 |
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 1); |
|
| 740 |
tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
|
| 741 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 746 | 742 |
|
| 747 | 743 |
// b1 = N ^ V; |
| 748 | 744 |
gen_mov_reg_N(cpu_tmp0, cpu_psr); |
| ... | ... | |
| 778 | 774 |
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
| 779 | 775 |
|
| 780 | 776 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 781 |
tcg_gen_trunc_i64_i32(r_temp, r_temp); |
|
| 782 |
tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 777 |
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
|
| 783 | 778 |
tcg_temp_free(r_temp); |
| 779 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); |
|
| 780 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 784 | 781 |
#ifdef TARGET_SPARC64 |
| 785 | 782 |
tcg_gen_mov_i64(dst, r_temp2); |
| 786 | 783 |
#else |
| ... | ... | |
| 801 | 798 |
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
| 802 | 799 |
|
| 803 | 800 |
tcg_gen_shri_i64(r_temp, r_temp2, 32); |
| 804 |
tcg_gen_trunc_i64_i32(r_temp, r_temp); |
|
| 805 |
tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 801 |
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
|
| 806 | 802 |
tcg_temp_free(r_temp); |
| 803 |
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff); |
|
| 804 |
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, y)); |
|
| 807 | 805 |
#ifdef TARGET_SPARC64 |
| 808 | 806 |
tcg_gen_mov_i64(dst, r_temp2); |
| 809 | 807 |
#else |
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