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1 | 02645926 | balrog | /*
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2 | 02645926 | balrog | * TI OMAP on-chip I2C controller. Only "new I2C" mode supported.
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3 | 02645926 | balrog | *
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4 | 02645926 | balrog | * Copyright (C) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | 02645926 | balrog | *
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6 | 02645926 | balrog | * This program is free software; you can redistribute it and/or
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7 | 02645926 | balrog | * modify it under the terms of the GNU General Public License as
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8 | 02645926 | balrog | * published by the Free Software Foundation; either version 2 of
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9 | 02645926 | balrog | * the License, or (at your option) any later version.
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10 | 02645926 | balrog | *
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11 | 02645926 | balrog | * This program is distributed in the hope that it will be useful,
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12 | 02645926 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 02645926 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 02645926 | balrog | * GNU General Public License for more details.
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15 | 02645926 | balrog | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | 02645926 | balrog | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "i2c.h" |
21 | 87ecb68b | pbrook | #include "omap.h" |
22 | 02645926 | balrog | |
23 | 02645926 | balrog | struct omap_i2c_s {
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24 | 02645926 | balrog | qemu_irq irq; |
25 | 02645926 | balrog | qemu_irq drq[2];
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26 | 02645926 | balrog | i2c_bus *bus; |
27 | 02645926 | balrog | |
28 | 29885477 | balrog | uint8_t revision; |
29 | 02645926 | balrog | uint8_t mask; |
30 | 02645926 | balrog | uint16_t stat; |
31 | 02645926 | balrog | uint16_t dma; |
32 | 02645926 | balrog | uint16_t count; |
33 | 02645926 | balrog | int count_cur;
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34 | 02645926 | balrog | uint32_t fifo; |
35 | 02645926 | balrog | int rxlen;
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36 | 02645926 | balrog | int txlen;
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37 | 02645926 | balrog | uint16_t control; |
38 | 02645926 | balrog | uint16_t addr[2];
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39 | 02645926 | balrog | uint8_t divider; |
40 | 02645926 | balrog | uint8_t times[2];
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41 | 02645926 | balrog | uint16_t test; |
42 | 02645926 | balrog | }; |
43 | 02645926 | balrog | |
44 | 29885477 | balrog | #define OMAP2_INTR_REV 0x34 |
45 | 29885477 | balrog | #define OMAP2_GC_REV 0x34 |
46 | 29885477 | balrog | |
47 | 02645926 | balrog | static void omap_i2c_interrupts_update(struct omap_i2c_s *s) |
48 | 02645926 | balrog | { |
49 | 02645926 | balrog | qemu_set_irq(s->irq, s->stat & s->mask); |
50 | 02645926 | balrog | if ((s->dma >> 15) & 1) /* RDMA_EN */ |
51 | 02645926 | balrog | qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ |
52 | 02645926 | balrog | if ((s->dma >> 7) & 1) /* XDMA_EN */ |
53 | 02645926 | balrog | qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ |
54 | 02645926 | balrog | } |
55 | 02645926 | balrog | |
56 | 02645926 | balrog | static void omap_i2c_fifo_run(struct omap_i2c_s *s) |
57 | 02645926 | balrog | { |
58 | 02645926 | balrog | int ack = 1; |
59 | 02645926 | balrog | |
60 | 02645926 | balrog | if (!i2c_bus_busy(s->bus))
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61 | 02645926 | balrog | return;
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62 | 02645926 | balrog | |
63 | 02645926 | balrog | if ((s->control >> 2) & 1) { /* RM */ |
64 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
65 | 02645926 | balrog | i2c_end_transfer(s->bus); |
66 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
67 | 02645926 | balrog | s->count_cur = s->count; |
68 | 29885477 | balrog | s->txlen = 0;
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69 | 02645926 | balrog | } else if ((s->control >> 9) & 1) { /* TRX */ |
70 | 02645926 | balrog | while (ack && s->txlen)
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71 | 02645926 | balrog | ack = (i2c_send(s->bus, |
72 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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73 | 02645926 | balrog | 0xff) >= 0); |
74 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
75 | 02645926 | balrog | } else {
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76 | 02645926 | balrog | while (s->rxlen < 4) |
77 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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78 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
79 | 02645926 | balrog | } |
80 | 02645926 | balrog | } else {
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81 | 02645926 | balrog | if ((s->control >> 9) & 1) { /* TRX */ |
82 | 02645926 | balrog | while (ack && s->count_cur && s->txlen) {
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83 | 02645926 | balrog | ack = (i2c_send(s->bus, |
84 | 02645926 | balrog | (s->fifo >> ((-- s->txlen) << 3)) &
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85 | 02645926 | balrog | 0xff) >= 0); |
86 | 02645926 | balrog | s->count_cur --; |
87 | 02645926 | balrog | } |
88 | 02645926 | balrog | if (ack && s->count_cur)
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89 | 02645926 | balrog | s->stat |= 1 << 4; /* XRDY */ |
90 | 827df9f3 | balrog | else
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91 | 827df9f3 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
92 | 02645926 | balrog | if (!s->count_cur) {
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93 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
94 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
95 | 02645926 | balrog | } |
96 | 02645926 | balrog | } else {
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97 | 02645926 | balrog | while (s->count_cur && s->rxlen < 4) { |
98 | 02645926 | balrog | s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3);
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99 | 02645926 | balrog | s->count_cur --; |
100 | 02645926 | balrog | } |
101 | 02645926 | balrog | if (s->rxlen)
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102 | 02645926 | balrog | s->stat |= 1 << 3; /* RRDY */ |
103 | 827df9f3 | balrog | else
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104 | 827df9f3 | balrog | s->stat &= ~(1 << 3); /* RRDY */ |
105 | 02645926 | balrog | } |
106 | 02645926 | balrog | if (!s->count_cur) {
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107 | 02645926 | balrog | if ((s->control >> 1) & 1) { /* STP */ |
108 | 02645926 | balrog | i2c_end_transfer(s->bus); |
109 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
110 | 02645926 | balrog | s->count_cur = s->count; |
111 | 29885477 | balrog | s->txlen = 0;
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112 | 02645926 | balrog | } else {
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113 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
114 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
115 | 02645926 | balrog | } |
116 | 02645926 | balrog | } |
117 | 02645926 | balrog | } |
118 | 02645926 | balrog | |
119 | 02645926 | balrog | s->stat |= (!ack) << 1; /* NACK */ |
120 | 02645926 | balrog | if (!ack)
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121 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
122 | 02645926 | balrog | } |
123 | 02645926 | balrog | |
124 | 02645926 | balrog | void omap_i2c_reset(struct omap_i2c_s *s) |
125 | 02645926 | balrog | { |
126 | 02645926 | balrog | s->mask = 0;
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127 | 02645926 | balrog | s->stat = 0;
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128 | 02645926 | balrog | s->dma = 0;
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129 | 02645926 | balrog | s->count = 0;
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130 | 02645926 | balrog | s->count_cur = 0;
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131 | 02645926 | balrog | s->fifo = 0;
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132 | 02645926 | balrog | s->rxlen = 0;
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133 | 02645926 | balrog | s->txlen = 0;
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134 | 02645926 | balrog | s->control = 0;
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135 | 02645926 | balrog | s->addr[0] = 0; |
136 | 02645926 | balrog | s->addr[1] = 0; |
137 | 02645926 | balrog | s->divider = 0;
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138 | 02645926 | balrog | s->times[0] = 0; |
139 | 02645926 | balrog | s->times[1] = 0; |
140 | 02645926 | balrog | s->test = 0;
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141 | 02645926 | balrog | } |
142 | 02645926 | balrog | |
143 | c227f099 | Anthony Liguori | static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr) |
144 | 02645926 | balrog | { |
145 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
146 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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147 | 02645926 | balrog | uint16_t ret; |
148 | 02645926 | balrog | |
149 | 02645926 | balrog | switch (offset) {
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150 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
151 | 29885477 | balrog | return s->revision; /* REV */ |
152 | 02645926 | balrog | |
153 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
154 | 02645926 | balrog | return s->mask;
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155 | 02645926 | balrog | |
156 | 02645926 | balrog | case 0x08: /* I2C_STAT */ |
157 | 02645926 | balrog | return s->stat | (i2c_bus_busy(s->bus) << 12); |
158 | 02645926 | balrog | |
159 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
160 | 29885477 | balrog | if (s->revision >= OMAP2_INTR_REV)
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161 | 29885477 | balrog | break;
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162 | 02645926 | balrog | ret = ffs(s->stat & s->mask); |
163 | 02645926 | balrog | if (ret)
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164 | 02645926 | balrog | s->stat ^= 1 << (ret - 1); |
165 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
166 | 02645926 | balrog | return ret;
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167 | 02645926 | balrog | |
168 | 29885477 | balrog | case 0x10: /* I2C_SYSS */ |
169 | 29885477 | balrog | return (s->control >> 15) & 1; /* I2C_EN */ |
170 | 29885477 | balrog | |
171 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
172 | 02645926 | balrog | return s->dma;
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173 | 02645926 | balrog | |
174 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
175 | 02645926 | balrog | return s->count_cur; /* DCOUNT */ |
176 | 02645926 | balrog | |
177 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
178 | 02645926 | balrog | ret = 0;
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179 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
180 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 8; |
181 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 0; |
182 | 02645926 | balrog | } else {
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183 | 02645926 | balrog | ret |= ((s->fifo >> 8) & 0xff) << 8; |
184 | 02645926 | balrog | ret |= ((s->fifo >> 0) & 0xff) << 0; |
185 | 02645926 | balrog | } |
186 | 02645926 | balrog | if (s->rxlen == 1) { |
187 | 02645926 | balrog | s->stat |= 1 << 15; /* SBD */ |
188 | 02645926 | balrog | s->rxlen = 0;
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189 | 02645926 | balrog | } else if (s->rxlen > 1) { |
190 | 02645926 | balrog | if (s->rxlen > 2) |
191 | 02645926 | balrog | s->fifo >>= 16;
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192 | 02645926 | balrog | s->rxlen -= 2;
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193 | 02645926 | balrog | } else
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194 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */;
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195 | 02645926 | balrog | if (!s->rxlen) {
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196 | 29885477 | balrog | s->stat &= ~(1 << 3); /* RRDY */ |
197 | 02645926 | balrog | if (((s->control >> 10) & 1) && /* MST */ |
198 | 02645926 | balrog | ((~s->control >> 9) & 1)) { /* TRX */ |
199 | 02645926 | balrog | s->stat |= 1 << 2; /* ARDY */ |
200 | 02645926 | balrog | s->control &= ~(1 << 10); /* MST */ |
201 | 02645926 | balrog | } |
202 | 02645926 | balrog | } |
203 | 02645926 | balrog | s->stat &= ~(1 << 11); /* ROVR */ |
204 | 02645926 | balrog | omap_i2c_fifo_run(s); |
205 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
206 | 02645926 | balrog | return ret;
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207 | 02645926 | balrog | |
208 | 29885477 | balrog | case 0x20: /* I2C_SYSC */ |
209 | 29885477 | balrog | return 0; |
210 | 29885477 | balrog | |
211 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
212 | 02645926 | balrog | return s->control;
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213 | 02645926 | balrog | |
214 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
215 | 02645926 | balrog | return s->addr[0]; |
216 | 02645926 | balrog | |
217 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
218 | 02645926 | balrog | return s->addr[1]; |
219 | 02645926 | balrog | |
220 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
221 | 02645926 | balrog | return s->divider;
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222 | 02645926 | balrog | |
223 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
224 | 02645926 | balrog | return s->times[0]; |
225 | 02645926 | balrog | |
226 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
227 | 02645926 | balrog | return s->times[1]; |
228 | 02645926 | balrog | |
229 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
230 | 02645926 | balrog | if (s->test & (1 << 15)) { /* ST_EN */ |
231 | 02645926 | balrog | s->test ^= 0xa;
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232 | 02645926 | balrog | return s->test;
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233 | 02645926 | balrog | } else
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234 | 02645926 | balrog | return s->test & ~0x300f; |
235 | 02645926 | balrog | } |
236 | 02645926 | balrog | |
237 | 02645926 | balrog | OMAP_BAD_REG(addr); |
238 | 02645926 | balrog | return 0; |
239 | 02645926 | balrog | } |
240 | 02645926 | balrog | |
241 | c227f099 | Anthony Liguori | static void omap_i2c_write(void *opaque, target_phys_addr_t addr, |
242 | 02645926 | balrog | uint32_t value) |
243 | 02645926 | balrog | { |
244 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
245 | cf965d24 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
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246 | 02645926 | balrog | int nack;
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247 | 02645926 | balrog | |
248 | 02645926 | balrog | switch (offset) {
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249 | 02645926 | balrog | case 0x00: /* I2C_REV */ |
250 | 02645926 | balrog | case 0x0c: /* I2C_IV */ |
251 | 29885477 | balrog | case 0x10: /* I2C_SYSS */ |
252 | 29885477 | balrog | OMAP_RO_REG(addr); |
253 | 02645926 | balrog | return;
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254 | 02645926 | balrog | |
255 | 02645926 | balrog | case 0x04: /* I2C_IE */ |
256 | 29885477 | balrog | s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); |
257 | 29885477 | balrog | break;
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258 | 29885477 | balrog | |
259 | 29885477 | balrog | case 0x08: /* I2C_STAT */ |
260 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV) {
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261 | 29885477 | balrog | OMAP_RO_REG(addr); |
262 | 29885477 | balrog | return;
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263 | 29885477 | balrog | } |
264 | 29885477 | balrog | |
265 | 827df9f3 | balrog | /* RRDY and XRDY are reset by hardware. (in all versions???) */
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266 | 827df9f3 | balrog | s->stat &= ~(value & 0x27);
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267 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
268 | 02645926 | balrog | break;
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269 | 02645926 | balrog | |
270 | 02645926 | balrog | case 0x14: /* I2C_BUF */ |
271 | 02645926 | balrog | s->dma = value & 0x8080;
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272 | 02645926 | balrog | if (value & (1 << 15)) /* RDMA_EN */ |
273 | 02645926 | balrog | s->mask &= ~(1 << 3); /* RRDY_IE */ |
274 | 02645926 | balrog | if (value & (1 << 7)) /* XDMA_EN */ |
275 | 02645926 | balrog | s->mask &= ~(1 << 4); /* XRDY_IE */ |
276 | 02645926 | balrog | break;
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277 | 02645926 | balrog | |
278 | 02645926 | balrog | case 0x18: /* I2C_CNT */ |
279 | 02645926 | balrog | s->count = value; /* DCOUNT */
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280 | 02645926 | balrog | break;
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281 | 02645926 | balrog | |
282 | 02645926 | balrog | case 0x1c: /* I2C_DATA */ |
283 | 02645926 | balrog | if (s->txlen > 2) { |
284 | 02645926 | balrog | /* XXX: remote access (qualifier) error - what's that? */
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285 | 02645926 | balrog | break;
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286 | 02645926 | balrog | } |
287 | 02645926 | balrog | s->fifo <<= 16;
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288 | 02645926 | balrog | s->txlen += 2;
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289 | 02645926 | balrog | if (s->control & (1 << 14)) { /* BE */ |
290 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 8; |
291 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 0; |
292 | 02645926 | balrog | } else {
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293 | 02645926 | balrog | s->fifo |= ((value >> 0) & 0xff) << 8; |
294 | 02645926 | balrog | s->fifo |= ((value >> 8) & 0xff) << 0; |
295 | 02645926 | balrog | } |
296 | 02645926 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
297 | 02645926 | balrog | if (s->txlen > 2) |
298 | 02645926 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
299 | 02645926 | balrog | omap_i2c_fifo_run(s); |
300 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
301 | 02645926 | balrog | break;
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302 | 02645926 | balrog | |
303 | 29885477 | balrog | case 0x20: /* I2C_SYSC */ |
304 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV) {
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305 | 29885477 | balrog | OMAP_BAD_REG(addr); |
306 | 29885477 | balrog | return;
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307 | 29885477 | balrog | } |
308 | 29885477 | balrog | |
309 | 29885477 | balrog | if (value & 2) |
310 | 29885477 | balrog | omap_i2c_reset(s); |
311 | 29885477 | balrog | break;
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312 | 29885477 | balrog | |
313 | 02645926 | balrog | case 0x24: /* I2C_CON */ |
314 | 29885477 | balrog | s->control = value & 0xcf87;
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315 | 02645926 | balrog | if (~value & (1 << 15)) { /* I2C_EN */ |
316 | 29885477 | balrog | if (s->revision < OMAP2_INTR_REV)
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317 | 29885477 | balrog | omap_i2c_reset(s); |
318 | 02645926 | balrog | break;
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319 | 02645926 | balrog | } |
320 | 29885477 | balrog | if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */ |
321 | 827df9f3 | balrog | fprintf(stderr, "%s: I^2C slave mode not supported\n",
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322 | 827df9f3 | balrog | __FUNCTION__); |
323 | 02645926 | balrog | break;
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324 | 02645926 | balrog | } |
325 | 29885477 | balrog | if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */ |
326 | 827df9f3 | balrog | fprintf(stderr, "%s: 10-bit addressing mode not supported\n",
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327 | 827df9f3 | balrog | __FUNCTION__); |
328 | 02645926 | balrog | break;
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329 | 02645926 | balrog | } |
330 | 29885477 | balrog | if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */ |
331 | 02645926 | balrog | nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ |
332 | 02645926 | balrog | (~value >> 9) & 1); /* TRX */ |
333 | 02645926 | balrog | s->stat |= nack << 1; /* NACK */ |
334 | 02645926 | balrog | s->control &= ~(1 << 0); /* STT */ |
335 | 51fec3cc | balrog | s->fifo = 0;
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336 | 02645926 | balrog | if (nack)
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337 | 02645926 | balrog | s->control &= ~(1 << 1); /* STP */ |
338 | 29885477 | balrog | else {
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339 | 29885477 | balrog | s->count_cur = s->count; |
340 | 02645926 | balrog | omap_i2c_fifo_run(s); |
341 | 29885477 | balrog | } |
342 | 02645926 | balrog | omap_i2c_interrupts_update(s); |
343 | 02645926 | balrog | } |
344 | 02645926 | balrog | break;
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345 | 02645926 | balrog | |
346 | 02645926 | balrog | case 0x28: /* I2C_OA */ |
347 | 02645926 | balrog | s->addr[0] = value & 0x3ff; |
348 | 02645926 | balrog | break;
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349 | 02645926 | balrog | |
350 | 02645926 | balrog | case 0x2c: /* I2C_SA */ |
351 | 02645926 | balrog | s->addr[1] = value & 0x3ff; |
352 | 02645926 | balrog | break;
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353 | 02645926 | balrog | |
354 | 02645926 | balrog | case 0x30: /* I2C_PSC */ |
355 | 02645926 | balrog | s->divider = value; |
356 | 02645926 | balrog | break;
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357 | 02645926 | balrog | |
358 | 02645926 | balrog | case 0x34: /* I2C_SCLL */ |
359 | 02645926 | balrog | s->times[0] = value;
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360 | 02645926 | balrog | break;
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361 | 02645926 | balrog | |
362 | 02645926 | balrog | case 0x38: /* I2C_SCLH */ |
363 | 02645926 | balrog | s->times[1] = value;
|
364 | 02645926 | balrog | break;
|
365 | 02645926 | balrog | |
366 | 02645926 | balrog | case 0x3c: /* I2C_SYSTEST */ |
367 | 29885477 | balrog | s->test = value & 0xf80f;
|
368 | 29885477 | balrog | if (value & (1 << 11)) /* SBB */ |
369 | 29885477 | balrog | if (s->revision >= OMAP2_INTR_REV) {
|
370 | 29885477 | balrog | s->stat |= 0x3f;
|
371 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
372 | 29885477 | balrog | } |
373 | 02645926 | balrog | if (value & (1 << 15)) /* ST_EN */ |
374 | 827df9f3 | balrog | fprintf(stderr, "%s: System Test not supported\n", __FUNCTION__);
|
375 | 02645926 | balrog | break;
|
376 | 02645926 | balrog | |
377 | 02645926 | balrog | default:
|
378 | 02645926 | balrog | OMAP_BAD_REG(addr); |
379 | 02645926 | balrog | return;
|
380 | 02645926 | balrog | } |
381 | 02645926 | balrog | } |
382 | 02645926 | balrog | |
383 | c227f099 | Anthony Liguori | static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, |
384 | 29885477 | balrog | uint32_t value) |
385 | 29885477 | balrog | { |
386 | 29885477 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) opaque; |
387 | 29885477 | balrog | int offset = addr & OMAP_MPUI_REG_MASK;
|
388 | 29885477 | balrog | |
389 | 29885477 | balrog | switch (offset) {
|
390 | 29885477 | balrog | case 0x1c: /* I2C_DATA */ |
391 | 29885477 | balrog | if (s->txlen > 2) { |
392 | 29885477 | balrog | /* XXX: remote access (qualifier) error - what's that? */
|
393 | 29885477 | balrog | break;
|
394 | 29885477 | balrog | } |
395 | 29885477 | balrog | s->fifo <<= 8;
|
396 | 29885477 | balrog | s->txlen += 1;
|
397 | 29885477 | balrog | s->fifo |= value & 0xff;
|
398 | 29885477 | balrog | s->stat &= ~(1 << 10); /* XUDF */ |
399 | 29885477 | balrog | if (s->txlen > 2) |
400 | 29885477 | balrog | s->stat &= ~(1 << 4); /* XRDY */ |
401 | 29885477 | balrog | omap_i2c_fifo_run(s); |
402 | 29885477 | balrog | omap_i2c_interrupts_update(s); |
403 | 29885477 | balrog | break;
|
404 | 29885477 | balrog | |
405 | 29885477 | balrog | default:
|
406 | 29885477 | balrog | OMAP_BAD_REG(addr); |
407 | 29885477 | balrog | return;
|
408 | 29885477 | balrog | } |
409 | 29885477 | balrog | } |
410 | 29885477 | balrog | |
411 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_i2c_readfn[] = { |
412 | 02645926 | balrog | omap_badwidth_read16, |
413 | 02645926 | balrog | omap_i2c_read, |
414 | 02645926 | balrog | omap_badwidth_read16, |
415 | 02645926 | balrog | }; |
416 | 02645926 | balrog | |
417 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_i2c_writefn[] = { |
418 | 29885477 | balrog | omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
|
419 | 02645926 | balrog | omap_i2c_write, |
420 | 29885477 | balrog | omap_badwidth_write16, |
421 | 02645926 | balrog | }; |
422 | 02645926 | balrog | |
423 | c227f099 | Anthony Liguori | struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
|
424 | 02645926 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk clk) |
425 | 02645926 | balrog | { |
426 | 02645926 | balrog | int iomemtype;
|
427 | 02645926 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
428 | 02645926 | balrog | qemu_mallocz(sizeof(struct omap_i2c_s)); |
429 | 02645926 | balrog | |
430 | 29885477 | balrog | /* TODO: set a value greater or equal to real hardware */
|
431 | 29885477 | balrog | s->revision = 0x11;
|
432 | 02645926 | balrog | s->irq = irq; |
433 | 02645926 | balrog | s->drq[0] = dma[0]; |
434 | 02645926 | balrog | s->drq[1] = dma[1]; |
435 | 02e2da45 | Paul Brook | s->bus = i2c_init_bus(NULL, "i2c"); |
436 | 02645926 | balrog | omap_i2c_reset(s); |
437 | 02645926 | balrog | |
438 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_i2c_readfn, |
439 | 02645926 | balrog | omap_i2c_writefn, s); |
440 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
441 | 02645926 | balrog | |
442 | 02645926 | balrog | return s;
|
443 | 02645926 | balrog | } |
444 | 02645926 | balrog | |
445 | 29885477 | balrog | struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
446 | 29885477 | balrog | qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk) |
447 | 29885477 | balrog | { |
448 | 29885477 | balrog | int iomemtype;
|
449 | 29885477 | balrog | struct omap_i2c_s *s = (struct omap_i2c_s *) |
450 | 29885477 | balrog | qemu_mallocz(sizeof(struct omap_i2c_s)); |
451 | 29885477 | balrog | |
452 | 29885477 | balrog | s->revision = 0x34;
|
453 | 29885477 | balrog | s->irq = irq; |
454 | 29885477 | balrog | s->drq[0] = dma[0]; |
455 | 29885477 | balrog | s->drq[1] = dma[1]; |
456 | 02e2da45 | Paul Brook | s->bus = i2c_init_bus(NULL, "i2c"); |
457 | 29885477 | balrog | omap_i2c_reset(s); |
458 | 29885477 | balrog | |
459 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_i2c_readfn, |
460 | 29885477 | balrog | omap_i2c_writefn, s); |
461 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
462 | 29885477 | balrog | |
463 | 29885477 | balrog | return s;
|
464 | 29885477 | balrog | } |
465 | 29885477 | balrog | |
466 | 02645926 | balrog | i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
|
467 | 02645926 | balrog | { |
468 | 02645926 | balrog | return s->bus;
|
469 | 02645926 | balrog | } |