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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | 5fafdf24 | ths | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | 875cdcf6 | aliguori | #ifndef _EXEC_ALL_H_
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22 | 875cdcf6 | aliguori | #define _EXEC_ALL_H_
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23 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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24 | de9a95f0 | aurel32 | #define DEBUG_DISAS
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25 | b346ff46 | bellard | |
26 | b346ff46 | bellard | /* is_jmp field values */
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27 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
28 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
29 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
30 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
31 | b346ff46 | bellard | |
32 | 2e70f6ef | pbrook | typedef struct TranslationBlock TranslationBlock; |
33 | b346ff46 | bellard | |
34 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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35 | e83a8673 | edgar_igl | #define MAX_OP_PER_INSTR 64 |
36 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
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37 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
38 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
39 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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40 | b346ff46 | bellard | |
41 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
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42 | a208e54a | pbrook | single op may require several host instructions and regirster reloads.
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43 | a208e54a | pbrook | For now take a wild guess at 128 bytes, which should allow at least
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44 | a208e54a | pbrook | a couple of fixup instructions per argument. */
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45 | a208e54a | pbrook | #define TCG_MAX_OP_SIZE 128 |
46 | a208e54a | pbrook | |
47 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
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48 | b346ff46 | bellard | |
49 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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50 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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51 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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52 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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53 | 2e70f6ef | pbrook | extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
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54 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
55 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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56 | b346ff46 | bellard | |
57 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
58 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
59 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
60 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
61 | 3b46e624 | ths | |
62 | 79383c9c | blueswir1 | #include "qemu-log.h" |
63 | b346ff46 | bellard | |
64 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
65 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
66 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
67 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc); |
68 | d2856f1a | aurel32 | |
69 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
70 | 57fec1fe | bellard | void cpu_gen_init(void); |
71 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
72 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
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73 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
74 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
75 | 58fe2f10 | bellard | void *puc);
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76 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
77 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
78 | 58fe2f10 | bellard | void *puc);
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79 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
80 | 2e70f6ef | pbrook | void cpu_io_recompile(CPUState *env, void *retaddr); |
81 | 2e70f6ef | pbrook | TranslationBlock *tb_gen_code(CPUState *env, |
82 | 2e70f6ef | pbrook | target_ulong pc, target_ulong cs_base, int flags,
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83 | 2e70f6ef | pbrook | int cflags);
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84 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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85 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
86 | 00f82b8a | aurel32 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
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87 | 2e12669a | bellard | int is_cpu_write_access);
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88 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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89 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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90 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
91 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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92 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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93 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
94 | 4d7a0880 | blueswir1 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
95 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
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96 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
97 | 84b7b8e7 | bellard | { |
98 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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99 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
100 | 4d7a0880 | blueswir1 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
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101 | 84b7b8e7 | bellard | } |
102 | d4e8164f | bellard | |
103 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
104 | d4e8164f | bellard | |
105 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
106 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
107 | 4390df51 | bellard | |
108 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
109 | d4e8164f | bellard | |
110 | 4390df51 | bellard | /* estimated block size for TB allocation */
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111 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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112 | 4390df51 | bellard | according to the host CPU */
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113 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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114 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
115 | 4390df51 | bellard | #else
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116 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
117 | 4390df51 | bellard | #endif
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118 | 4390df51 | bellard | |
119 | 811d4cf4 | balrog | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
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120 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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121 | 4390df51 | bellard | #endif
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122 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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123 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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124 | d4e8164f | bellard | #endif
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125 | d4e8164f | bellard | |
126 | 2e70f6ef | pbrook | struct TranslationBlock {
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127 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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128 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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129 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
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130 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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131 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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132 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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133 | 2e70f6ef | pbrook | #define CF_COUNT_MASK 0x7fff |
134 | 2e70f6ef | pbrook | #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ |
135 | 58fe2f10 | bellard | |
136 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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137 | 4390df51 | bellard | /* next matching tb for physical address. */
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138 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
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139 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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140 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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141 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
142 | 5fafdf24 | ths | target_ulong page_addr[2];
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143 | 4390df51 | bellard | |
144 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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145 | d4e8164f | bellard | the code of this one. */
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146 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
147 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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148 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
149 | d4e8164f | bellard | #else
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150 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
151 | d4e8164f | bellard | #endif
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152 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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153 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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154 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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155 | d4e8164f | bellard | jmp_first */
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156 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
157 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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158 | 2e70f6ef | pbrook | uint32_t icount; |
159 | 2e70f6ef | pbrook | }; |
160 | d4e8164f | bellard | |
161 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
162 | b362e5e0 | pbrook | { |
163 | b362e5e0 | pbrook | target_ulong tmp; |
164 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
165 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
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166 | b362e5e0 | pbrook | } |
167 | b362e5e0 | pbrook | |
168 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
169 | d4e8164f | bellard | { |
170 | b362e5e0 | pbrook | target_ulong tmp; |
171 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
172 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
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173 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
174 | d4e8164f | bellard | } |
175 | d4e8164f | bellard | |
176 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
177 | 4390df51 | bellard | { |
178 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
179 | 4390df51 | bellard | } |
180 | 4390df51 | bellard | |
181 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
182 | 2e70f6ef | pbrook | void tb_free(TranslationBlock *tb);
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183 | 0124311e | bellard | void tb_flush(CPUState *env);
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184 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
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185 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
186 | 2e70f6ef | pbrook | void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
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187 | d4e8164f | bellard | |
188 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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189 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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190 | 26a5f13b | bellard | extern int code_gen_max_blocks; |
191 | d4e8164f | bellard | |
192 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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193 | 4390df51 | bellard | |
194 | 4390df51 | bellard | #if defined(__powerpc__)
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195 | 810260a8 | malc | extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr); |
196 | 810260a8 | malc | #define tb_set_jmp_target1 ppc_tb_set_jmp_target
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197 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
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198 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
199 | 4390df51 | bellard | { |
200 | 4390df51 | bellard | /* patch the branch destination */
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201 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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202 | 1235fc06 | ths | /* no need to flush icache explicitly */
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203 | 4390df51 | bellard | } |
204 | 811d4cf4 | balrog | #elif defined(__arm__)
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205 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
206 | 811d4cf4 | balrog | { |
207 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
208 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
209 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
210 | 811d4cf4 | balrog | |
211 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
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212 | 811d4cf4 | balrog | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; |
213 | 811d4cf4 | balrog | |
214 | 811d4cf4 | balrog | /* flush icache */
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215 | 811d4cf4 | balrog | _beg = jmp_addr; |
216 | 811d4cf4 | balrog | _end = jmp_addr + 4;
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217 | 811d4cf4 | balrog | _flg = 0;
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218 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
219 | 811d4cf4 | balrog | } |
220 | 4390df51 | bellard | #endif
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221 | d4e8164f | bellard | |
222 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
223 | 4cbb86e1 | bellard | int n, unsigned long addr) |
224 | 4cbb86e1 | bellard | { |
225 | 4cbb86e1 | bellard | unsigned long offset; |
226 | 4cbb86e1 | bellard | |
227 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
228 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
229 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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230 | 4cbb86e1 | bellard | if (offset != 0xffff) |
231 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
232 | 4cbb86e1 | bellard | } |
233 | 4cbb86e1 | bellard | |
234 | d4e8164f | bellard | #else
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235 | d4e8164f | bellard | |
236 | d4e8164f | bellard | /* set the jump target */
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237 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
238 | d4e8164f | bellard | int n, unsigned long addr) |
239 | d4e8164f | bellard | { |
240 | 95f7652d | bellard | tb->tb_next[n] = addr; |
241 | d4e8164f | bellard | } |
242 | d4e8164f | bellard | |
243 | d4e8164f | bellard | #endif
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244 | d4e8164f | bellard | |
245 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
246 | d4e8164f | bellard | TranslationBlock *tb_next) |
247 | d4e8164f | bellard | { |
248 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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249 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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250 | cf25629d | bellard | /* patch the native jump address */
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251 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
252 | 3b46e624 | ths | |
253 | cf25629d | bellard | /* add in TB jmp circular list */
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254 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
255 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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256 | cf25629d | bellard | } |
257 | d4e8164f | bellard | } |
258 | d4e8164f | bellard | |
259 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
260 | a513fe19 | bellard | |
261 | d549f7d9 | bellard | #if defined(_WIN32)
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262 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
263 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
264 | d549f7d9 | bellard | #elif defined(__APPLE__)
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265 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
266 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
267 | d549f7d9 | bellard | #else
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268 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
269 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
270 | d549f7d9 | bellard | #endif
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271 | d549f7d9 | bellard | |
272 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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273 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
274 | 75913b72 | bellard | |
275 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
276 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
277 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
278 | 33417e70 | bellard | |
279 | d5975363 | pbrook | #include "qemu-lock.h" |
280 | d4e8164f | bellard | |
281 | d4e8164f | bellard | extern spinlock_t tb_lock;
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282 | d4e8164f | bellard | |
283 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
284 | 6e59c1db | bellard | |
285 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
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286 | 6e59c1db | bellard | |
287 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
288 | 6e59c1db | bellard | void *retaddr);
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289 | 6e59c1db | bellard | |
290 | 79383c9c | blueswir1 | #include "softmmu_defs.h" |
291 | 79383c9c | blueswir1 | |
292 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
293 | 6e59c1db | bellard | #define MEMSUFFIX _code
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294 | 6e59c1db | bellard | #define env cpu_single_env
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295 | 6e59c1db | bellard | |
296 | 6e59c1db | bellard | #define DATA_SIZE 1 |
297 | 6e59c1db | bellard | #include "softmmu_header.h" |
298 | 6e59c1db | bellard | |
299 | 6e59c1db | bellard | #define DATA_SIZE 2 |
300 | 6e59c1db | bellard | #include "softmmu_header.h" |
301 | 6e59c1db | bellard | |
302 | 6e59c1db | bellard | #define DATA_SIZE 4 |
303 | 6e59c1db | bellard | #include "softmmu_header.h" |
304 | 6e59c1db | bellard | |
305 | c27004ec | bellard | #define DATA_SIZE 8 |
306 | c27004ec | bellard | #include "softmmu_header.h" |
307 | c27004ec | bellard | |
308 | 6e59c1db | bellard | #undef ACCESS_TYPE
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309 | 6e59c1db | bellard | #undef MEMSUFFIX
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310 | 6e59c1db | bellard | #undef env
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311 | 6e59c1db | bellard | |
312 | 6e59c1db | bellard | #endif
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313 | 4390df51 | bellard | |
314 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
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315 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
316 | 4390df51 | bellard | { |
317 | 4390df51 | bellard | return addr;
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318 | 4390df51 | bellard | } |
319 | 4390df51 | bellard | #else
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320 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
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321 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
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322 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
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323 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
324 | 4390df51 | bellard | { |
325 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
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326 | 4390df51 | bellard | |
327 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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328 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
329 | 551bd27f | ths | if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
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330 | 551bd27f | ths | (addr & TARGET_PAGE_MASK))) { |
331 | c27004ec | bellard | ldub_code(addr); |
332 | c27004ec | bellard | } |
333 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
334 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
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335 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
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336 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 1, 0, 4); |
337 | 6c36d3fa | blueswir1 | #else
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338 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
339 | 6c36d3fa | blueswir1 | #endif
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340 | 4390df51 | bellard | } |
341 | 4d7a0880 | blueswir1 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
342 | 4390df51 | bellard | } |
343 | 2e70f6ef | pbrook | |
344 | bf20dc07 | ths | /* Deterministic execution requires that IO only be performed on the last
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345 | 2e70f6ef | pbrook | instruction of a TB so that interrupts take effect immediately. */
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346 | 2e70f6ef | pbrook | static inline int can_do_io(CPUState *env) |
347 | 2e70f6ef | pbrook | { |
348 | 2e70f6ef | pbrook | if (!use_icount)
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349 | 2e70f6ef | pbrook | return 1; |
350 | 2e70f6ef | pbrook | |
351 | 2e70f6ef | pbrook | /* If not executing code then assume we are ok. */
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352 | 2e70f6ef | pbrook | if (!env->current_tb)
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353 | 2e70f6ef | pbrook | return 1; |
354 | 2e70f6ef | pbrook | |
355 | 2e70f6ef | pbrook | return env->can_do_io != 0; |
356 | 2e70f6ef | pbrook | } |
357 | 4390df51 | bellard | #endif
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358 | 9df217a3 | bellard | |
359 | 9df217a3 | bellard | #ifdef USE_KQEMU
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360 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
361 | f32fc648 | bellard | |
362 | da260249 | bellard | #define MSR_QPI_COMMBASE 0xfabe0010 |
363 | da260249 | bellard | |
364 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
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365 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
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366 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
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367 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
368 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
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369 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
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370 | da260249 | bellard | void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
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371 | da260249 | bellard | ram_addr_t phys_offset); |
372 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
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373 | f32fc648 | bellard | void kqemu_record_dump(void); |
374 | 9df217a3 | bellard | |
375 | da260249 | bellard | extern uint32_t kqemu_comm_base;
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376 | da260249 | bellard | |
377 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
378 | 9df217a3 | bellard | { |
379 | 9df217a3 | bellard | return(env->kqemu_enabled &&
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380 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
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381 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
382 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
383 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
384 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
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385 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
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386 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
387 | 9df217a3 | bellard | } |
388 | 9df217a3 | bellard | |
389 | 9df217a3 | bellard | #endif
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390 | 875cdcf6 | aliguori | #endif |