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/*
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 * QEMU Cirrus CLGD 54xx VGA Emulator.
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 *
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 * Copyright (c) 2004 Fabrice Bellard
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 * Copyright (c) 2004 Makoto Suzuki (suzu)
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * Reference: Finn Thogersons' VGADOC4b
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 *   available at http://home.worldonline.dk/~finth/
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 */
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "console.h"
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#include "vga_int.h"
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#include "kvm.h"
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/*
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 * TODO:
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 *    - destination write mask support not complete (bits 5..7)
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 *    - optimize linear mappings
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 *    - optimize bitblt functions
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 */
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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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/***************************************
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 *
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 *  definitions
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 *
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 ***************************************/
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#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
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// ID
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#define CIRRUS_ID_CLGD5422  (0x23<<2)
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#define CIRRUS_ID_CLGD5426  (0x24<<2)
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#define CIRRUS_ID_CLGD5424  (0x25<<2)
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#define CIRRUS_ID_CLGD5428  (0x26<<2)
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#define CIRRUS_ID_CLGD5430  (0x28<<2)
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#define CIRRUS_ID_CLGD5434  (0x2A<<2)
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#define CIRRUS_ID_CLGD5436  (0x2B<<2)
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#define CIRRUS_ID_CLGD5446  (0x2E<<2)
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA            0x00
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#define CIRRUS_SR7_BPP_SVGA           0x01
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#define CIRRUS_SR7_BPP_MASK           0x0e
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#define CIRRUS_SR7_BPP_8              0x00
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#define CIRRUS_SR7_BPP_16_DOUBLEVCLK  0x02
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#define CIRRUS_SR7_BPP_24             0x04
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#define CIRRUS_SR7_BPP_16             0x06
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#define CIRRUS_SR7_BPP_32             0x08
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#define CIRRUS_SR7_ISAADDR_MASK       0xe0
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// sequencer 0x0f
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#define CIRRUS_MEMSIZE_512k        0x08
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#define CIRRUS_MEMSIZE_1M          0x10
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#define CIRRUS_MEMSIZE_2M          0x18
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#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80        // bank switching is enabled.
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// sequencer 0x12
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#define CIRRUS_CURSOR_SHOW         0x01
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#define CIRRUS_CURSOR_HIDDENPEL    0x02
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#define CIRRUS_CURSOR_LARGE        0x04        // 64x64 if set, 32x32 if clear
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// sequencer 0x17
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#define CIRRUS_BUSTYPE_VLBFAST   0x10
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#define CIRRUS_BUSTYPE_PCI       0x20
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#define CIRRUS_BUSTYPE_VLBSLOW   0x30
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#define CIRRUS_BUSTYPE_ISA       0x38
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#define CIRRUS_MMIO_ENABLE       0x04
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#define CIRRUS_MMIO_USE_PCIADDR  0x40        // 0xb8000 if cleared.
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#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
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// control 0x0b
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#define CIRRUS_BANKING_DUAL             0x01
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#define CIRRUS_BANKING_GRANULARITY_16K  0x20        // set:16k, clear:4k
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// control 0x30
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#define CIRRUS_BLTMODE_BACKWARDS        0x01
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#define CIRRUS_BLTMODE_MEMSYSDEST       0x02
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#define CIRRUS_BLTMODE_MEMSYSSRC        0x04
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#define CIRRUS_BLTMODE_TRANSPARENTCOMP  0x08
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#define CIRRUS_BLTMODE_PATTERNCOPY      0x40
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#define CIRRUS_BLTMODE_COLOREXPAND      0x80
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#define CIRRUS_BLTMODE_PIXELWIDTHMASK   0x30
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#define CIRRUS_BLTMODE_PIXELWIDTH8      0x00
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#define CIRRUS_BLTMODE_PIXELWIDTH16     0x10
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#define CIRRUS_BLTMODE_PIXELWIDTH24     0x20
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#define CIRRUS_BLTMODE_PIXELWIDTH32     0x30
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// control 0x31
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#define CIRRUS_BLT_BUSY                 0x01
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#define CIRRUS_BLT_START                0x02
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#define CIRRUS_BLT_RESET                0x04
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#define CIRRUS_BLT_FIFOUSED             0x10
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#define CIRRUS_BLT_AUTOSTART            0x80
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// control 0x32
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#define CIRRUS_ROP_0                    0x00
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#define CIRRUS_ROP_SRC_AND_DST          0x05
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#define CIRRUS_ROP_NOP                  0x06
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#define CIRRUS_ROP_SRC_AND_NOTDST       0x09
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#define CIRRUS_ROP_NOTDST               0x0b
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#define CIRRUS_ROP_SRC                  0x0d
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#define CIRRUS_ROP_1                    0x0e
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#define CIRRUS_ROP_NOTSRC_AND_DST       0x50
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#define CIRRUS_ROP_SRC_XOR_DST          0x59
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#define CIRRUS_ROP_SRC_OR_DST           0x6d
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#define CIRRUS_ROP_NOTSRC_OR_NOTDST     0x90
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#define CIRRUS_ROP_SRC_NOTXOR_DST       0x95
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#define CIRRUS_ROP_SRC_OR_NOTDST        0xad
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#define CIRRUS_ROP_NOTSRC               0xd0
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#define CIRRUS_ROP_NOTSRC_OR_DST        0xd6
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST    0xda
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#define CIRRUS_ROP_NOP_INDEX 2
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#define CIRRUS_ROP_SRC_INDEX 5
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL        0x04
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#define CIRRUS_BLTMODEEXT_COLOREXPINV      0x02
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR        0x00        // dword
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#define CIRRUS_MMIO_BLTFGCOLOR        0x04        // dword
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#define CIRRUS_MMIO_BLTWIDTH          0x08        // word
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#define CIRRUS_MMIO_BLTHEIGHT         0x0a        // word
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#define CIRRUS_MMIO_BLTDESTPITCH      0x0c        // word
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#define CIRRUS_MMIO_BLTSRCPITCH       0x0e        // word
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#define CIRRUS_MMIO_BLTDESTADDR       0x10        // dword
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#define CIRRUS_MMIO_BLTSRCADDR        0x14        // dword
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#define CIRRUS_MMIO_BLTWRITEMASK      0x17        // byte
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#define CIRRUS_MMIO_BLTMODE           0x18        // byte
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#define CIRRUS_MMIO_BLTROP            0x1a        // byte
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#define CIRRUS_MMIO_BLTMODEEXT        0x1b        // byte
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c        // word?
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#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20        // word?
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#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24        // word
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#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26        // word
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#define CIRRUS_MMIO_LINEARDRAW_END_X  0x28        // word
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#define CIRRUS_MMIO_LINEARDRAW_END_Y  0x2a        // word
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e        // byte
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#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f        // byte
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#define CIRRUS_MMIO_BRESENHAM_K1      0x30        // word
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#define CIRRUS_MMIO_BRESENHAM_K3      0x32        // word
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#define CIRRUS_MMIO_BRESENHAM_ERROR   0x34        // word
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#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36        // word
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#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38        // byte
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#define CIRRUS_MMIO_LINEDRAW_MODE     0x39        // byte
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#define CIRRUS_MMIO_BLTSTATUS         0x40        // byte
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// PCI 0x00: vendor, 0x02: device
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#define PCI_VENDOR_CIRRUS             0x1013
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#define PCI_DEVICE_CLGD5462           0x00d0
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#define PCI_DEVICE_CLGD5465           0x00d6
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// PCI 0x04: command(word), 0x06(word): status
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#define PCI_COMMAND_IOACCESS                0x0001
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#define PCI_COMMAND_MEMACCESS               0x0002
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#define PCI_COMMAND_BUSMASTER               0x0004
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#define PCI_COMMAND_SPECIALCYCLE            0x0008
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#define PCI_COMMAND_MEMWRITEINVALID         0x0010
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#define PCI_COMMAND_PALETTESNOOPING         0x0020
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#define PCI_COMMAND_PARITYDETECTION         0x0040
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#define PCI_COMMAND_ADDRESSDATASTEPPING     0x0080
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#define PCI_COMMAND_SERR                    0x0100
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#define PCI_COMMAND_BACKTOBACKTRANS         0x0200
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// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
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#define PCI_CLASS_BASE_DISPLAY        0x03
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// PCI 0x08, 0x00ff0000
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#define PCI_CLASS_SUB_VGA             0x00
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// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
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#define PCI_CLASS_HEADERTYPE_00h  0x00
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// 0x10-0x3f (headertype 00h)
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// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
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//   0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
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#define PCI_MAP_MEM                 0x0
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#define PCI_MAP_IO                  0x1
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#define PCI_MAP_MEM_ADDR_MASK       (~0xf)
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#define PCI_MAP_IO_ADDR_MASK        (~0x3)
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#define PCI_MAP_MEMFLAGS_32BIT      0x0
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#define PCI_MAP_MEMFLAGS_32BIT_1M   0x1
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#define PCI_MAP_MEMFLAGS_64BIT      0x4
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#define PCI_MAP_MEMFLAGS_CACHEABLE  0x8
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// PCI 0x28: cardbus CIS pointer
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// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
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// PCI 0x30: expansion ROM base address
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#define PCI_ROMBIOS_ENABLED         0x1
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// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
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// PCI 0x38: reserved
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// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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#define CIRRUS_PNPMMIO_SIZE         0x1000
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/* I/O and memory hook */
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#define CIRRUS_HOOK_NOT_HANDLED 0
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#define CIRRUS_HOOK_HANDLED 1
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#define ABS(a) ((signed)(a) > 0 ? a : -a)
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#define BLTUNSAFE(s) \
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    ( \
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        ( /* check dst is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
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                + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vram_size \
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        ) || \
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        ( /* check src is within bounds */ \
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            (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
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                + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
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                    (s)->vram_size \
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        ) \
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    )
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struct CirrusVGAState;
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typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
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                                     uint8_t * dst, const uint8_t * src,
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                                     int dstpitch, int srcpitch,
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                                     int bltwidth, int bltheight);
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typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
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                              uint8_t *dst, int dst_pitch, int width, int height);
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typedef struct CirrusVGAState {
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    VGA_STATE_COMMON
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    int cirrus_linear_io_addr;
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    int cirrus_linear_bitblt_io_addr;
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    int cirrus_mmio_io_addr;
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    uint32_t cirrus_addr_mask;
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    uint32_t linear_mmio_mask;
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    uint8_t cirrus_shadow_gr0;
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    uint8_t cirrus_shadow_gr1;
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    uint8_t cirrus_hidden_dac_lockindex;
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    uint8_t cirrus_hidden_dac_data;
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    uint32_t cirrus_bank_base[2];
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    uint32_t cirrus_bank_limit[2];
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    uint8_t cirrus_hidden_palette[48];
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    uint32_t hw_cursor_x;
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    uint32_t hw_cursor_y;
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    int cirrus_blt_pixelwidth;
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    int cirrus_blt_width;
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    int cirrus_blt_height;
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    int cirrus_blt_dstpitch;
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    int cirrus_blt_srcpitch;
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    uint32_t cirrus_blt_fgcol;
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    uint32_t cirrus_blt_bgcol;
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    uint32_t cirrus_blt_dstaddr;
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    uint32_t cirrus_blt_srcaddr;
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    uint8_t cirrus_blt_mode;
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    uint8_t cirrus_blt_modeext;
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    cirrus_bitblt_rop_t cirrus_rop;
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#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
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    uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
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    uint8_t *cirrus_srcptr;
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    uint8_t *cirrus_srcptr_end;
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    uint32_t cirrus_srccounter;
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    /* hwcursor display state */
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    int last_hw_cursor_size;
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    int last_hw_cursor_x;
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    int last_hw_cursor_y;
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    int last_hw_cursor_y_start;
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    int last_hw_cursor_y_end;
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    int real_vram_size; /* XXX: suppress that */
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    CPUWriteMemoryFunc **cirrus_linear_write;
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    int device_id;
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    int bustype;
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} CirrusVGAState;
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typedef struct PCICirrusVGAState {
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    PCIDevice dev;
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    CirrusVGAState cirrus_vga;
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} PCICirrusVGAState;
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static uint8_t rop_to_index[256];
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/***************************************
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 *
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 *  prototypes.
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 *
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 ***************************************/
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static void cirrus_bitblt_reset(CirrusVGAState *s);
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static void cirrus_update_memory_access(CirrusVGAState *s);
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/***************************************
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 *
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 *  raster operations
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 *
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 ***************************************/
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static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
318 a5082316 bellard
                                  uint8_t *dst,const uint8_t *src,
319 a5082316 bellard
                                  int dstpitch,int srcpitch,
320 a5082316 bellard
                                  int bltwidth,int bltheight)
321 a5082316 bellard
{
322 e6e5ad80 bellard
}
323 e6e5ad80 bellard
324 a5082316 bellard
static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
325 a5082316 bellard
                                   uint8_t *dst,
326 a5082316 bellard
                                   int dstpitch, int bltwidth,int bltheight)
327 e6e5ad80 bellard
{
328 a5082316 bellard
}
329 e6e5ad80 bellard
330 a5082316 bellard
#define ROP_NAME 0
331 a5082316 bellard
#define ROP_OP(d, s) d = 0
332 a5082316 bellard
#include "cirrus_vga_rop.h"
333 e6e5ad80 bellard
334 a5082316 bellard
#define ROP_NAME src_and_dst
335 a5082316 bellard
#define ROP_OP(d, s) d = (s) & (d)
336 a5082316 bellard
#include "cirrus_vga_rop.h"
337 e6e5ad80 bellard
338 a5082316 bellard
#define ROP_NAME src_and_notdst
339 a5082316 bellard
#define ROP_OP(d, s) d = (s) & (~(d))
340 a5082316 bellard
#include "cirrus_vga_rop.h"
341 e6e5ad80 bellard
342 a5082316 bellard
#define ROP_NAME notdst
343 a5082316 bellard
#define ROP_OP(d, s) d = ~(d)
344 a5082316 bellard
#include "cirrus_vga_rop.h"
345 e6e5ad80 bellard
346 a5082316 bellard
#define ROP_NAME src
347 a5082316 bellard
#define ROP_OP(d, s) d = s
348 a5082316 bellard
#include "cirrus_vga_rop.h"
349 e6e5ad80 bellard
350 a5082316 bellard
#define ROP_NAME 1
351 4c8732d7 bellard
#define ROP_OP(d, s) d = ~0
352 a5082316 bellard
#include "cirrus_vga_rop.h"
353 a5082316 bellard
354 a5082316 bellard
#define ROP_NAME notsrc_and_dst
355 a5082316 bellard
#define ROP_OP(d, s) d = (~(s)) & (d)
356 a5082316 bellard
#include "cirrus_vga_rop.h"
357 a5082316 bellard
358 a5082316 bellard
#define ROP_NAME src_xor_dst
359 a5082316 bellard
#define ROP_OP(d, s) d = (s) ^ (d)
360 a5082316 bellard
#include "cirrus_vga_rop.h"
361 a5082316 bellard
362 a5082316 bellard
#define ROP_NAME src_or_dst
363 a5082316 bellard
#define ROP_OP(d, s) d = (s) | (d)
364 a5082316 bellard
#include "cirrus_vga_rop.h"
365 a5082316 bellard
366 a5082316 bellard
#define ROP_NAME notsrc_or_notdst
367 a5082316 bellard
#define ROP_OP(d, s) d = (~(s)) | (~(d))
368 a5082316 bellard
#include "cirrus_vga_rop.h"
369 a5082316 bellard
370 a5082316 bellard
#define ROP_NAME src_notxor_dst
371 a5082316 bellard
#define ROP_OP(d, s) d = ~((s) ^ (d))
372 a5082316 bellard
#include "cirrus_vga_rop.h"
373 e6e5ad80 bellard
374 a5082316 bellard
#define ROP_NAME src_or_notdst
375 a5082316 bellard
#define ROP_OP(d, s) d = (s) | (~(d))
376 a5082316 bellard
#include "cirrus_vga_rop.h"
377 a5082316 bellard
378 a5082316 bellard
#define ROP_NAME notsrc
379 a5082316 bellard
#define ROP_OP(d, s) d = (~(s))
380 a5082316 bellard
#include "cirrus_vga_rop.h"
381 a5082316 bellard
382 a5082316 bellard
#define ROP_NAME notsrc_or_dst
383 a5082316 bellard
#define ROP_OP(d, s) d = (~(s)) | (d)
384 a5082316 bellard
#include "cirrus_vga_rop.h"
385 a5082316 bellard
386 a5082316 bellard
#define ROP_NAME notsrc_and_notdst
387 a5082316 bellard
#define ROP_OP(d, s) d = (~(s)) & (~(d))
388 a5082316 bellard
#include "cirrus_vga_rop.h"
389 a5082316 bellard
390 a5082316 bellard
static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
391 a5082316 bellard
    cirrus_bitblt_rop_fwd_0,
392 a5082316 bellard
    cirrus_bitblt_rop_fwd_src_and_dst,
393 a5082316 bellard
    cirrus_bitblt_rop_nop,
394 a5082316 bellard
    cirrus_bitblt_rop_fwd_src_and_notdst,
395 a5082316 bellard
    cirrus_bitblt_rop_fwd_notdst,
396 a5082316 bellard
    cirrus_bitblt_rop_fwd_src,
397 a5082316 bellard
    cirrus_bitblt_rop_fwd_1,
398 a5082316 bellard
    cirrus_bitblt_rop_fwd_notsrc_and_dst,
399 a5082316 bellard
    cirrus_bitblt_rop_fwd_src_xor_dst,
400 a5082316 bellard
    cirrus_bitblt_rop_fwd_src_or_dst,
401 a5082316 bellard
    cirrus_bitblt_rop_fwd_notsrc_or_notdst,
402 a5082316 bellard
    cirrus_bitblt_rop_fwd_src_notxor_dst,
403 a5082316 bellard
    cirrus_bitblt_rop_fwd_src_or_notdst,
404 a5082316 bellard
    cirrus_bitblt_rop_fwd_notsrc,
405 a5082316 bellard
    cirrus_bitblt_rop_fwd_notsrc_or_dst,
406 a5082316 bellard
    cirrus_bitblt_rop_fwd_notsrc_and_notdst,
407 a5082316 bellard
};
408 a5082316 bellard
409 a5082316 bellard
static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
410 a5082316 bellard
    cirrus_bitblt_rop_bkwd_0,
411 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src_and_dst,
412 a5082316 bellard
    cirrus_bitblt_rop_nop,
413 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src_and_notdst,
414 a5082316 bellard
    cirrus_bitblt_rop_bkwd_notdst,
415 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src,
416 a5082316 bellard
    cirrus_bitblt_rop_bkwd_1,
417 a5082316 bellard
    cirrus_bitblt_rop_bkwd_notsrc_and_dst,
418 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src_xor_dst,
419 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src_or_dst,
420 a5082316 bellard
    cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
421 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src_notxor_dst,
422 a5082316 bellard
    cirrus_bitblt_rop_bkwd_src_or_notdst,
423 a5082316 bellard
    cirrus_bitblt_rop_bkwd_notsrc,
424 a5082316 bellard
    cirrus_bitblt_rop_bkwd_notsrc_or_dst,
425 a5082316 bellard
    cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
426 a5082316 bellard
};
427 96cf2df8 ths
428 96cf2df8 ths
#define TRANSP_ROP(name) {\
429 96cf2df8 ths
    name ## _8,\
430 96cf2df8 ths
    name ## _16,\
431 96cf2df8 ths
        }
432 96cf2df8 ths
#define TRANSP_NOP(func) {\
433 96cf2df8 ths
    func,\
434 96cf2df8 ths
    func,\
435 96cf2df8 ths
        }
436 96cf2df8 ths
437 96cf2df8 ths
static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
438 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
439 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
440 96cf2df8 ths
    TRANSP_NOP(cirrus_bitblt_rop_nop),
441 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
442 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
443 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
444 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
445 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
446 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
447 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
448 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
449 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
450 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
451 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
452 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
453 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
454 96cf2df8 ths
};
455 96cf2df8 ths
456 96cf2df8 ths
static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
457 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
458 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
459 96cf2df8 ths
    TRANSP_NOP(cirrus_bitblt_rop_nop),
460 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
461 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
462 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
463 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
464 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
465 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
466 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
467 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
468 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
469 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
470 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
471 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
472 96cf2df8 ths
    TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
473 96cf2df8 ths
};
474 96cf2df8 ths
475 a5082316 bellard
#define ROP2(name) {\
476 a5082316 bellard
    name ## _8,\
477 a5082316 bellard
    name ## _16,\
478 a5082316 bellard
    name ## _24,\
479 a5082316 bellard
    name ## _32,\
480 a5082316 bellard
        }
481 a5082316 bellard
482 a5082316 bellard
#define ROP_NOP2(func) {\
483 a5082316 bellard
    func,\
484 a5082316 bellard
    func,\
485 a5082316 bellard
    func,\
486 a5082316 bellard
    func,\
487 a5082316 bellard
        }
488 a5082316 bellard
489 e69390ce bellard
static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
490 e69390ce bellard
    ROP2(cirrus_patternfill_0),
491 e69390ce bellard
    ROP2(cirrus_patternfill_src_and_dst),
492 e69390ce bellard
    ROP_NOP2(cirrus_bitblt_rop_nop),
493 e69390ce bellard
    ROP2(cirrus_patternfill_src_and_notdst),
494 e69390ce bellard
    ROP2(cirrus_patternfill_notdst),
495 e69390ce bellard
    ROP2(cirrus_patternfill_src),
496 e69390ce bellard
    ROP2(cirrus_patternfill_1),
497 e69390ce bellard
    ROP2(cirrus_patternfill_notsrc_and_dst),
498 e69390ce bellard
    ROP2(cirrus_patternfill_src_xor_dst),
499 e69390ce bellard
    ROP2(cirrus_patternfill_src_or_dst),
500 e69390ce bellard
    ROP2(cirrus_patternfill_notsrc_or_notdst),
501 e69390ce bellard
    ROP2(cirrus_patternfill_src_notxor_dst),
502 e69390ce bellard
    ROP2(cirrus_patternfill_src_or_notdst),
503 e69390ce bellard
    ROP2(cirrus_patternfill_notsrc),
504 e69390ce bellard
    ROP2(cirrus_patternfill_notsrc_or_dst),
505 e69390ce bellard
    ROP2(cirrus_patternfill_notsrc_and_notdst),
506 e69390ce bellard
};
507 e69390ce bellard
508 a5082316 bellard
static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
509 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_0),
510 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src_and_dst),
511 a5082316 bellard
    ROP_NOP2(cirrus_bitblt_rop_nop),
512 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src_and_notdst),
513 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_notdst),
514 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src),
515 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_1),
516 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
517 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src_xor_dst),
518 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src_or_dst),
519 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
520 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src_notxor_dst),
521 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_src_or_notdst),
522 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_notsrc),
523 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
524 a5082316 bellard
    ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
525 a5082316 bellard
};
526 a5082316 bellard
527 a5082316 bellard
static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
528 a5082316 bellard
    ROP2(cirrus_colorexpand_0),
529 a5082316 bellard
    ROP2(cirrus_colorexpand_src_and_dst),
530 a5082316 bellard
    ROP_NOP2(cirrus_bitblt_rop_nop),
531 a5082316 bellard
    ROP2(cirrus_colorexpand_src_and_notdst),
532 a5082316 bellard
    ROP2(cirrus_colorexpand_notdst),
533 a5082316 bellard
    ROP2(cirrus_colorexpand_src),
534 a5082316 bellard
    ROP2(cirrus_colorexpand_1),
535 a5082316 bellard
    ROP2(cirrus_colorexpand_notsrc_and_dst),
536 a5082316 bellard
    ROP2(cirrus_colorexpand_src_xor_dst),
537 a5082316 bellard
    ROP2(cirrus_colorexpand_src_or_dst),
538 a5082316 bellard
    ROP2(cirrus_colorexpand_notsrc_or_notdst),
539 a5082316 bellard
    ROP2(cirrus_colorexpand_src_notxor_dst),
540 a5082316 bellard
    ROP2(cirrus_colorexpand_src_or_notdst),
541 a5082316 bellard
    ROP2(cirrus_colorexpand_notsrc),
542 a5082316 bellard
    ROP2(cirrus_colorexpand_notsrc_or_dst),
543 a5082316 bellard
    ROP2(cirrus_colorexpand_notsrc_and_notdst),
544 a5082316 bellard
};
545 a5082316 bellard
546 b30d4608 bellard
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
547 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_0),
548 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
549 b30d4608 bellard
    ROP_NOP2(cirrus_bitblt_rop_nop),
550 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
551 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_notdst),
552 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src),
553 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_1),
554 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
555 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
556 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
557 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
558 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
559 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
560 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_notsrc),
561 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
562 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
563 b30d4608 bellard
};
564 b30d4608 bellard
565 b30d4608 bellard
static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
566 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_0),
567 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src_and_dst),
568 b30d4608 bellard
    ROP_NOP2(cirrus_bitblt_rop_nop),
569 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src_and_notdst),
570 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_notdst),
571 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src),
572 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_1),
573 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
574 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src_xor_dst),
575 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src_or_dst),
576 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
577 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
578 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_src_or_notdst),
579 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_notsrc),
580 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
581 b30d4608 bellard
    ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
582 b30d4608 bellard
};
583 b30d4608 bellard
584 a5082316 bellard
static const cirrus_fill_t cirrus_fill[16][4] = {
585 a5082316 bellard
    ROP2(cirrus_fill_0),
586 a5082316 bellard
    ROP2(cirrus_fill_src_and_dst),
587 a5082316 bellard
    ROP_NOP2(cirrus_bitblt_fill_nop),
588 a5082316 bellard
    ROP2(cirrus_fill_src_and_notdst),
589 a5082316 bellard
    ROP2(cirrus_fill_notdst),
590 a5082316 bellard
    ROP2(cirrus_fill_src),
591 a5082316 bellard
    ROP2(cirrus_fill_1),
592 a5082316 bellard
    ROP2(cirrus_fill_notsrc_and_dst),
593 a5082316 bellard
    ROP2(cirrus_fill_src_xor_dst),
594 a5082316 bellard
    ROP2(cirrus_fill_src_or_dst),
595 a5082316 bellard
    ROP2(cirrus_fill_notsrc_or_notdst),
596 a5082316 bellard
    ROP2(cirrus_fill_src_notxor_dst),
597 a5082316 bellard
    ROP2(cirrus_fill_src_or_notdst),
598 a5082316 bellard
    ROP2(cirrus_fill_notsrc),
599 a5082316 bellard
    ROP2(cirrus_fill_notsrc_or_dst),
600 a5082316 bellard
    ROP2(cirrus_fill_notsrc_and_notdst),
601 a5082316 bellard
};
602 a5082316 bellard
603 a5082316 bellard
static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
604 e6e5ad80 bellard
{
605 a5082316 bellard
    unsigned int color;
606 a5082316 bellard
    switch (s->cirrus_blt_pixelwidth) {
607 a5082316 bellard
    case 1:
608 a5082316 bellard
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
609 a5082316 bellard
        break;
610 a5082316 bellard
    case 2:
611 a5082316 bellard
        color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
612 a5082316 bellard
        s->cirrus_blt_fgcol = le16_to_cpu(color);
613 a5082316 bellard
        break;
614 a5082316 bellard
    case 3:
615 5fafdf24 ths
        s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
616 a5082316 bellard
            (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
617 a5082316 bellard
        break;
618 a5082316 bellard
    default:
619 a5082316 bellard
    case 4:
620 a5082316 bellard
        color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
621 a5082316 bellard
            (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
622 a5082316 bellard
        s->cirrus_blt_fgcol = le32_to_cpu(color);
623 a5082316 bellard
        break;
624 e6e5ad80 bellard
    }
625 e6e5ad80 bellard
}
626 e6e5ad80 bellard
627 a5082316 bellard
static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
628 e6e5ad80 bellard
{
629 a5082316 bellard
    unsigned int color;
630 e6e5ad80 bellard
    switch (s->cirrus_blt_pixelwidth) {
631 e6e5ad80 bellard
    case 1:
632 a5082316 bellard
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
633 a5082316 bellard
        break;
634 e6e5ad80 bellard
    case 2:
635 a5082316 bellard
        color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
636 a5082316 bellard
        s->cirrus_blt_bgcol = le16_to_cpu(color);
637 a5082316 bellard
        break;
638 e6e5ad80 bellard
    case 3:
639 5fafdf24 ths
        s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
640 a5082316 bellard
            (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
641 a5082316 bellard
        break;
642 e6e5ad80 bellard
    default:
643 a5082316 bellard
    case 4:
644 a5082316 bellard
        color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
645 a5082316 bellard
            (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
646 a5082316 bellard
        s->cirrus_blt_bgcol = le32_to_cpu(color);
647 a5082316 bellard
        break;
648 e6e5ad80 bellard
    }
649 e6e5ad80 bellard
}
650 e6e5ad80 bellard
651 e6e5ad80 bellard
static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
652 e6e5ad80 bellard
                                     int off_pitch, int bytesperline,
653 e6e5ad80 bellard
                                     int lines)
654 e6e5ad80 bellard
{
655 e6e5ad80 bellard
    int y;
656 e6e5ad80 bellard
    int off_cur;
657 e6e5ad80 bellard
    int off_cur_end;
658 e6e5ad80 bellard
659 e6e5ad80 bellard
    for (y = 0; y < lines; y++) {
660 e6e5ad80 bellard
        off_cur = off_begin;
661 b2eb849d aurel32
        off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
662 e6e5ad80 bellard
        off_cur &= TARGET_PAGE_MASK;
663 e6e5ad80 bellard
        while (off_cur < off_cur_end) {
664 e6e5ad80 bellard
            cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
665 e6e5ad80 bellard
            off_cur += TARGET_PAGE_SIZE;
666 e6e5ad80 bellard
        }
667 e6e5ad80 bellard
        off_begin += off_pitch;
668 e6e5ad80 bellard
    }
669 e6e5ad80 bellard
}
670 e6e5ad80 bellard
671 e6e5ad80 bellard
static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
672 e6e5ad80 bellard
                                            const uint8_t * src)
673 e6e5ad80 bellard
{
674 e6e5ad80 bellard
    uint8_t *dst;
675 e6e5ad80 bellard
676 b2eb849d aurel32
    dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
677 b2eb849d aurel32
678 b2eb849d aurel32
    if (BLTUNSAFE(s))
679 b2eb849d aurel32
        return 0;
680 b2eb849d aurel32
681 e69390ce bellard
    (*s->cirrus_rop) (s, dst, src,
682 5fafdf24 ths
                      s->cirrus_blt_dstpitch, 0,
683 e69390ce bellard
                      s->cirrus_blt_width, s->cirrus_blt_height);
684 e6e5ad80 bellard
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
685 e69390ce bellard
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
686 e69390ce bellard
                             s->cirrus_blt_height);
687 e6e5ad80 bellard
    return 1;
688 e6e5ad80 bellard
}
689 e6e5ad80 bellard
690 a21ae81d bellard
/* fill */
691 a21ae81d bellard
692 a5082316 bellard
static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
693 a21ae81d bellard
{
694 a5082316 bellard
    cirrus_fill_t rop_func;
695 a21ae81d bellard
696 b2eb849d aurel32
    if (BLTUNSAFE(s))
697 b2eb849d aurel32
        return 0;
698 a5082316 bellard
    rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
699 b2eb849d aurel32
    rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
700 a5082316 bellard
             s->cirrus_blt_dstpitch,
701 a5082316 bellard
             s->cirrus_blt_width, s->cirrus_blt_height);
702 a21ae81d bellard
    cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
703 a21ae81d bellard
                             s->cirrus_blt_dstpitch, s->cirrus_blt_width,
704 a21ae81d bellard
                             s->cirrus_blt_height);
705 a21ae81d bellard
    cirrus_bitblt_reset(s);
706 a21ae81d bellard
    return 1;
707 a21ae81d bellard
}
708 a21ae81d bellard
709 e6e5ad80 bellard
/***************************************
710 e6e5ad80 bellard
 *
711 e6e5ad80 bellard
 *  bitblt (video-to-video)
712 e6e5ad80 bellard
 *
713 e6e5ad80 bellard
 ***************************************/
714 e6e5ad80 bellard
715 e6e5ad80 bellard
static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
716 e6e5ad80 bellard
{
717 e6e5ad80 bellard
    return cirrus_bitblt_common_patterncopy(s,
718 b2eb849d aurel32
                                            s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
719 b2eb849d aurel32
                                            s->cirrus_addr_mask));
720 e6e5ad80 bellard
}
721 e6e5ad80 bellard
722 24236869 bellard
static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
723 e6e5ad80 bellard
{
724 24236869 bellard
    int sx, sy;
725 24236869 bellard
    int dx, dy;
726 24236869 bellard
    int width, height;
727 24236869 bellard
    int depth;
728 24236869 bellard
    int notify = 0;
729 24236869 bellard
730 24236869 bellard
    depth = s->get_bpp((VGAState *)s) / 8;
731 24236869 bellard
    s->get_resolution((VGAState *)s, &width, &height);
732 24236869 bellard
733 24236869 bellard
    /* extra x, y */
734 24236869 bellard
    sx = (src % (width * depth)) / depth;
735 24236869 bellard
    sy = (src / (width * depth));
736 24236869 bellard
    dx = (dst % (width *depth)) / depth;
737 24236869 bellard
    dy = (dst / (width * depth));
738 24236869 bellard
739 24236869 bellard
    /* normalize width */
740 24236869 bellard
    w /= depth;
741 24236869 bellard
742 24236869 bellard
    /* if we're doing a backward copy, we have to adjust
743 24236869 bellard
       our x/y to be the upper left corner (instead of the lower
744 24236869 bellard
       right corner) */
745 24236869 bellard
    if (s->cirrus_blt_dstpitch < 0) {
746 24236869 bellard
        sx -= (s->cirrus_blt_width / depth) - 1;
747 24236869 bellard
        dx -= (s->cirrus_blt_width / depth) - 1;
748 24236869 bellard
        sy -= s->cirrus_blt_height - 1;
749 24236869 bellard
        dy -= s->cirrus_blt_height - 1;
750 24236869 bellard
    }
751 24236869 bellard
752 24236869 bellard
    /* are we in the visible portion of memory? */
753 24236869 bellard
    if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
754 24236869 bellard
        (sx + w) <= width && (sy + h) <= height &&
755 24236869 bellard
        (dx + w) <= width && (dy + h) <= height) {
756 24236869 bellard
        notify = 1;
757 24236869 bellard
    }
758 24236869 bellard
759 24236869 bellard
    /* make to sure only copy if it's a plain copy ROP */
760 24236869 bellard
    if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
761 24236869 bellard
        *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
762 24236869 bellard
        notify = 0;
763 24236869 bellard
764 24236869 bellard
    /* we have to flush all pending changes so that the copy
765 24236869 bellard
       is generated at the appropriate moment in time */
766 24236869 bellard
    if (notify)
767 24236869 bellard
        vga_hw_update();
768 24236869 bellard
769 b2eb849d aurel32
    (*s->cirrus_rop) (s, s->vram_ptr +
770 b2eb849d aurel32
                      (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
771 b2eb849d aurel32
                      s->vram_ptr +
772 b2eb849d aurel32
                      (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
773 e6e5ad80 bellard
                      s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
774 e6e5ad80 bellard
                      s->cirrus_blt_width, s->cirrus_blt_height);
775 24236869 bellard
776 24236869 bellard
    if (notify)
777 38334f76 balrog
        qemu_console_copy(s->console,
778 38334f76 balrog
                          sx, sy, dx, dy,
779 38334f76 balrog
                          s->cirrus_blt_width / depth,
780 38334f76 balrog
                          s->cirrus_blt_height);
781 24236869 bellard
782 24236869 bellard
    /* we don't have to notify the display that this portion has
783 38334f76 balrog
       changed since qemu_console_copy implies this */
784 24236869 bellard
785 24236869 bellard
    if (!notify)
786 24236869 bellard
        cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
787 24236869 bellard
                                 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
788 24236869 bellard
                                 s->cirrus_blt_height);
789 24236869 bellard
}
790 24236869 bellard
791 24236869 bellard
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
792 24236869 bellard
{
793 65d35a09 aurel32
    if (BLTUNSAFE(s))
794 65d35a09 aurel32
        return 0;
795 65d35a09 aurel32
796 24236869 bellard
    if (s->ds->dpy_copy) {
797 24236869 bellard
        cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
798 24236869 bellard
                       s->cirrus_blt_srcaddr - s->start_addr,
799 24236869 bellard
                       s->cirrus_blt_width, s->cirrus_blt_height);
800 24236869 bellard
    } else {
801 b2eb849d aurel32
        (*s->cirrus_rop) (s, s->vram_ptr +
802 b2eb849d aurel32
                (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
803 b2eb849d aurel32
                          s->vram_ptr +
804 b2eb849d aurel32
                (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
805 24236869 bellard
                          s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
806 24236869 bellard
                          s->cirrus_blt_width, s->cirrus_blt_height);
807 24236869 bellard
808 24236869 bellard
        cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
809 24236869 bellard
                                 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
810 24236869 bellard
                                 s->cirrus_blt_height);
811 24236869 bellard
    }
812 24236869 bellard
813 e6e5ad80 bellard
    return 1;
814 e6e5ad80 bellard
}
815 e6e5ad80 bellard
816 e6e5ad80 bellard
/***************************************
817 e6e5ad80 bellard
 *
818 e6e5ad80 bellard
 *  bitblt (cpu-to-video)
819 e6e5ad80 bellard
 *
820 e6e5ad80 bellard
 ***************************************/
821 e6e5ad80 bellard
822 e6e5ad80 bellard
static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
823 e6e5ad80 bellard
{
824 e6e5ad80 bellard
    int copy_count;
825 a5082316 bellard
    uint8_t *end_ptr;
826 3b46e624 ths
827 e6e5ad80 bellard
    if (s->cirrus_srccounter > 0) {
828 a5082316 bellard
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
829 a5082316 bellard
            cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
830 a5082316 bellard
        the_end:
831 a5082316 bellard
            s->cirrus_srccounter = 0;
832 a5082316 bellard
            cirrus_bitblt_reset(s);
833 a5082316 bellard
        } else {
834 a5082316 bellard
            /* at least one scan line */
835 a5082316 bellard
            do {
836 b2eb849d aurel32
                (*s->cirrus_rop)(s, s->vram_ptr +
837 b2eb849d aurel32
                                 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
838 b2eb849d aurel32
                                  s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
839 a5082316 bellard
                cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
840 a5082316 bellard
                                         s->cirrus_blt_width, 1);
841 a5082316 bellard
                s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
842 a5082316 bellard
                s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
843 a5082316 bellard
                if (s->cirrus_srccounter <= 0)
844 a5082316 bellard
                    goto the_end;
845 a5082316 bellard
                /* more bytes than needed can be transfered because of
846 a5082316 bellard
                   word alignment, so we keep them for the next line */
847 a5082316 bellard
                /* XXX: keep alignment to speed up transfer */
848 a5082316 bellard
                end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
849 a5082316 bellard
                copy_count = s->cirrus_srcptr_end - end_ptr;
850 a5082316 bellard
                memmove(s->cirrus_bltbuf, end_ptr, copy_count);
851 a5082316 bellard
                s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
852 a5082316 bellard
                s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
853 a5082316 bellard
            } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
854 a5082316 bellard
        }
855 e6e5ad80 bellard
    }
856 e6e5ad80 bellard
}
857 e6e5ad80 bellard
858 e6e5ad80 bellard
/***************************************
859 e6e5ad80 bellard
 *
860 e6e5ad80 bellard
 *  bitblt wrapper
861 e6e5ad80 bellard
 *
862 e6e5ad80 bellard
 ***************************************/
863 e6e5ad80 bellard
864 e6e5ad80 bellard
static void cirrus_bitblt_reset(CirrusVGAState * s)
865 e6e5ad80 bellard
{
866 e6e5ad80 bellard
    s->gr[0x31] &=
867 e6e5ad80 bellard
        ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
868 e6e5ad80 bellard
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
869 e6e5ad80 bellard
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
870 e6e5ad80 bellard
    s->cirrus_srccounter = 0;
871 8926b517 bellard
    cirrus_update_memory_access(s);
872 e6e5ad80 bellard
}
873 e6e5ad80 bellard
874 e6e5ad80 bellard
static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
875 e6e5ad80 bellard
{
876 a5082316 bellard
    int w;
877 a5082316 bellard
878 e6e5ad80 bellard
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
879 e6e5ad80 bellard
    s->cirrus_srcptr = &s->cirrus_bltbuf[0];
880 e6e5ad80 bellard
    s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
881 e6e5ad80 bellard
882 e6e5ad80 bellard
    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
883 e6e5ad80 bellard
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
884 a5082316 bellard
            s->cirrus_blt_srcpitch = 8;
885 e6e5ad80 bellard
        } else {
886 b30d4608 bellard
            /* XXX: check for 24 bpp */
887 a5082316 bellard
            s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
888 e6e5ad80 bellard
        }
889 a5082316 bellard
        s->cirrus_srccounter = s->cirrus_blt_srcpitch;
890 e6e5ad80 bellard
    } else {
891 e6e5ad80 bellard
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
892 a5082316 bellard
            w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
893 5fafdf24 ths
            if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
894 a5082316 bellard
                s->cirrus_blt_srcpitch = ((w + 31) >> 5);
895 a5082316 bellard
            else
896 a5082316 bellard
                s->cirrus_blt_srcpitch = ((w + 7) >> 3);
897 e6e5ad80 bellard
        } else {
898 c9c0eae8 bellard
            /* always align input size to 32 bits */
899 c9c0eae8 bellard
            s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
900 e6e5ad80 bellard
        }
901 a5082316 bellard
        s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
902 e6e5ad80 bellard
    }
903 a5082316 bellard
    s->cirrus_srcptr = s->cirrus_bltbuf;
904 a5082316 bellard
    s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
905 8926b517 bellard
    cirrus_update_memory_access(s);
906 e6e5ad80 bellard
    return 1;
907 e6e5ad80 bellard
}
908 e6e5ad80 bellard
909 e6e5ad80 bellard
static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
910 e6e5ad80 bellard
{
911 e6e5ad80 bellard
    /* XXX */
912 a5082316 bellard
#ifdef DEBUG_BITBLT
913 e6e5ad80 bellard
    printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
914 e6e5ad80 bellard
#endif
915 e6e5ad80 bellard
    return 0;
916 e6e5ad80 bellard
}
917 e6e5ad80 bellard
918 e6e5ad80 bellard
static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
919 e6e5ad80 bellard
{
920 e6e5ad80 bellard
    int ret;
921 e6e5ad80 bellard
922 e6e5ad80 bellard
    if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
923 e6e5ad80 bellard
        ret = cirrus_bitblt_videotovideo_patterncopy(s);
924 e6e5ad80 bellard
    } else {
925 e6e5ad80 bellard
        ret = cirrus_bitblt_videotovideo_copy(s);
926 e6e5ad80 bellard
    }
927 e6e5ad80 bellard
    if (ret)
928 e6e5ad80 bellard
        cirrus_bitblt_reset(s);
929 e6e5ad80 bellard
    return ret;
930 e6e5ad80 bellard
}
931 e6e5ad80 bellard
932 e6e5ad80 bellard
static void cirrus_bitblt_start(CirrusVGAState * s)
933 e6e5ad80 bellard
{
934 e6e5ad80 bellard
    uint8_t blt_rop;
935 e6e5ad80 bellard
936 a5082316 bellard
    s->gr[0x31] |= CIRRUS_BLT_BUSY;
937 a5082316 bellard
938 e6e5ad80 bellard
    s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
939 e6e5ad80 bellard
    s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
940 e6e5ad80 bellard
    s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
941 e6e5ad80 bellard
    s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
942 e6e5ad80 bellard
    s->cirrus_blt_dstaddr =
943 e6e5ad80 bellard
        (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
944 e6e5ad80 bellard
    s->cirrus_blt_srcaddr =
945 e6e5ad80 bellard
        (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
946 e6e5ad80 bellard
    s->cirrus_blt_mode = s->gr[0x30];
947 a5082316 bellard
    s->cirrus_blt_modeext = s->gr[0x33];
948 e6e5ad80 bellard
    blt_rop = s->gr[0x32];
949 e6e5ad80 bellard
950 a21ae81d bellard
#ifdef DEBUG_BITBLT
951 0b74ed78 bellard
    printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
952 5fafdf24 ths
           blt_rop,
953 a21ae81d bellard
           s->cirrus_blt_mode,
954 a5082316 bellard
           s->cirrus_blt_modeext,
955 a21ae81d bellard
           s->cirrus_blt_width,
956 a21ae81d bellard
           s->cirrus_blt_height,
957 a21ae81d bellard
           s->cirrus_blt_dstpitch,
958 a21ae81d bellard
           s->cirrus_blt_srcpitch,
959 a21ae81d bellard
           s->cirrus_blt_dstaddr,
960 a5082316 bellard
           s->cirrus_blt_srcaddr,
961 e3a4e4b6 bellard
           s->gr[0x2f]);
962 a21ae81d bellard
#endif
963 a21ae81d bellard
964 e6e5ad80 bellard
    switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
965 e6e5ad80 bellard
    case CIRRUS_BLTMODE_PIXELWIDTH8:
966 e6e5ad80 bellard
        s->cirrus_blt_pixelwidth = 1;
967 e6e5ad80 bellard
        break;
968 e6e5ad80 bellard
    case CIRRUS_BLTMODE_PIXELWIDTH16:
969 e6e5ad80 bellard
        s->cirrus_blt_pixelwidth = 2;
970 e6e5ad80 bellard
        break;
971 e6e5ad80 bellard
    case CIRRUS_BLTMODE_PIXELWIDTH24:
972 e6e5ad80 bellard
        s->cirrus_blt_pixelwidth = 3;
973 e6e5ad80 bellard
        break;
974 e6e5ad80 bellard
    case CIRRUS_BLTMODE_PIXELWIDTH32:
975 e6e5ad80 bellard
        s->cirrus_blt_pixelwidth = 4;
976 e6e5ad80 bellard
        break;
977 e6e5ad80 bellard
    default:
978 a5082316 bellard
#ifdef DEBUG_BITBLT
979 e6e5ad80 bellard
        printf("cirrus: bitblt - pixel width is unknown\n");
980 e6e5ad80 bellard
#endif
981 e6e5ad80 bellard
        goto bitblt_ignore;
982 e6e5ad80 bellard
    }
983 e6e5ad80 bellard
    s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
984 e6e5ad80 bellard
985 e6e5ad80 bellard
    if ((s->
986 e6e5ad80 bellard
         cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
987 e6e5ad80 bellard
                            CIRRUS_BLTMODE_MEMSYSDEST))
988 e6e5ad80 bellard
        == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
989 a5082316 bellard
#ifdef DEBUG_BITBLT
990 e6e5ad80 bellard
        printf("cirrus: bitblt - memory-to-memory copy is requested\n");
991 e6e5ad80 bellard
#endif
992 e6e5ad80 bellard
        goto bitblt_ignore;
993 e6e5ad80 bellard
    }
994 e6e5ad80 bellard
995 a5082316 bellard
    if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
996 5fafdf24 ths
        (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
997 a21ae81d bellard
                               CIRRUS_BLTMODE_TRANSPARENTCOMP |
998 5fafdf24 ths
                               CIRRUS_BLTMODE_PATTERNCOPY |
999 5fafdf24 ths
                               CIRRUS_BLTMODE_COLOREXPAND)) ==
1000 a21ae81d bellard
         (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1001 a5082316 bellard
        cirrus_bitblt_fgcol(s);
1002 a5082316 bellard
        cirrus_bitblt_solidfill(s, blt_rop);
1003 e6e5ad80 bellard
    } else {
1004 5fafdf24 ths
        if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1005 5fafdf24 ths
                                   CIRRUS_BLTMODE_PATTERNCOPY)) ==
1006 a5082316 bellard
            CIRRUS_BLTMODE_COLOREXPAND) {
1007 a5082316 bellard
1008 a5082316 bellard
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1009 b30d4608 bellard
                if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1010 4c8732d7 bellard
                    cirrus_bitblt_bgcol(s);
1011 b30d4608 bellard
                else
1012 4c8732d7 bellard
                    cirrus_bitblt_fgcol(s);
1013 b30d4608 bellard
                s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1014 a5082316 bellard
            } else {
1015 a5082316 bellard
                cirrus_bitblt_fgcol(s);
1016 a5082316 bellard
                cirrus_bitblt_bgcol(s);
1017 a5082316 bellard
                s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1018 a5082316 bellard
            }
1019 e69390ce bellard
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1020 b30d4608 bellard
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1021 b30d4608 bellard
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1022 b30d4608 bellard
                    if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1023 b30d4608 bellard
                        cirrus_bitblt_bgcol(s);
1024 b30d4608 bellard
                    else
1025 b30d4608 bellard
                        cirrus_bitblt_fgcol(s);
1026 b30d4608 bellard
                    s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1027 b30d4608 bellard
                } else {
1028 b30d4608 bellard
                    cirrus_bitblt_fgcol(s);
1029 b30d4608 bellard
                    cirrus_bitblt_bgcol(s);
1030 b30d4608 bellard
                    s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1031 b30d4608 bellard
                }
1032 b30d4608 bellard
            } else {
1033 b30d4608 bellard
                s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1034 b30d4608 bellard
            }
1035 a21ae81d bellard
        } else {
1036 96cf2df8 ths
            if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1037 96cf2df8 ths
                if (s->cirrus_blt_pixelwidth > 2) {
1038 96cf2df8 ths
                    printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1039 96cf2df8 ths
                    goto bitblt_ignore;
1040 96cf2df8 ths
                }
1041 96cf2df8 ths
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1042 96cf2df8 ths
                    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1043 96cf2df8 ths
                    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1044 96cf2df8 ths
                    s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1045 96cf2df8 ths
                } else {
1046 96cf2df8 ths
                    s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1047 96cf2df8 ths
                }
1048 96cf2df8 ths
            } else {
1049 96cf2df8 ths
                if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1050 96cf2df8 ths
                    s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1051 96cf2df8 ths
                    s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1052 96cf2df8 ths
                    s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1053 96cf2df8 ths
                } else {
1054 96cf2df8 ths
                    s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1055 96cf2df8 ths
                }
1056 96cf2df8 ths
            }
1057 96cf2df8 ths
        }
1058 a21ae81d bellard
        // setup bitblt engine.
1059 a21ae81d bellard
        if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1060 a21ae81d bellard
            if (!cirrus_bitblt_cputovideo(s))
1061 a21ae81d bellard
                goto bitblt_ignore;
1062 a21ae81d bellard
        } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1063 a21ae81d bellard
            if (!cirrus_bitblt_videotocpu(s))
1064 a21ae81d bellard
                goto bitblt_ignore;
1065 a21ae81d bellard
        } else {
1066 a21ae81d bellard
            if (!cirrus_bitblt_videotovideo(s))
1067 a21ae81d bellard
                goto bitblt_ignore;
1068 a21ae81d bellard
        }
1069 e6e5ad80 bellard
    }
1070 e6e5ad80 bellard
    return;
1071 e6e5ad80 bellard
  bitblt_ignore:;
1072 e6e5ad80 bellard
    cirrus_bitblt_reset(s);
1073 e6e5ad80 bellard
}
1074 e6e5ad80 bellard
1075 e6e5ad80 bellard
static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1076 e6e5ad80 bellard
{
1077 e6e5ad80 bellard
    unsigned old_value;
1078 e6e5ad80 bellard
1079 e6e5ad80 bellard
    old_value = s->gr[0x31];
1080 e6e5ad80 bellard
    s->gr[0x31] = reg_value;
1081 e6e5ad80 bellard
1082 e6e5ad80 bellard
    if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1083 e6e5ad80 bellard
        ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1084 e6e5ad80 bellard
        cirrus_bitblt_reset(s);
1085 e6e5ad80 bellard
    } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1086 e6e5ad80 bellard
               ((reg_value & CIRRUS_BLT_START) != 0)) {
1087 e6e5ad80 bellard
        cirrus_bitblt_start(s);
1088 e6e5ad80 bellard
    }
1089 e6e5ad80 bellard
}
1090 e6e5ad80 bellard
1091 e6e5ad80 bellard
1092 e6e5ad80 bellard
/***************************************
1093 e6e5ad80 bellard
 *
1094 e6e5ad80 bellard
 *  basic parameters
1095 e6e5ad80 bellard
 *
1096 e6e5ad80 bellard
 ***************************************/
1097 e6e5ad80 bellard
1098 5fafdf24 ths
static void cirrus_get_offsets(VGAState *s1,
1099 83acc96b bellard
                               uint32_t *pline_offset,
1100 83acc96b bellard
                               uint32_t *pstart_addr,
1101 83acc96b bellard
                               uint32_t *pline_compare)
1102 e6e5ad80 bellard
{
1103 e6e5ad80 bellard
    CirrusVGAState * s = (CirrusVGAState *)s1;
1104 83acc96b bellard
    uint32_t start_addr, line_offset, line_compare;
1105 e6e5ad80 bellard
1106 e6e5ad80 bellard
    line_offset = s->cr[0x13]
1107 e36f36e1 bellard
        | ((s->cr[0x1b] & 0x10) << 4);
1108 e6e5ad80 bellard
    line_offset <<= 3;
1109 e6e5ad80 bellard
    *pline_offset = line_offset;
1110 e6e5ad80 bellard
1111 e6e5ad80 bellard
    start_addr = (s->cr[0x0c] << 8)
1112 e6e5ad80 bellard
        | s->cr[0x0d]
1113 e6e5ad80 bellard
        | ((s->cr[0x1b] & 0x01) << 16)
1114 e6e5ad80 bellard
        | ((s->cr[0x1b] & 0x0c) << 15)
1115 e6e5ad80 bellard
        | ((s->cr[0x1d] & 0x80) << 12);
1116 e6e5ad80 bellard
    *pstart_addr = start_addr;
1117 83acc96b bellard
1118 5fafdf24 ths
    line_compare = s->cr[0x18] |
1119 83acc96b bellard
        ((s->cr[0x07] & 0x10) << 4) |
1120 83acc96b bellard
        ((s->cr[0x09] & 0x40) << 3);
1121 83acc96b bellard
    *pline_compare = line_compare;
1122 e6e5ad80 bellard
}
1123 e6e5ad80 bellard
1124 e6e5ad80 bellard
static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1125 e6e5ad80 bellard
{
1126 e6e5ad80 bellard
    uint32_t ret = 16;
1127 e6e5ad80 bellard
1128 e6e5ad80 bellard
    switch (s->cirrus_hidden_dac_data & 0xf) {
1129 e6e5ad80 bellard
    case 0:
1130 e6e5ad80 bellard
        ret = 15;
1131 e6e5ad80 bellard
        break;                        /* Sierra HiColor */
1132 e6e5ad80 bellard
    case 1:
1133 e6e5ad80 bellard
        ret = 16;
1134 e6e5ad80 bellard
        break;                        /* XGA HiColor */
1135 e6e5ad80 bellard
    default:
1136 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1137 e6e5ad80 bellard
        printf("cirrus: invalid DAC value %x in 16bpp\n",
1138 e6e5ad80 bellard
               (s->cirrus_hidden_dac_data & 0xf));
1139 e6e5ad80 bellard
#endif
1140 e6e5ad80 bellard
        ret = 15;                /* XXX */
1141 e6e5ad80 bellard
        break;
1142 e6e5ad80 bellard
    }
1143 e6e5ad80 bellard
    return ret;
1144 e6e5ad80 bellard
}
1145 e6e5ad80 bellard
1146 e6e5ad80 bellard
static int cirrus_get_bpp(VGAState *s1)
1147 e6e5ad80 bellard
{
1148 e6e5ad80 bellard
    CirrusVGAState * s = (CirrusVGAState *)s1;
1149 e6e5ad80 bellard
    uint32_t ret = 8;
1150 e6e5ad80 bellard
1151 e6e5ad80 bellard
    if ((s->sr[0x07] & 0x01) != 0) {
1152 e6e5ad80 bellard
        /* Cirrus SVGA */
1153 e6e5ad80 bellard
        switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1154 e6e5ad80 bellard
        case CIRRUS_SR7_BPP_8:
1155 e6e5ad80 bellard
            ret = 8;
1156 e6e5ad80 bellard
            break;
1157 e6e5ad80 bellard
        case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1158 e6e5ad80 bellard
            ret = cirrus_get_bpp16_depth(s);
1159 e6e5ad80 bellard
            break;
1160 e6e5ad80 bellard
        case CIRRUS_SR7_BPP_24:
1161 e6e5ad80 bellard
            ret = 24;
1162 e6e5ad80 bellard
            break;
1163 e6e5ad80 bellard
        case CIRRUS_SR7_BPP_16:
1164 e6e5ad80 bellard
            ret = cirrus_get_bpp16_depth(s);
1165 e6e5ad80 bellard
            break;
1166 e6e5ad80 bellard
        case CIRRUS_SR7_BPP_32:
1167 e6e5ad80 bellard
            ret = 32;
1168 e6e5ad80 bellard
            break;
1169 e6e5ad80 bellard
        default:
1170 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1171 e6e5ad80 bellard
            printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1172 e6e5ad80 bellard
#endif
1173 e6e5ad80 bellard
            ret = 8;
1174 e6e5ad80 bellard
            break;
1175 e6e5ad80 bellard
        }
1176 e6e5ad80 bellard
    } else {
1177 e6e5ad80 bellard
        /* VGA */
1178 aeb3c85f bellard
        ret = 0;
1179 e6e5ad80 bellard
    }
1180 e6e5ad80 bellard
1181 e6e5ad80 bellard
    return ret;
1182 e6e5ad80 bellard
}
1183 e6e5ad80 bellard
1184 78e127ef bellard
static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1185 78e127ef bellard
{
1186 78e127ef bellard
    int width, height;
1187 3b46e624 ths
1188 78e127ef bellard
    width = (s->cr[0x01] + 1) * 8;
1189 5fafdf24 ths
    height = s->cr[0x12] |
1190 5fafdf24 ths
        ((s->cr[0x07] & 0x02) << 7) |
1191 78e127ef bellard
        ((s->cr[0x07] & 0x40) << 3);
1192 78e127ef bellard
    height = (height + 1);
1193 78e127ef bellard
    /* interlace support */
1194 78e127ef bellard
    if (s->cr[0x1a] & 0x01)
1195 78e127ef bellard
        height = height * 2;
1196 78e127ef bellard
    *pwidth = width;
1197 78e127ef bellard
    *pheight = height;
1198 78e127ef bellard
}
1199 78e127ef bellard
1200 e6e5ad80 bellard
/***************************************
1201 e6e5ad80 bellard
 *
1202 e6e5ad80 bellard
 * bank memory
1203 e6e5ad80 bellard
 *
1204 e6e5ad80 bellard
 ***************************************/
1205 e6e5ad80 bellard
1206 e6e5ad80 bellard
static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1207 e6e5ad80 bellard
{
1208 e6e5ad80 bellard
    unsigned offset;
1209 e6e5ad80 bellard
    unsigned limit;
1210 e6e5ad80 bellard
1211 e6e5ad80 bellard
    if ((s->gr[0x0b] & 0x01) != 0)        /* dual bank */
1212 e6e5ad80 bellard
        offset = s->gr[0x09 + bank_index];
1213 e6e5ad80 bellard
    else                        /* single bank */
1214 e6e5ad80 bellard
        offset = s->gr[0x09];
1215 e6e5ad80 bellard
1216 e6e5ad80 bellard
    if ((s->gr[0x0b] & 0x20) != 0)
1217 e6e5ad80 bellard
        offset <<= 14;
1218 e6e5ad80 bellard
    else
1219 e6e5ad80 bellard
        offset <<= 12;
1220 e6e5ad80 bellard
1221 e3a4e4b6 bellard
    if (s->real_vram_size <= offset)
1222 e6e5ad80 bellard
        limit = 0;
1223 e6e5ad80 bellard
    else
1224 e3a4e4b6 bellard
        limit = s->real_vram_size - offset;
1225 e6e5ad80 bellard
1226 e6e5ad80 bellard
    if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1227 e6e5ad80 bellard
        if (limit > 0x8000) {
1228 e6e5ad80 bellard
            offset += 0x8000;
1229 e6e5ad80 bellard
            limit -= 0x8000;
1230 e6e5ad80 bellard
        } else {
1231 e6e5ad80 bellard
            limit = 0;
1232 e6e5ad80 bellard
        }
1233 e6e5ad80 bellard
    }
1234 e6e5ad80 bellard
1235 e6e5ad80 bellard
    if (limit > 0) {
1236 2bec46dc aliguori
        /* Thinking about changing bank base? First, drop the dirty bitmap information
1237 2bec46dc aliguori
         * on the current location, otherwise we lose this pointer forever */
1238 2bec46dc aliguori
        if (s->lfb_vram_mapped) {
1239 2bec46dc aliguori
            target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1240 2bec46dc aliguori
            cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1241 2bec46dc aliguori
        }
1242 e6e5ad80 bellard
        s->cirrus_bank_base[bank_index] = offset;
1243 e6e5ad80 bellard
        s->cirrus_bank_limit[bank_index] = limit;
1244 e6e5ad80 bellard
    } else {
1245 e6e5ad80 bellard
        s->cirrus_bank_base[bank_index] = 0;
1246 e6e5ad80 bellard
        s->cirrus_bank_limit[bank_index] = 0;
1247 e6e5ad80 bellard
    }
1248 e6e5ad80 bellard
}
1249 e6e5ad80 bellard
1250 e6e5ad80 bellard
/***************************************
1251 e6e5ad80 bellard
 *
1252 e6e5ad80 bellard
 *  I/O access between 0x3c4-0x3c5
1253 e6e5ad80 bellard
 *
1254 e6e5ad80 bellard
 ***************************************/
1255 e6e5ad80 bellard
1256 e6e5ad80 bellard
static int
1257 e6e5ad80 bellard
cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1258 e6e5ad80 bellard
{
1259 e6e5ad80 bellard
    switch (reg_index) {
1260 e6e5ad80 bellard
    case 0x00:                        // Standard VGA
1261 e6e5ad80 bellard
    case 0x01:                        // Standard VGA
1262 e6e5ad80 bellard
    case 0x02:                        // Standard VGA
1263 e6e5ad80 bellard
    case 0x03:                        // Standard VGA
1264 e6e5ad80 bellard
    case 0x04:                        // Standard VGA
1265 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1266 e6e5ad80 bellard
    case 0x06:                        // Unlock Cirrus extensions
1267 e6e5ad80 bellard
        *reg_value = s->sr[reg_index];
1268 e6e5ad80 bellard
        break;
1269 e6e5ad80 bellard
    case 0x10:
1270 e6e5ad80 bellard
    case 0x30:
1271 e6e5ad80 bellard
    case 0x50:
1272 e6e5ad80 bellard
    case 0x70:                        // Graphics Cursor X
1273 e6e5ad80 bellard
    case 0x90:
1274 e6e5ad80 bellard
    case 0xb0:
1275 e6e5ad80 bellard
    case 0xd0:
1276 e6e5ad80 bellard
    case 0xf0:                        // Graphics Cursor X
1277 aeb3c85f bellard
        *reg_value = s->sr[0x10];
1278 aeb3c85f bellard
        break;
1279 e6e5ad80 bellard
    case 0x11:
1280 e6e5ad80 bellard
    case 0x31:
1281 e6e5ad80 bellard
    case 0x51:
1282 e6e5ad80 bellard
    case 0x71:                        // Graphics Cursor Y
1283 e6e5ad80 bellard
    case 0x91:
1284 e6e5ad80 bellard
    case 0xb1:
1285 e6e5ad80 bellard
    case 0xd1:
1286 a5082316 bellard
    case 0xf1:                        // Graphics Cursor Y
1287 aeb3c85f bellard
        *reg_value = s->sr[0x11];
1288 aeb3c85f bellard
        break;
1289 aeb3c85f bellard
    case 0x05:                        // ???
1290 aeb3c85f bellard
    case 0x07:                        // Extended Sequencer Mode
1291 aeb3c85f bellard
    case 0x08:                        // EEPROM Control
1292 aeb3c85f bellard
    case 0x09:                        // Scratch Register 0
1293 aeb3c85f bellard
    case 0x0a:                        // Scratch Register 1
1294 aeb3c85f bellard
    case 0x0b:                        // VCLK 0
1295 aeb3c85f bellard
    case 0x0c:                        // VCLK 1
1296 aeb3c85f bellard
    case 0x0d:                        // VCLK 2
1297 aeb3c85f bellard
    case 0x0e:                        // VCLK 3
1298 aeb3c85f bellard
    case 0x0f:                        // DRAM Control
1299 e6e5ad80 bellard
    case 0x12:                        // Graphics Cursor Attribute
1300 e6e5ad80 bellard
    case 0x13:                        // Graphics Cursor Pattern Address
1301 e6e5ad80 bellard
    case 0x14:                        // Scratch Register 2
1302 e6e5ad80 bellard
    case 0x15:                        // Scratch Register 3
1303 e6e5ad80 bellard
    case 0x16:                        // Performance Tuning Register
1304 e6e5ad80 bellard
    case 0x17:                        // Configuration Readback and Extended Control
1305 e6e5ad80 bellard
    case 0x18:                        // Signature Generator Control
1306 e6e5ad80 bellard
    case 0x19:                        // Signal Generator Result
1307 e6e5ad80 bellard
    case 0x1a:                        // Signal Generator Result
1308 e6e5ad80 bellard
    case 0x1b:                        // VCLK 0 Denominator & Post
1309 e6e5ad80 bellard
    case 0x1c:                        // VCLK 1 Denominator & Post
1310 e6e5ad80 bellard
    case 0x1d:                        // VCLK 2 Denominator & Post
1311 e6e5ad80 bellard
    case 0x1e:                        // VCLK 3 Denominator & Post
1312 e6e5ad80 bellard
    case 0x1f:                        // BIOS Write Enable and MCLK select
1313 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1314 e6e5ad80 bellard
        printf("cirrus: handled inport sr_index %02x\n", reg_index);
1315 e6e5ad80 bellard
#endif
1316 e6e5ad80 bellard
        *reg_value = s->sr[reg_index];
1317 e6e5ad80 bellard
        break;
1318 e6e5ad80 bellard
    default:
1319 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1320 e6e5ad80 bellard
        printf("cirrus: inport sr_index %02x\n", reg_index);
1321 e6e5ad80 bellard
#endif
1322 e6e5ad80 bellard
        *reg_value = 0xff;
1323 e6e5ad80 bellard
        break;
1324 e6e5ad80 bellard
    }
1325 e6e5ad80 bellard
1326 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1327 e6e5ad80 bellard
}
1328 e6e5ad80 bellard
1329 e6e5ad80 bellard
static int
1330 e6e5ad80 bellard
cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1331 e6e5ad80 bellard
{
1332 e6e5ad80 bellard
    switch (reg_index) {
1333 e6e5ad80 bellard
    case 0x00:                        // Standard VGA
1334 e6e5ad80 bellard
    case 0x01:                        // Standard VGA
1335 e6e5ad80 bellard
    case 0x02:                        // Standard VGA
1336 e6e5ad80 bellard
    case 0x03:                        // Standard VGA
1337 e6e5ad80 bellard
    case 0x04:                        // Standard VGA
1338 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1339 e6e5ad80 bellard
    case 0x06:                        // Unlock Cirrus extensions
1340 e6e5ad80 bellard
        reg_value &= 0x17;
1341 e6e5ad80 bellard
        if (reg_value == 0x12) {
1342 e6e5ad80 bellard
            s->sr[reg_index] = 0x12;
1343 e6e5ad80 bellard
        } else {
1344 e6e5ad80 bellard
            s->sr[reg_index] = 0x0f;
1345 e6e5ad80 bellard
        }
1346 e6e5ad80 bellard
        break;
1347 e6e5ad80 bellard
    case 0x10:
1348 e6e5ad80 bellard
    case 0x30:
1349 e6e5ad80 bellard
    case 0x50:
1350 e6e5ad80 bellard
    case 0x70:                        // Graphics Cursor X
1351 e6e5ad80 bellard
    case 0x90:
1352 e6e5ad80 bellard
    case 0xb0:
1353 e6e5ad80 bellard
    case 0xd0:
1354 e6e5ad80 bellard
    case 0xf0:                        // Graphics Cursor X
1355 e6e5ad80 bellard
        s->sr[0x10] = reg_value;
1356 a5082316 bellard
        s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1357 e6e5ad80 bellard
        break;
1358 e6e5ad80 bellard
    case 0x11:
1359 e6e5ad80 bellard
    case 0x31:
1360 e6e5ad80 bellard
    case 0x51:
1361 e6e5ad80 bellard
    case 0x71:                        // Graphics Cursor Y
1362 e6e5ad80 bellard
    case 0x91:
1363 e6e5ad80 bellard
    case 0xb1:
1364 e6e5ad80 bellard
    case 0xd1:
1365 e6e5ad80 bellard
    case 0xf1:                        // Graphics Cursor Y
1366 e6e5ad80 bellard
        s->sr[0x11] = reg_value;
1367 a5082316 bellard
        s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1368 e6e5ad80 bellard
        break;
1369 e6e5ad80 bellard
    case 0x07:                        // Extended Sequencer Mode
1370 2bec46dc aliguori
    cirrus_update_memory_access(s);
1371 e6e5ad80 bellard
    case 0x08:                        // EEPROM Control
1372 e6e5ad80 bellard
    case 0x09:                        // Scratch Register 0
1373 e6e5ad80 bellard
    case 0x0a:                        // Scratch Register 1
1374 e6e5ad80 bellard
    case 0x0b:                        // VCLK 0
1375 e6e5ad80 bellard
    case 0x0c:                        // VCLK 1
1376 e6e5ad80 bellard
    case 0x0d:                        // VCLK 2
1377 e6e5ad80 bellard
    case 0x0e:                        // VCLK 3
1378 e6e5ad80 bellard
    case 0x0f:                        // DRAM Control
1379 e6e5ad80 bellard
    case 0x12:                        // Graphics Cursor Attribute
1380 e6e5ad80 bellard
    case 0x13:                        // Graphics Cursor Pattern Address
1381 e6e5ad80 bellard
    case 0x14:                        // Scratch Register 2
1382 e6e5ad80 bellard
    case 0x15:                        // Scratch Register 3
1383 e6e5ad80 bellard
    case 0x16:                        // Performance Tuning Register
1384 e6e5ad80 bellard
    case 0x18:                        // Signature Generator Control
1385 e6e5ad80 bellard
    case 0x19:                        // Signature Generator Result
1386 e6e5ad80 bellard
    case 0x1a:                        // Signature Generator Result
1387 e6e5ad80 bellard
    case 0x1b:                        // VCLK 0 Denominator & Post
1388 e6e5ad80 bellard
    case 0x1c:                        // VCLK 1 Denominator & Post
1389 e6e5ad80 bellard
    case 0x1d:                        // VCLK 2 Denominator & Post
1390 e6e5ad80 bellard
    case 0x1e:                        // VCLK 3 Denominator & Post
1391 e6e5ad80 bellard
    case 0x1f:                        // BIOS Write Enable and MCLK select
1392 e6e5ad80 bellard
        s->sr[reg_index] = reg_value;
1393 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1394 e6e5ad80 bellard
        printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1395 e6e5ad80 bellard
               reg_index, reg_value);
1396 e6e5ad80 bellard
#endif
1397 e6e5ad80 bellard
        break;
1398 8926b517 bellard
    case 0x17:                        // Configuration Readback and Extended Control
1399 e3a4e4b6 bellard
        s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1400 8926b517 bellard
        cirrus_update_memory_access(s);
1401 8926b517 bellard
        break;
1402 e6e5ad80 bellard
    default:
1403 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1404 e6e5ad80 bellard
        printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1405 e6e5ad80 bellard
               reg_value);
1406 e6e5ad80 bellard
#endif
1407 e6e5ad80 bellard
        break;
1408 e6e5ad80 bellard
    }
1409 e6e5ad80 bellard
1410 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1411 e6e5ad80 bellard
}
1412 e6e5ad80 bellard
1413 e6e5ad80 bellard
/***************************************
1414 e6e5ad80 bellard
 *
1415 e6e5ad80 bellard
 *  I/O access at 0x3c6
1416 e6e5ad80 bellard
 *
1417 e6e5ad80 bellard
 ***************************************/
1418 e6e5ad80 bellard
1419 e6e5ad80 bellard
static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1420 e6e5ad80 bellard
{
1421 e6e5ad80 bellard
    *reg_value = 0xff;
1422 a21ae81d bellard
    if (++s->cirrus_hidden_dac_lockindex == 5) {
1423 a21ae81d bellard
        *reg_value = s->cirrus_hidden_dac_data;
1424 a21ae81d bellard
        s->cirrus_hidden_dac_lockindex = 0;
1425 e6e5ad80 bellard
    }
1426 e6e5ad80 bellard
}
1427 e6e5ad80 bellard
1428 e6e5ad80 bellard
static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1429 e6e5ad80 bellard
{
1430 e6e5ad80 bellard
    if (s->cirrus_hidden_dac_lockindex == 4) {
1431 e6e5ad80 bellard
        s->cirrus_hidden_dac_data = reg_value;
1432 a21ae81d bellard
#if defined(DEBUG_CIRRUS)
1433 e6e5ad80 bellard
        printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1434 e6e5ad80 bellard
#endif
1435 e6e5ad80 bellard
    }
1436 e6e5ad80 bellard
    s->cirrus_hidden_dac_lockindex = 0;
1437 e6e5ad80 bellard
}
1438 e6e5ad80 bellard
1439 e6e5ad80 bellard
/***************************************
1440 e6e5ad80 bellard
 *
1441 e6e5ad80 bellard
 *  I/O access at 0x3c9
1442 e6e5ad80 bellard
 *
1443 e6e5ad80 bellard
 ***************************************/
1444 e6e5ad80 bellard
1445 e6e5ad80 bellard
static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1446 e6e5ad80 bellard
{
1447 e6e5ad80 bellard
    if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1448 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1449 a5082316 bellard
    *reg_value =
1450 a5082316 bellard
        s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1451 a5082316 bellard
                                 s->dac_sub_index];
1452 e6e5ad80 bellard
    if (++s->dac_sub_index == 3) {
1453 e6e5ad80 bellard
        s->dac_sub_index = 0;
1454 e6e5ad80 bellard
        s->dac_read_index++;
1455 e6e5ad80 bellard
    }
1456 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1457 e6e5ad80 bellard
}
1458 e6e5ad80 bellard
1459 e6e5ad80 bellard
static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1460 e6e5ad80 bellard
{
1461 e6e5ad80 bellard
    if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1462 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1463 e6e5ad80 bellard
    s->dac_cache[s->dac_sub_index] = reg_value;
1464 e6e5ad80 bellard
    if (++s->dac_sub_index == 3) {
1465 a5082316 bellard
        memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1466 a5082316 bellard
               s->dac_cache, 3);
1467 a5082316 bellard
        /* XXX update cursor */
1468 e6e5ad80 bellard
        s->dac_sub_index = 0;
1469 e6e5ad80 bellard
        s->dac_write_index++;
1470 e6e5ad80 bellard
    }
1471 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1472 e6e5ad80 bellard
}
1473 e6e5ad80 bellard
1474 e6e5ad80 bellard
/***************************************
1475 e6e5ad80 bellard
 *
1476 e6e5ad80 bellard
 *  I/O access between 0x3ce-0x3cf
1477 e6e5ad80 bellard
 *
1478 e6e5ad80 bellard
 ***************************************/
1479 e6e5ad80 bellard
1480 e6e5ad80 bellard
static int
1481 e6e5ad80 bellard
cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1482 e6e5ad80 bellard
{
1483 e6e5ad80 bellard
    switch (reg_index) {
1484 aeb3c85f bellard
    case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1485 aeb3c85f bellard
      *reg_value = s->cirrus_shadow_gr0;
1486 aeb3c85f bellard
      return CIRRUS_HOOK_HANDLED;
1487 aeb3c85f bellard
    case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1488 aeb3c85f bellard
      *reg_value = s->cirrus_shadow_gr1;
1489 aeb3c85f bellard
      return CIRRUS_HOOK_HANDLED;
1490 e6e5ad80 bellard
    case 0x02:                        // Standard VGA
1491 e6e5ad80 bellard
    case 0x03:                        // Standard VGA
1492 e6e5ad80 bellard
    case 0x04:                        // Standard VGA
1493 e6e5ad80 bellard
    case 0x06:                        // Standard VGA
1494 e6e5ad80 bellard
    case 0x07:                        // Standard VGA
1495 e6e5ad80 bellard
    case 0x08:                        // Standard VGA
1496 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1497 e6e5ad80 bellard
    case 0x05:                        // Standard VGA, Cirrus extended mode
1498 e6e5ad80 bellard
    default:
1499 e6e5ad80 bellard
        break;
1500 e6e5ad80 bellard
    }
1501 e6e5ad80 bellard
1502 e6e5ad80 bellard
    if (reg_index < 0x3a) {
1503 e6e5ad80 bellard
        *reg_value = s->gr[reg_index];
1504 e6e5ad80 bellard
    } else {
1505 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1506 e6e5ad80 bellard
        printf("cirrus: inport gr_index %02x\n", reg_index);
1507 e6e5ad80 bellard
#endif
1508 e6e5ad80 bellard
        *reg_value = 0xff;
1509 e6e5ad80 bellard
    }
1510 e6e5ad80 bellard
1511 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1512 e6e5ad80 bellard
}
1513 e6e5ad80 bellard
1514 e6e5ad80 bellard
static int
1515 e6e5ad80 bellard
cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1516 e6e5ad80 bellard
{
1517 a5082316 bellard
#if defined(DEBUG_BITBLT) && 0
1518 a5082316 bellard
    printf("gr%02x: %02x\n", reg_index, reg_value);
1519 a5082316 bellard
#endif
1520 e6e5ad80 bellard
    switch (reg_index) {
1521 e6e5ad80 bellard
    case 0x00:                        // Standard VGA, BGCOLOR 0x000000ff
1522 aeb3c85f bellard
        s->cirrus_shadow_gr0 = reg_value;
1523 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1524 e6e5ad80 bellard
    case 0x01:                        // Standard VGA, FGCOLOR 0x000000ff
1525 aeb3c85f bellard
        s->cirrus_shadow_gr1 = reg_value;
1526 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1527 e6e5ad80 bellard
    case 0x02:                        // Standard VGA
1528 e6e5ad80 bellard
    case 0x03:                        // Standard VGA
1529 e6e5ad80 bellard
    case 0x04:                        // Standard VGA
1530 e6e5ad80 bellard
    case 0x06:                        // Standard VGA
1531 e6e5ad80 bellard
    case 0x07:                        // Standard VGA
1532 e6e5ad80 bellard
    case 0x08:                        // Standard VGA
1533 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1534 e6e5ad80 bellard
    case 0x05:                        // Standard VGA, Cirrus extended mode
1535 e6e5ad80 bellard
        s->gr[reg_index] = reg_value & 0x7f;
1536 8926b517 bellard
        cirrus_update_memory_access(s);
1537 e6e5ad80 bellard
        break;
1538 e6e5ad80 bellard
    case 0x09:                        // bank offset #0
1539 e6e5ad80 bellard
    case 0x0A:                        // bank offset #1
1540 8926b517 bellard
        s->gr[reg_index] = reg_value;
1541 8926b517 bellard
        cirrus_update_bank_ptr(s, 0);
1542 8926b517 bellard
        cirrus_update_bank_ptr(s, 1);
1543 2bec46dc aliguori
        cirrus_update_memory_access(s);
1544 8926b517 bellard
        break;
1545 e6e5ad80 bellard
    case 0x0B:
1546 e6e5ad80 bellard
        s->gr[reg_index] = reg_value;
1547 e6e5ad80 bellard
        cirrus_update_bank_ptr(s, 0);
1548 e6e5ad80 bellard
        cirrus_update_bank_ptr(s, 1);
1549 8926b517 bellard
        cirrus_update_memory_access(s);
1550 e6e5ad80 bellard
        break;
1551 e6e5ad80 bellard
    case 0x10:                        // BGCOLOR 0x0000ff00
1552 e6e5ad80 bellard
    case 0x11:                        // FGCOLOR 0x0000ff00
1553 e6e5ad80 bellard
    case 0x12:                        // BGCOLOR 0x00ff0000
1554 e6e5ad80 bellard
    case 0x13:                        // FGCOLOR 0x00ff0000
1555 e6e5ad80 bellard
    case 0x14:                        // BGCOLOR 0xff000000
1556 e6e5ad80 bellard
    case 0x15:                        // FGCOLOR 0xff000000
1557 e6e5ad80 bellard
    case 0x20:                        // BLT WIDTH 0x0000ff
1558 e6e5ad80 bellard
    case 0x22:                        // BLT HEIGHT 0x0000ff
1559 e6e5ad80 bellard
    case 0x24:                        // BLT DEST PITCH 0x0000ff
1560 e6e5ad80 bellard
    case 0x26:                        // BLT SRC PITCH 0x0000ff
1561 e6e5ad80 bellard
    case 0x28:                        // BLT DEST ADDR 0x0000ff
1562 e6e5ad80 bellard
    case 0x29:                        // BLT DEST ADDR 0x00ff00
1563 e6e5ad80 bellard
    case 0x2c:                        // BLT SRC ADDR 0x0000ff
1564 e6e5ad80 bellard
    case 0x2d:                        // BLT SRC ADDR 0x00ff00
1565 a5082316 bellard
    case 0x2f:                  // BLT WRITEMASK
1566 e6e5ad80 bellard
    case 0x30:                        // BLT MODE
1567 e6e5ad80 bellard
    case 0x32:                        // RASTER OP
1568 a21ae81d bellard
    case 0x33:                        // BLT MODEEXT
1569 e6e5ad80 bellard
    case 0x34:                        // BLT TRANSPARENT COLOR 0x00ff
1570 e6e5ad80 bellard
    case 0x35:                        // BLT TRANSPARENT COLOR 0xff00
1571 e6e5ad80 bellard
    case 0x38:                        // BLT TRANSPARENT COLOR MASK 0x00ff
1572 e6e5ad80 bellard
    case 0x39:                        // BLT TRANSPARENT COLOR MASK 0xff00
1573 e6e5ad80 bellard
        s->gr[reg_index] = reg_value;
1574 e6e5ad80 bellard
        break;
1575 e6e5ad80 bellard
    case 0x21:                        // BLT WIDTH 0x001f00
1576 e6e5ad80 bellard
    case 0x23:                        // BLT HEIGHT 0x001f00
1577 e6e5ad80 bellard
    case 0x25:                        // BLT DEST PITCH 0x001f00
1578 e6e5ad80 bellard
    case 0x27:                        // BLT SRC PITCH 0x001f00
1579 e6e5ad80 bellard
        s->gr[reg_index] = reg_value & 0x1f;
1580 e6e5ad80 bellard
        break;
1581 e6e5ad80 bellard
    case 0x2a:                        // BLT DEST ADDR 0x3f0000
1582 a5082316 bellard
        s->gr[reg_index] = reg_value & 0x3f;
1583 a5082316 bellard
        /* if auto start mode, starts bit blt now */
1584 a5082316 bellard
        if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1585 a5082316 bellard
            cirrus_bitblt_start(s);
1586 a5082316 bellard
        }
1587 a5082316 bellard
        break;
1588 e6e5ad80 bellard
    case 0x2e:                        // BLT SRC ADDR 0x3f0000
1589 e6e5ad80 bellard
        s->gr[reg_index] = reg_value & 0x3f;
1590 e6e5ad80 bellard
        break;
1591 e6e5ad80 bellard
    case 0x31:                        // BLT STATUS/START
1592 e6e5ad80 bellard
        cirrus_write_bitblt(s, reg_value);
1593 e6e5ad80 bellard
        break;
1594 e6e5ad80 bellard
    default:
1595 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1596 e6e5ad80 bellard
        printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1597 e6e5ad80 bellard
               reg_value);
1598 e6e5ad80 bellard
#endif
1599 e6e5ad80 bellard
        break;
1600 e6e5ad80 bellard
    }
1601 e6e5ad80 bellard
1602 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1603 e6e5ad80 bellard
}
1604 e6e5ad80 bellard
1605 e6e5ad80 bellard
/***************************************
1606 e6e5ad80 bellard
 *
1607 e6e5ad80 bellard
 *  I/O access between 0x3d4-0x3d5
1608 e6e5ad80 bellard
 *
1609 e6e5ad80 bellard
 ***************************************/
1610 e6e5ad80 bellard
1611 e6e5ad80 bellard
static int
1612 e6e5ad80 bellard
cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1613 e6e5ad80 bellard
{
1614 e6e5ad80 bellard
    switch (reg_index) {
1615 e6e5ad80 bellard
    case 0x00:                        // Standard VGA
1616 e6e5ad80 bellard
    case 0x01:                        // Standard VGA
1617 e6e5ad80 bellard
    case 0x02:                        // Standard VGA
1618 e6e5ad80 bellard
    case 0x03:                        // Standard VGA
1619 e6e5ad80 bellard
    case 0x04:                        // Standard VGA
1620 e6e5ad80 bellard
    case 0x05:                        // Standard VGA
1621 e6e5ad80 bellard
    case 0x06:                        // Standard VGA
1622 e6e5ad80 bellard
    case 0x07:                        // Standard VGA
1623 e6e5ad80 bellard
    case 0x08:                        // Standard VGA
1624 e6e5ad80 bellard
    case 0x09:                        // Standard VGA
1625 e6e5ad80 bellard
    case 0x0a:                        // Standard VGA
1626 e6e5ad80 bellard
    case 0x0b:                        // Standard VGA
1627 e6e5ad80 bellard
    case 0x0c:                        // Standard VGA
1628 e6e5ad80 bellard
    case 0x0d:                        // Standard VGA
1629 e6e5ad80 bellard
    case 0x0e:                        // Standard VGA
1630 e6e5ad80 bellard
    case 0x0f:                        // Standard VGA
1631 e6e5ad80 bellard
    case 0x10:                        // Standard VGA
1632 e6e5ad80 bellard
    case 0x11:                        // Standard VGA
1633 e6e5ad80 bellard
    case 0x12:                        // Standard VGA
1634 e6e5ad80 bellard
    case 0x13:                        // Standard VGA
1635 e6e5ad80 bellard
    case 0x14:                        // Standard VGA
1636 e6e5ad80 bellard
    case 0x15:                        // Standard VGA
1637 e6e5ad80 bellard
    case 0x16:                        // Standard VGA
1638 e6e5ad80 bellard
    case 0x17:                        // Standard VGA
1639 e6e5ad80 bellard
    case 0x18:                        // Standard VGA
1640 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1641 ca896ef3 aurel32
    case 0x24:                        // Attribute Controller Toggle Readback (R)
1642 ca896ef3 aurel32
        *reg_value = (s->ar_flip_flop << 7);
1643 ca896ef3 aurel32
        break;
1644 e6e5ad80 bellard
    case 0x19:                        // Interlace End
1645 e6e5ad80 bellard
    case 0x1a:                        // Miscellaneous Control
1646 e6e5ad80 bellard
    case 0x1b:                        // Extended Display Control
1647 e6e5ad80 bellard
    case 0x1c:                        // Sync Adjust and Genlock
1648 e6e5ad80 bellard
    case 0x1d:                        // Overlay Extended Control
1649 e6e5ad80 bellard
    case 0x22:                        // Graphics Data Latches Readback (R)
1650 e6e5ad80 bellard
    case 0x25:                        // Part Status
1651 e6e5ad80 bellard
    case 0x27:                        // Part ID (R)
1652 e6e5ad80 bellard
        *reg_value = s->cr[reg_index];
1653 e6e5ad80 bellard
        break;
1654 e6e5ad80 bellard
    case 0x26:                        // Attribute Controller Index Readback (R)
1655 e6e5ad80 bellard
        *reg_value = s->ar_index & 0x3f;
1656 e6e5ad80 bellard
        break;
1657 e6e5ad80 bellard
    default:
1658 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1659 e6e5ad80 bellard
        printf("cirrus: inport cr_index %02x\n", reg_index);
1660 e6e5ad80 bellard
        *reg_value = 0xff;
1661 e6e5ad80 bellard
#endif
1662 e6e5ad80 bellard
        break;
1663 e6e5ad80 bellard
    }
1664 e6e5ad80 bellard
1665 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1666 e6e5ad80 bellard
}
1667 e6e5ad80 bellard
1668 e6e5ad80 bellard
static int
1669 e6e5ad80 bellard
cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1670 e6e5ad80 bellard
{
1671 e6e5ad80 bellard
    switch (reg_index) {
1672 e6e5ad80 bellard
    case 0x00:                        // Standard VGA
1673 e6e5ad80 bellard
    case 0x01:                        // Standard VGA
1674 e6e5ad80 bellard
    case 0x02:                        // Standard VGA
1675 e6e5ad80 bellard
    case 0x03:                        // Standard VGA
1676 e6e5ad80 bellard
    case 0x04:                        // Standard VGA
1677 e6e5ad80 bellard
    case 0x05:                        // Standard VGA
1678 e6e5ad80 bellard
    case 0x06:                        // Standard VGA
1679 e6e5ad80 bellard
    case 0x07:                        // Standard VGA
1680 e6e5ad80 bellard
    case 0x08:                        // Standard VGA
1681 e6e5ad80 bellard
    case 0x09:                        // Standard VGA
1682 e6e5ad80 bellard
    case 0x0a:                        // Standard VGA
1683 e6e5ad80 bellard
    case 0x0b:                        // Standard VGA
1684 e6e5ad80 bellard
    case 0x0c:                        // Standard VGA
1685 e6e5ad80 bellard
    case 0x0d:                        // Standard VGA
1686 e6e5ad80 bellard
    case 0x0e:                        // Standard VGA
1687 e6e5ad80 bellard
    case 0x0f:                        // Standard VGA
1688 e6e5ad80 bellard
    case 0x10:                        // Standard VGA
1689 e6e5ad80 bellard
    case 0x11:                        // Standard VGA
1690 e6e5ad80 bellard
    case 0x12:                        // Standard VGA
1691 e6e5ad80 bellard
    case 0x13:                        // Standard VGA
1692 e6e5ad80 bellard
    case 0x14:                        // Standard VGA
1693 e6e5ad80 bellard
    case 0x15:                        // Standard VGA
1694 e6e5ad80 bellard
    case 0x16:                        // Standard VGA
1695 e6e5ad80 bellard
    case 0x17:                        // Standard VGA
1696 e6e5ad80 bellard
    case 0x18:                        // Standard VGA
1697 e6e5ad80 bellard
        return CIRRUS_HOOK_NOT_HANDLED;
1698 e6e5ad80 bellard
    case 0x19:                        // Interlace End
1699 e6e5ad80 bellard
    case 0x1a:                        // Miscellaneous Control
1700 e6e5ad80 bellard
    case 0x1b:                        // Extended Display Control
1701 e6e5ad80 bellard
    case 0x1c:                        // Sync Adjust and Genlock
1702 ae184e4a bellard
    case 0x1d:                        // Overlay Extended Control
1703 e6e5ad80 bellard
        s->cr[reg_index] = reg_value;
1704 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1705 e6e5ad80 bellard
        printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1706 e6e5ad80 bellard
               reg_index, reg_value);
1707 e6e5ad80 bellard
#endif
1708 e6e5ad80 bellard
        break;
1709 e6e5ad80 bellard
    case 0x22:                        // Graphics Data Latches Readback (R)
1710 e6e5ad80 bellard
    case 0x24:                        // Attribute Controller Toggle Readback (R)
1711 e6e5ad80 bellard
    case 0x26:                        // Attribute Controller Index Readback (R)
1712 e6e5ad80 bellard
    case 0x27:                        // Part ID (R)
1713 e6e5ad80 bellard
        break;
1714 e6e5ad80 bellard
    case 0x25:                        // Part Status
1715 e6e5ad80 bellard
    default:
1716 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1717 e6e5ad80 bellard
        printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1718 e6e5ad80 bellard
               reg_value);
1719 e6e5ad80 bellard
#endif
1720 e6e5ad80 bellard
        break;
1721 e6e5ad80 bellard
    }
1722 e6e5ad80 bellard
1723 e6e5ad80 bellard
    return CIRRUS_HOOK_HANDLED;
1724 e6e5ad80 bellard
}
1725 e6e5ad80 bellard
1726 e6e5ad80 bellard
/***************************************
1727 e6e5ad80 bellard
 *
1728 e6e5ad80 bellard
 *  memory-mapped I/O (bitblt)
1729 e6e5ad80 bellard
 *
1730 e6e5ad80 bellard
 ***************************************/
1731 e6e5ad80 bellard
1732 e6e5ad80 bellard
static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1733 e6e5ad80 bellard
{
1734 e6e5ad80 bellard
    int value = 0xff;
1735 e6e5ad80 bellard
1736 e6e5ad80 bellard
    switch (address) {
1737 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1738 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x00, &value);
1739 e6e5ad80 bellard
        break;
1740 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1741 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x10, &value);
1742 e6e5ad80 bellard
        break;
1743 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1744 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x12, &value);
1745 e6e5ad80 bellard
        break;
1746 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1747 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x14, &value);
1748 e6e5ad80 bellard
        break;
1749 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1750 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x01, &value);
1751 e6e5ad80 bellard
        break;
1752 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1753 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x11, &value);
1754 e6e5ad80 bellard
        break;
1755 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1756 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x13, &value);
1757 e6e5ad80 bellard
        break;
1758 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1759 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x15, &value);
1760 e6e5ad80 bellard
        break;
1761 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1762 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x20, &value);
1763 e6e5ad80 bellard
        break;
1764 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1765 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x21, &value);
1766 e6e5ad80 bellard
        break;
1767 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1768 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x22, &value);
1769 e6e5ad80 bellard
        break;
1770 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1771 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x23, &value);
1772 e6e5ad80 bellard
        break;
1773 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1774 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x24, &value);
1775 e6e5ad80 bellard
        break;
1776 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1777 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x25, &value);
1778 e6e5ad80 bellard
        break;
1779 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1780 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x26, &value);
1781 e6e5ad80 bellard
        break;
1782 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1783 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x27, &value);
1784 e6e5ad80 bellard
        break;
1785 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1786 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x28, &value);
1787 e6e5ad80 bellard
        break;
1788 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1789 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x29, &value);
1790 e6e5ad80 bellard
        break;
1791 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1792 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x2a, &value);
1793 e6e5ad80 bellard
        break;
1794 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1795 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x2c, &value);
1796 e6e5ad80 bellard
        break;
1797 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1798 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x2d, &value);
1799 e6e5ad80 bellard
        break;
1800 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1801 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x2e, &value);
1802 e6e5ad80 bellard
        break;
1803 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTWRITEMASK:
1804 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x2f, &value);
1805 e6e5ad80 bellard
        break;
1806 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTMODE:
1807 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x30, &value);
1808 e6e5ad80 bellard
        break;
1809 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTROP:
1810 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x32, &value);
1811 e6e5ad80 bellard
        break;
1812 a21ae81d bellard
    case CIRRUS_MMIO_BLTMODEEXT:
1813 a21ae81d bellard
        cirrus_hook_read_gr(s, 0x33, &value);
1814 a21ae81d bellard
        break;
1815 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1816 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x34, &value);
1817 e6e5ad80 bellard
        break;
1818 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1819 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x35, &value);
1820 e6e5ad80 bellard
        break;
1821 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1822 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x38, &value);
1823 e6e5ad80 bellard
        break;
1824 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1825 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x39, &value);
1826 e6e5ad80 bellard
        break;
1827 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTSTATUS:
1828 e6e5ad80 bellard
        cirrus_hook_read_gr(s, 0x31, &value);
1829 e6e5ad80 bellard
        break;
1830 e6e5ad80 bellard
    default:
1831 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1832 e6e5ad80 bellard
        printf("cirrus: mmio read - address 0x%04x\n", address);
1833 e6e5ad80 bellard
#endif
1834 e6e5ad80 bellard
        break;
1835 e6e5ad80 bellard
    }
1836 e6e5ad80 bellard
1837 e6e5ad80 bellard
    return (uint8_t) value;
1838 e6e5ad80 bellard
}
1839 e6e5ad80 bellard
1840 e6e5ad80 bellard
static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1841 e6e5ad80 bellard
                                  uint8_t value)
1842 e6e5ad80 bellard
{
1843 e6e5ad80 bellard
    switch (address) {
1844 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1845 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x00, value);
1846 e6e5ad80 bellard
        break;
1847 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1848 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x10, value);
1849 e6e5ad80 bellard
        break;
1850 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1851 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x12, value);
1852 e6e5ad80 bellard
        break;
1853 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1854 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x14, value);
1855 e6e5ad80 bellard
        break;
1856 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1857 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x01, value);
1858 e6e5ad80 bellard
        break;
1859 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1860 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x11, value);
1861 e6e5ad80 bellard
        break;
1862 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1863 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x13, value);
1864 e6e5ad80 bellard
        break;
1865 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1866 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x15, value);
1867 e6e5ad80 bellard
        break;
1868 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTWIDTH + 0):
1869 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x20, value);
1870 e6e5ad80 bellard
        break;
1871 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTWIDTH + 1):
1872 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x21, value);
1873 e6e5ad80 bellard
        break;
1874 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTHEIGHT + 0):
1875 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x22, value);
1876 e6e5ad80 bellard
        break;
1877 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTHEIGHT + 1):
1878 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x23, value);
1879 e6e5ad80 bellard
        break;
1880 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1881 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x24, value);
1882 e6e5ad80 bellard
        break;
1883 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1884 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x25, value);
1885 e6e5ad80 bellard
        break;
1886 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1887 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x26, value);
1888 e6e5ad80 bellard
        break;
1889 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1890 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x27, value);
1891 e6e5ad80 bellard
        break;
1892 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 0):
1893 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x28, value);
1894 e6e5ad80 bellard
        break;
1895 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 1):
1896 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x29, value);
1897 e6e5ad80 bellard
        break;
1898 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 2):
1899 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x2a, value);
1900 e6e5ad80 bellard
        break;
1901 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTDESTADDR + 3):
1902 e6e5ad80 bellard
        /* ignored */
1903 e6e5ad80 bellard
        break;
1904 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCADDR + 0):
1905 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x2c, value);
1906 e6e5ad80 bellard
        break;
1907 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCADDR + 1):
1908 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x2d, value);
1909 e6e5ad80 bellard
        break;
1910 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTSRCADDR + 2):
1911 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x2e, value);
1912 e6e5ad80 bellard
        break;
1913 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTWRITEMASK:
1914 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x2f, value);
1915 e6e5ad80 bellard
        break;
1916 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTMODE:
1917 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x30, value);
1918 e6e5ad80 bellard
        break;
1919 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTROP:
1920 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x32, value);
1921 e6e5ad80 bellard
        break;
1922 a21ae81d bellard
    case CIRRUS_MMIO_BLTMODEEXT:
1923 a21ae81d bellard
        cirrus_hook_write_gr(s, 0x33, value);
1924 a21ae81d bellard
        break;
1925 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1926 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x34, value);
1927 e6e5ad80 bellard
        break;
1928 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1929 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x35, value);
1930 e6e5ad80 bellard
        break;
1931 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1932 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x38, value);
1933 e6e5ad80 bellard
        break;
1934 e6e5ad80 bellard
    case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1935 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x39, value);
1936 e6e5ad80 bellard
        break;
1937 e6e5ad80 bellard
    case CIRRUS_MMIO_BLTSTATUS:
1938 e6e5ad80 bellard
        cirrus_hook_write_gr(s, 0x31, value);
1939 e6e5ad80 bellard
        break;
1940 e6e5ad80 bellard
    default:
1941 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
1942 e6e5ad80 bellard
        printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1943 e6e5ad80 bellard
               address, value);
1944 e6e5ad80 bellard
#endif
1945 e6e5ad80 bellard
        break;
1946 e6e5ad80 bellard
    }
1947 e6e5ad80 bellard
}
1948 e6e5ad80 bellard
1949 e6e5ad80 bellard
/***************************************
1950 e6e5ad80 bellard
 *
1951 e6e5ad80 bellard
 *  write mode 4/5
1952 e6e5ad80 bellard
 *
1953 e6e5ad80 bellard
 * assume TARGET_PAGE_SIZE >= 16
1954 e6e5ad80 bellard
 *
1955 e6e5ad80 bellard
 ***************************************/
1956 e6e5ad80 bellard
1957 e6e5ad80 bellard
static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1958 e6e5ad80 bellard
                                             unsigned mode,
1959 e6e5ad80 bellard
                                             unsigned offset,
1960 e6e5ad80 bellard
                                             uint32_t mem_value)
1961 e6e5ad80 bellard
{
1962 e6e5ad80 bellard
    int x;
1963 e6e5ad80 bellard
    unsigned val = mem_value;
1964 e6e5ad80 bellard
    uint8_t *dst;
1965 e6e5ad80 bellard
1966 b2eb849d aurel32
    dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1967 e6e5ad80 bellard
    for (x = 0; x < 8; x++) {
1968 e6e5ad80 bellard
        if (val & 0x80) {
1969 0b74ed78 bellard
            *dst = s->cirrus_shadow_gr1;
1970 e6e5ad80 bellard
        } else if (mode == 5) {
1971 0b74ed78 bellard
            *dst = s->cirrus_shadow_gr0;
1972 e6e5ad80 bellard
        }
1973 e6e5ad80 bellard
        val <<= 1;
1974 0b74ed78 bellard
        dst++;
1975 e6e5ad80 bellard
    }
1976 e6e5ad80 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + offset);
1977 e6e5ad80 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1978 e6e5ad80 bellard
}
1979 e6e5ad80 bellard
1980 e6e5ad80 bellard
static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1981 e6e5ad80 bellard
                                              unsigned mode,
1982 e6e5ad80 bellard
                                              unsigned offset,
1983 e6e5ad80 bellard
                                              uint32_t mem_value)
1984 e6e5ad80 bellard
{
1985 e6e5ad80 bellard
    int x;
1986 e6e5ad80 bellard
    unsigned val = mem_value;
1987 e6e5ad80 bellard
    uint8_t *dst;
1988 e6e5ad80 bellard
1989 b2eb849d aurel32
    dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1990 e6e5ad80 bellard
    for (x = 0; x < 8; x++) {
1991 e6e5ad80 bellard
        if (val & 0x80) {
1992 0b74ed78 bellard
            *dst = s->cirrus_shadow_gr1;
1993 0b74ed78 bellard
            *(dst + 1) = s->gr[0x11];
1994 e6e5ad80 bellard
        } else if (mode == 5) {
1995 0b74ed78 bellard
            *dst = s->cirrus_shadow_gr0;
1996 0b74ed78 bellard
            *(dst + 1) = s->gr[0x10];
1997 e6e5ad80 bellard
        }
1998 e6e5ad80 bellard
        val <<= 1;
1999 0b74ed78 bellard
        dst += 2;
2000 e6e5ad80 bellard
    }
2001 e6e5ad80 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + offset);
2002 e6e5ad80 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
2003 e6e5ad80 bellard
}
2004 e6e5ad80 bellard
2005 e6e5ad80 bellard
/***************************************
2006 e6e5ad80 bellard
 *
2007 e6e5ad80 bellard
 *  memory access between 0xa0000-0xbffff
2008 e6e5ad80 bellard
 *
2009 e6e5ad80 bellard
 ***************************************/
2010 e6e5ad80 bellard
2011 e6e5ad80 bellard
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2012 e6e5ad80 bellard
{
2013 e6e5ad80 bellard
    CirrusVGAState *s = opaque;
2014 e6e5ad80 bellard
    unsigned bank_index;
2015 e6e5ad80 bellard
    unsigned bank_offset;
2016 e6e5ad80 bellard
    uint32_t val;
2017 e6e5ad80 bellard
2018 e6e5ad80 bellard
    if ((s->sr[0x07] & 0x01) == 0) {
2019 e6e5ad80 bellard
        return vga_mem_readb(s, addr);
2020 e6e5ad80 bellard
    }
2021 e6e5ad80 bellard
2022 aeb3c85f bellard
    addr &= 0x1ffff;
2023 aeb3c85f bellard
2024 e6e5ad80 bellard
    if (addr < 0x10000) {
2025 e6e5ad80 bellard
        /* XXX handle bitblt */
2026 e6e5ad80 bellard
        /* video memory */
2027 e6e5ad80 bellard
        bank_index = addr >> 15;
2028 e6e5ad80 bellard
        bank_offset = addr & 0x7fff;
2029 e6e5ad80 bellard
        if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2030 e6e5ad80 bellard
            bank_offset += s->cirrus_bank_base[bank_index];
2031 e6e5ad80 bellard
            if ((s->gr[0x0B] & 0x14) == 0x14) {
2032 e6e5ad80 bellard
                bank_offset <<= 4;
2033 e6e5ad80 bellard
            } else if (s->gr[0x0B] & 0x02) {
2034 e6e5ad80 bellard
                bank_offset <<= 3;
2035 e6e5ad80 bellard
            }
2036 e6e5ad80 bellard
            bank_offset &= s->cirrus_addr_mask;
2037 e6e5ad80 bellard
            val = *(s->vram_ptr + bank_offset);
2038 e6e5ad80 bellard
        } else
2039 e6e5ad80 bellard
            val = 0xff;
2040 e6e5ad80 bellard
    } else if (addr >= 0x18000 && addr < 0x18100) {
2041 e6e5ad80 bellard
        /* memory-mapped I/O */
2042 e6e5ad80 bellard
        val = 0xff;
2043 e6e5ad80 bellard
        if ((s->sr[0x17] & 0x44) == 0x04) {
2044 e6e5ad80 bellard
            val = cirrus_mmio_blt_read(s, addr & 0xff);
2045 e6e5ad80 bellard
        }
2046 e6e5ad80 bellard
    } else {
2047 e6e5ad80 bellard
        val = 0xff;
2048 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
2049 e6e5ad80 bellard
        printf("cirrus: mem_readb %06x\n", addr);
2050 e6e5ad80 bellard
#endif
2051 e6e5ad80 bellard
    }
2052 e6e5ad80 bellard
    return val;
2053 e6e5ad80 bellard
}
2054 e6e5ad80 bellard
2055 e6e5ad80 bellard
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2056 e6e5ad80 bellard
{
2057 e6e5ad80 bellard
    uint32_t v;
2058 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2059 e6e5ad80 bellard
    v = cirrus_vga_mem_readb(opaque, addr) << 8;
2060 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 1);
2061 e6e5ad80 bellard
#else
2062 e6e5ad80 bellard
    v = cirrus_vga_mem_readb(opaque, addr);
2063 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2064 e6e5ad80 bellard
#endif
2065 e6e5ad80 bellard
    return v;
2066 e6e5ad80 bellard
}
2067 e6e5ad80 bellard
2068 e6e5ad80 bellard
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2069 e6e5ad80 bellard
{
2070 e6e5ad80 bellard
    uint32_t v;
2071 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2072 e6e5ad80 bellard
    v = cirrus_vga_mem_readb(opaque, addr) << 24;
2073 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2074 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2075 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 3);
2076 e6e5ad80 bellard
#else
2077 e6e5ad80 bellard
    v = cirrus_vga_mem_readb(opaque, addr);
2078 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2079 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2080 e6e5ad80 bellard
    v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2081 e6e5ad80 bellard
#endif
2082 e6e5ad80 bellard
    return v;
2083 e6e5ad80 bellard
}
2084 e6e5ad80 bellard
2085 5fafdf24 ths
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2086 e6e5ad80 bellard
                                  uint32_t mem_value)
2087 e6e5ad80 bellard
{
2088 e6e5ad80 bellard
    CirrusVGAState *s = opaque;
2089 e6e5ad80 bellard
    unsigned bank_index;
2090 e6e5ad80 bellard
    unsigned bank_offset;
2091 e6e5ad80 bellard
    unsigned mode;
2092 e6e5ad80 bellard
2093 e6e5ad80 bellard
    if ((s->sr[0x07] & 0x01) == 0) {
2094 e6e5ad80 bellard
        vga_mem_writeb(s, addr, mem_value);
2095 e6e5ad80 bellard
        return;
2096 e6e5ad80 bellard
    }
2097 e6e5ad80 bellard
2098 aeb3c85f bellard
    addr &= 0x1ffff;
2099 aeb3c85f bellard
2100 e6e5ad80 bellard
    if (addr < 0x10000) {
2101 e6e5ad80 bellard
        if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2102 e6e5ad80 bellard
            /* bitblt */
2103 e6e5ad80 bellard
            *s->cirrus_srcptr++ = (uint8_t) mem_value;
2104 a5082316 bellard
            if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2105 e6e5ad80 bellard
                cirrus_bitblt_cputovideo_next(s);
2106 e6e5ad80 bellard
            }
2107 e6e5ad80 bellard
        } else {
2108 e6e5ad80 bellard
            /* video memory */
2109 e6e5ad80 bellard
            bank_index = addr >> 15;
2110 e6e5ad80 bellard
            bank_offset = addr & 0x7fff;
2111 e6e5ad80 bellard
            if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2112 e6e5ad80 bellard
                bank_offset += s->cirrus_bank_base[bank_index];
2113 e6e5ad80 bellard
                if ((s->gr[0x0B] & 0x14) == 0x14) {
2114 e6e5ad80 bellard
                    bank_offset <<= 4;
2115 e6e5ad80 bellard
                } else if (s->gr[0x0B] & 0x02) {
2116 e6e5ad80 bellard
                    bank_offset <<= 3;
2117 e6e5ad80 bellard
                }
2118 e6e5ad80 bellard
                bank_offset &= s->cirrus_addr_mask;
2119 e6e5ad80 bellard
                mode = s->gr[0x05] & 0x7;
2120 e6e5ad80 bellard
                if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2121 e6e5ad80 bellard
                    *(s->vram_ptr + bank_offset) = mem_value;
2122 e6e5ad80 bellard
                    cpu_physical_memory_set_dirty(s->vram_offset +
2123 e6e5ad80 bellard
                                                  bank_offset);
2124 e6e5ad80 bellard
                } else {
2125 e6e5ad80 bellard
                    if ((s->gr[0x0B] & 0x14) != 0x14) {
2126 e6e5ad80 bellard
                        cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2127 e6e5ad80 bellard
                                                         bank_offset,
2128 e6e5ad80 bellard
                                                         mem_value);
2129 e6e5ad80 bellard
                    } else {
2130 e6e5ad80 bellard
                        cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2131 e6e5ad80 bellard
                                                          bank_offset,
2132 e6e5ad80 bellard
                                                          mem_value);
2133 e6e5ad80 bellard
                    }
2134 e6e5ad80 bellard
                }
2135 e6e5ad80 bellard
            }
2136 e6e5ad80 bellard
        }
2137 e6e5ad80 bellard
    } else if (addr >= 0x18000 && addr < 0x18100) {
2138 e6e5ad80 bellard
        /* memory-mapped I/O */
2139 e6e5ad80 bellard
        if ((s->sr[0x17] & 0x44) == 0x04) {
2140 e6e5ad80 bellard
            cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2141 e6e5ad80 bellard
        }
2142 e6e5ad80 bellard
    } else {
2143 e6e5ad80 bellard
#ifdef DEBUG_CIRRUS
2144 e6e5ad80 bellard
        printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2145 e6e5ad80 bellard
#endif
2146 e6e5ad80 bellard
    }
2147 e6e5ad80 bellard
}
2148 e6e5ad80 bellard
2149 e6e5ad80 bellard
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2150 e6e5ad80 bellard
{
2151 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2152 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2153 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2154 e6e5ad80 bellard
#else
2155 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2156 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2157 e6e5ad80 bellard
#endif
2158 e6e5ad80 bellard
}
2159 e6e5ad80 bellard
2160 e6e5ad80 bellard
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2161 e6e5ad80 bellard
{
2162 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2163 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2164 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2165 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2166 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2167 e6e5ad80 bellard
#else
2168 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2169 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2170 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2171 e6e5ad80 bellard
    cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2172 e6e5ad80 bellard
#endif
2173 e6e5ad80 bellard
}
2174 e6e5ad80 bellard
2175 e6e5ad80 bellard
static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2176 e6e5ad80 bellard
    cirrus_vga_mem_readb,
2177 e6e5ad80 bellard
    cirrus_vga_mem_readw,
2178 e6e5ad80 bellard
    cirrus_vga_mem_readl,
2179 e6e5ad80 bellard
};
2180 e6e5ad80 bellard
2181 e6e5ad80 bellard
static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2182 e6e5ad80 bellard
    cirrus_vga_mem_writeb,
2183 e6e5ad80 bellard
    cirrus_vga_mem_writew,
2184 e6e5ad80 bellard
    cirrus_vga_mem_writel,
2185 e6e5ad80 bellard
};
2186 e6e5ad80 bellard
2187 e6e5ad80 bellard
/***************************************
2188 e6e5ad80 bellard
 *
2189 a5082316 bellard
 *  hardware cursor
2190 a5082316 bellard
 *
2191 a5082316 bellard
 ***************************************/
2192 a5082316 bellard
2193 a5082316 bellard
static inline void invalidate_cursor1(CirrusVGAState *s)
2194 a5082316 bellard
{
2195 a5082316 bellard
    if (s->last_hw_cursor_size) {
2196 5fafdf24 ths
        vga_invalidate_scanlines((VGAState *)s,
2197 a5082316 bellard
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2198 a5082316 bellard
                                 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2199 a5082316 bellard
    }
2200 a5082316 bellard
}
2201 a5082316 bellard
2202 a5082316 bellard
static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2203 a5082316 bellard
{
2204 a5082316 bellard
    const uint8_t *src;
2205 a5082316 bellard
    uint32_t content;
2206 a5082316 bellard
    int y, y_min, y_max;
2207 a5082316 bellard
2208 78e127ef bellard
    src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2209 a5082316 bellard
    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2210 a5082316 bellard
        src += (s->sr[0x13] & 0x3c) * 256;
2211 a5082316 bellard
        y_min = 64;
2212 a5082316 bellard
        y_max = -1;
2213 a5082316 bellard
        for(y = 0; y < 64; y++) {
2214 a5082316 bellard
            content = ((uint32_t *)src)[0] |
2215 a5082316 bellard
                ((uint32_t *)src)[1] |
2216 a5082316 bellard
                ((uint32_t *)src)[2] |
2217 a5082316 bellard
                ((uint32_t *)src)[3];
2218 a5082316 bellard
            if (content) {
2219 a5082316 bellard
                if (y < y_min)
2220 a5082316 bellard
                    y_min = y;
2221 a5082316 bellard
                if (y > y_max)
2222 a5082316 bellard
                    y_max = y;
2223 a5082316 bellard
            }
2224 a5082316 bellard
            src += 16;
2225 a5082316 bellard
        }
2226 a5082316 bellard
    } else {
2227 a5082316 bellard
        src += (s->sr[0x13] & 0x3f) * 256;
2228 a5082316 bellard
        y_min = 32;
2229 a5082316 bellard
        y_max = -1;
2230 a5082316 bellard
        for(y = 0; y < 32; y++) {
2231 a5082316 bellard
            content = ((uint32_t *)src)[0] |
2232 a5082316 bellard
                ((uint32_t *)(src + 128))[0];
2233 a5082316 bellard
            if (content) {
2234 a5082316 bellard
                if (y < y_min)
2235 a5082316 bellard
                    y_min = y;
2236 a5082316 bellard
                if (y > y_max)
2237 a5082316 bellard
                    y_max = y;
2238 a5082316 bellard
            }
2239 a5082316 bellard
            src += 4;
2240 a5082316 bellard
        }
2241 a5082316 bellard
    }
2242 a5082316 bellard
    if (y_min > y_max) {
2243 a5082316 bellard
        s->last_hw_cursor_y_start = 0;
2244 a5082316 bellard
        s->last_hw_cursor_y_end = 0;
2245 a5082316 bellard
    } else {
2246 a5082316 bellard
        s->last_hw_cursor_y_start = y_min;
2247 a5082316 bellard
        s->last_hw_cursor_y_end = y_max + 1;
2248 a5082316 bellard
    }
2249 a5082316 bellard
}
2250 a5082316 bellard
2251 a5082316 bellard
/* NOTE: we do not currently handle the cursor bitmap change, so we
2252 a5082316 bellard
   update the cursor only if it moves. */
2253 a5082316 bellard
static void cirrus_cursor_invalidate(VGAState *s1)
2254 a5082316 bellard
{
2255 a5082316 bellard
    CirrusVGAState *s = (CirrusVGAState *)s1;
2256 a5082316 bellard
    int size;
2257 a5082316 bellard
2258 a5082316 bellard
    if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2259 a5082316 bellard
        size = 0;
2260 a5082316 bellard
    } else {
2261 a5082316 bellard
        if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2262 a5082316 bellard
            size = 64;
2263 a5082316 bellard
        else
2264 a5082316 bellard
            size = 32;
2265 a5082316 bellard
    }
2266 a5082316 bellard
    /* invalidate last cursor and new cursor if any change */
2267 a5082316 bellard
    if (s->last_hw_cursor_size != size ||
2268 a5082316 bellard
        s->last_hw_cursor_x != s->hw_cursor_x ||
2269 a5082316 bellard
        s->last_hw_cursor_y != s->hw_cursor_y) {
2270 a5082316 bellard
2271 a5082316 bellard
        invalidate_cursor1(s);
2272 3b46e624 ths
2273 a5082316 bellard
        s->last_hw_cursor_size = size;
2274 a5082316 bellard
        s->last_hw_cursor_x = s->hw_cursor_x;
2275 a5082316 bellard
        s->last_hw_cursor_y = s->hw_cursor_y;
2276 a5082316 bellard
        /* compute the real cursor min and max y */
2277 a5082316 bellard
        cirrus_cursor_compute_yrange(s);
2278 a5082316 bellard
        invalidate_cursor1(s);
2279 a5082316 bellard
    }
2280 a5082316 bellard
}
2281 a5082316 bellard
2282 a5082316 bellard
static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2283 a5082316 bellard
{
2284 a5082316 bellard
    CirrusVGAState *s = (CirrusVGAState *)s1;
2285 a5082316 bellard
    int w, h, bpp, x1, x2, poffset;
2286 a5082316 bellard
    unsigned int color0, color1;
2287 a5082316 bellard
    const uint8_t *palette, *src;
2288 a5082316 bellard
    uint32_t content;
2289 3b46e624 ths
2290 5fafdf24 ths
    if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2291 a5082316 bellard
        return;
2292 a5082316 bellard
    /* fast test to see if the cursor intersects with the scan line */
2293 a5082316 bellard
    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2294 a5082316 bellard
        h = 64;
2295 a5082316 bellard
    } else {
2296 a5082316 bellard
        h = 32;
2297 a5082316 bellard
    }
2298 a5082316 bellard
    if (scr_y < s->hw_cursor_y ||
2299 a5082316 bellard
        scr_y >= (s->hw_cursor_y + h))
2300 a5082316 bellard
        return;
2301 3b46e624 ths
2302 78e127ef bellard
    src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2303 a5082316 bellard
    if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2304 a5082316 bellard
        src += (s->sr[0x13] & 0x3c) * 256;
2305 a5082316 bellard
        src += (scr_y - s->hw_cursor_y) * 16;
2306 a5082316 bellard
        poffset = 8;
2307 a5082316 bellard
        content = ((uint32_t *)src)[0] |
2308 a5082316 bellard
            ((uint32_t *)src)[1] |
2309 a5082316 bellard
            ((uint32_t *)src)[2] |
2310 a5082316 bellard
            ((uint32_t *)src)[3];
2311 a5082316 bellard
    } else {
2312 a5082316 bellard
        src += (s->sr[0x13] & 0x3f) * 256;
2313 a5082316 bellard
        src += (scr_y - s->hw_cursor_y) * 4;
2314 a5082316 bellard
        poffset = 128;
2315 a5082316 bellard
        content = ((uint32_t *)src)[0] |
2316 a5082316 bellard
            ((uint32_t *)(src + 128))[0];
2317 a5082316 bellard
    }
2318 a5082316 bellard
    /* if nothing to draw, no need to continue */
2319 a5082316 bellard
    if (!content)
2320 a5082316 bellard
        return;
2321 a5082316 bellard
    w = h;
2322 a5082316 bellard
2323 a5082316 bellard
    x1 = s->hw_cursor_x;
2324 a5082316 bellard
    if (x1 >= s->last_scr_width)
2325 a5082316 bellard
        return;
2326 a5082316 bellard
    x2 = s->hw_cursor_x + w;
2327 a5082316 bellard
    if (x2 > s->last_scr_width)
2328 a5082316 bellard
        x2 = s->last_scr_width;
2329 a5082316 bellard
    w = x2 - x1;
2330 a5082316 bellard
    palette = s->cirrus_hidden_palette;
2331 5fafdf24 ths
    color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2332 5fafdf24 ths
                             c6_to_8(palette[0x0 * 3 + 1]),
2333 a5082316 bellard
                             c6_to_8(palette[0x0 * 3 + 2]));
2334 5fafdf24 ths
    color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2335 5fafdf24 ths
                             c6_to_8(palette[0xf * 3 + 1]),
2336 a5082316 bellard
                             c6_to_8(palette[0xf * 3 + 2]));
2337 0e1f5a0c aliguori
    bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2338 a5082316 bellard
    d1 += x1 * bpp;
2339 0e1f5a0c aliguori
    switch(ds_get_bits_per_pixel(s->ds)) {
2340 a5082316 bellard
    default:
2341 a5082316 bellard
        break;
2342 a5082316 bellard
    case 8:
2343 a5082316 bellard
        vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2344 a5082316 bellard
        break;
2345 a5082316 bellard
    case 15:
2346 a5082316 bellard
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2347 a5082316 bellard
        break;
2348 a5082316 bellard
    case 16:
2349 a5082316 bellard
        vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2350 a5082316 bellard
        break;
2351 a5082316 bellard
    case 32:
2352 a5082316 bellard
        vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2353 a5082316 bellard
        break;
2354 a5082316 bellard
    }
2355 a5082316 bellard
}
2356 a5082316 bellard
2357 a5082316 bellard
/***************************************
2358 a5082316 bellard
 *
2359 e6e5ad80 bellard
 *  LFB memory access
2360 e6e5ad80 bellard
 *
2361 e6e5ad80 bellard
 ***************************************/
2362 e6e5ad80 bellard
2363 e6e5ad80 bellard
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2364 e6e5ad80 bellard
{
2365 e6e5ad80 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2366 e6e5ad80 bellard
    uint32_t ret;
2367 e6e5ad80 bellard
2368 e6e5ad80 bellard
    addr &= s->cirrus_addr_mask;
2369 e6e5ad80 bellard
2370 5fafdf24 ths
    if (((s->sr[0x17] & 0x44) == 0x44) &&
2371 78e127ef bellard
        ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2372 e6e5ad80 bellard
        /* memory-mapped I/O */
2373 e6e5ad80 bellard
        ret = cirrus_mmio_blt_read(s, addr & 0xff);
2374 e6e5ad80 bellard
    } else if (0) {
2375 e6e5ad80 bellard
        /* XXX handle bitblt */
2376 e6e5ad80 bellard
        ret = 0xff;
2377 e6e5ad80 bellard
    } else {
2378 e6e5ad80 bellard
        /* video memory */
2379 e6e5ad80 bellard
        if ((s->gr[0x0B] & 0x14) == 0x14) {
2380 e6e5ad80 bellard
            addr <<= 4;
2381 e6e5ad80 bellard
        } else if (s->gr[0x0B] & 0x02) {
2382 e6e5ad80 bellard
            addr <<= 3;
2383 e6e5ad80 bellard
        }
2384 e6e5ad80 bellard
        addr &= s->cirrus_addr_mask;
2385 e6e5ad80 bellard
        ret = *(s->vram_ptr + addr);
2386 e6e5ad80 bellard
    }
2387 e6e5ad80 bellard
2388 e6e5ad80 bellard
    return ret;
2389 e6e5ad80 bellard
}
2390 e6e5ad80 bellard
2391 e6e5ad80 bellard
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2392 e6e5ad80 bellard
{
2393 e6e5ad80 bellard
    uint32_t v;
2394 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2395 e6e5ad80 bellard
    v = cirrus_linear_readb(opaque, addr) << 8;
2396 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 1);
2397 e6e5ad80 bellard
#else
2398 e6e5ad80 bellard
    v = cirrus_linear_readb(opaque, addr);
2399 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2400 e6e5ad80 bellard
#endif
2401 e6e5ad80 bellard
    return v;
2402 e6e5ad80 bellard
}
2403 e6e5ad80 bellard
2404 e6e5ad80 bellard
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2405 e6e5ad80 bellard
{
2406 e6e5ad80 bellard
    uint32_t v;
2407 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2408 e6e5ad80 bellard
    v = cirrus_linear_readb(opaque, addr) << 24;
2409 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2410 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2411 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 3);
2412 e6e5ad80 bellard
#else
2413 e6e5ad80 bellard
    v = cirrus_linear_readb(opaque, addr);
2414 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2415 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2416 e6e5ad80 bellard
    v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2417 e6e5ad80 bellard
#endif
2418 e6e5ad80 bellard
    return v;
2419 e6e5ad80 bellard
}
2420 e6e5ad80 bellard
2421 e6e5ad80 bellard
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2422 e6e5ad80 bellard
                                 uint32_t val)
2423 e6e5ad80 bellard
{
2424 e6e5ad80 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2425 e6e5ad80 bellard
    unsigned mode;
2426 e6e5ad80 bellard
2427 e6e5ad80 bellard
    addr &= s->cirrus_addr_mask;
2428 3b46e624 ths
2429 5fafdf24 ths
    if (((s->sr[0x17] & 0x44) == 0x44) &&
2430 78e127ef bellard
        ((addr & s->linear_mmio_mask) ==  s->linear_mmio_mask)) {
2431 e6e5ad80 bellard
        /* memory-mapped I/O */
2432 e6e5ad80 bellard
        cirrus_mmio_blt_write(s, addr & 0xff, val);
2433 e6e5ad80 bellard
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2434 e6e5ad80 bellard
        /* bitblt */
2435 e6e5ad80 bellard
        *s->cirrus_srcptr++ = (uint8_t) val;
2436 a5082316 bellard
        if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2437 e6e5ad80 bellard
            cirrus_bitblt_cputovideo_next(s);
2438 e6e5ad80 bellard
        }
2439 e6e5ad80 bellard
    } else {
2440 e6e5ad80 bellard
        /* video memory */
2441 e6e5ad80 bellard
        if ((s->gr[0x0B] & 0x14) == 0x14) {
2442 e6e5ad80 bellard
            addr <<= 4;
2443 e6e5ad80 bellard
        } else if (s->gr[0x0B] & 0x02) {
2444 e6e5ad80 bellard
            addr <<= 3;
2445 e6e5ad80 bellard
        }
2446 e6e5ad80 bellard
        addr &= s->cirrus_addr_mask;
2447 e6e5ad80 bellard
2448 e6e5ad80 bellard
        mode = s->gr[0x05] & 0x7;
2449 e6e5ad80 bellard
        if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2450 e6e5ad80 bellard
            *(s->vram_ptr + addr) = (uint8_t) val;
2451 e6e5ad80 bellard
            cpu_physical_memory_set_dirty(s->vram_offset + addr);
2452 e6e5ad80 bellard
        } else {
2453 e6e5ad80 bellard
            if ((s->gr[0x0B] & 0x14) != 0x14) {
2454 e6e5ad80 bellard
                cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2455 e6e5ad80 bellard
            } else {
2456 e6e5ad80 bellard
                cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2457 e6e5ad80 bellard
            }
2458 e6e5ad80 bellard
        }
2459 e6e5ad80 bellard
    }
2460 e6e5ad80 bellard
}
2461 e6e5ad80 bellard
2462 e6e5ad80 bellard
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2463 e6e5ad80 bellard
                                 uint32_t val)
2464 e6e5ad80 bellard
{
2465 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2466 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2467 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2468 e6e5ad80 bellard
#else
2469 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr, val & 0xff);
2470 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2471 e6e5ad80 bellard
#endif
2472 e6e5ad80 bellard
}
2473 e6e5ad80 bellard
2474 e6e5ad80 bellard
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2475 e6e5ad80 bellard
                                 uint32_t val)
2476 e6e5ad80 bellard
{
2477 e6e5ad80 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2478 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2479 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2480 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2481 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2482 e6e5ad80 bellard
#else
2483 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr, val & 0xff);
2484 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2485 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2486 e6e5ad80 bellard
    cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2487 e6e5ad80 bellard
#endif
2488 e6e5ad80 bellard
}
2489 e6e5ad80 bellard
2490 e6e5ad80 bellard
2491 e6e5ad80 bellard
static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2492 e6e5ad80 bellard
    cirrus_linear_readb,
2493 e6e5ad80 bellard
    cirrus_linear_readw,
2494 e6e5ad80 bellard
    cirrus_linear_readl,
2495 e6e5ad80 bellard
};
2496 e6e5ad80 bellard
2497 e6e5ad80 bellard
static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2498 e6e5ad80 bellard
    cirrus_linear_writeb,
2499 e6e5ad80 bellard
    cirrus_linear_writew,
2500 e6e5ad80 bellard
    cirrus_linear_writel,
2501 e6e5ad80 bellard
};
2502 e6e5ad80 bellard
2503 8926b517 bellard
static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2504 8926b517 bellard
                                     uint32_t val)
2505 8926b517 bellard
{
2506 8926b517 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2507 8926b517 bellard
2508 8926b517 bellard
    addr &= s->cirrus_addr_mask;
2509 8926b517 bellard
    *(s->vram_ptr + addr) = val;
2510 8926b517 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + addr);
2511 8926b517 bellard
}
2512 8926b517 bellard
2513 8926b517 bellard
static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2514 8926b517 bellard
                                     uint32_t val)
2515 8926b517 bellard
{
2516 8926b517 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2517 8926b517 bellard
2518 8926b517 bellard
    addr &= s->cirrus_addr_mask;
2519 8926b517 bellard
    cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2520 8926b517 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + addr);
2521 8926b517 bellard
}
2522 8926b517 bellard
2523 8926b517 bellard
static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2524 8926b517 bellard
                                     uint32_t val)
2525 8926b517 bellard
{
2526 8926b517 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2527 8926b517 bellard
2528 8926b517 bellard
    addr &= s->cirrus_addr_mask;
2529 8926b517 bellard
    cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2530 8926b517 bellard
    cpu_physical_memory_set_dirty(s->vram_offset + addr);
2531 8926b517 bellard
}
2532 8926b517 bellard
2533 a5082316 bellard
/***************************************
2534 a5082316 bellard
 *
2535 a5082316 bellard
 *  system to screen memory access
2536 a5082316 bellard
 *
2537 a5082316 bellard
 ***************************************/
2538 a5082316 bellard
2539 a5082316 bellard
2540 a5082316 bellard
static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2541 a5082316 bellard
{
2542 a5082316 bellard
    uint32_t ret;
2543 a5082316 bellard
2544 a5082316 bellard
    /* XXX handle bitblt */
2545 a5082316 bellard
    ret = 0xff;
2546 a5082316 bellard
    return ret;
2547 a5082316 bellard
}
2548 a5082316 bellard
2549 a5082316 bellard
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2550 a5082316 bellard
{
2551 a5082316 bellard
    uint32_t v;
2552 a5082316 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2553 a5082316 bellard
    v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2554 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2555 a5082316 bellard
#else
2556 a5082316 bellard
    v = cirrus_linear_bitblt_readb(opaque, addr);
2557 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2558 a5082316 bellard
#endif
2559 a5082316 bellard
    return v;
2560 a5082316 bellard
}
2561 a5082316 bellard
2562 a5082316 bellard
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2563 a5082316 bellard
{
2564 a5082316 bellard
    uint32_t v;
2565 a5082316 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2566 a5082316 bellard
    v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2567 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2568 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2569 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2570 a5082316 bellard
#else
2571 a5082316 bellard
    v = cirrus_linear_bitblt_readb(opaque, addr);
2572 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2573 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2574 a5082316 bellard
    v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2575 a5082316 bellard
#endif
2576 a5082316 bellard
    return v;
2577 a5082316 bellard
}
2578 a5082316 bellard
2579 a5082316 bellard
static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2580 a5082316 bellard
                                 uint32_t val)
2581 a5082316 bellard
{
2582 a5082316 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2583 a5082316 bellard
2584 a5082316 bellard
    if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2585 a5082316 bellard
        /* bitblt */
2586 a5082316 bellard
        *s->cirrus_srcptr++ = (uint8_t) val;
2587 a5082316 bellard
        if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2588 a5082316 bellard
            cirrus_bitblt_cputovideo_next(s);
2589 a5082316 bellard
        }
2590 a5082316 bellard
    }
2591 a5082316 bellard
}
2592 a5082316 bellard
2593 a5082316 bellard
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2594 a5082316 bellard
                                 uint32_t val)
2595 a5082316 bellard
{
2596 a5082316 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2597 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2598 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2599 a5082316 bellard
#else
2600 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2601 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2602 a5082316 bellard
#endif
2603 a5082316 bellard
}
2604 a5082316 bellard
2605 a5082316 bellard
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2606 a5082316 bellard
                                 uint32_t val)
2607 a5082316 bellard
{
2608 a5082316 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2609 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2610 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2611 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2612 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2613 a5082316 bellard
#else
2614 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2615 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2616 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2617 a5082316 bellard
    cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2618 a5082316 bellard
#endif
2619 a5082316 bellard
}
2620 a5082316 bellard
2621 a5082316 bellard
2622 a5082316 bellard
static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2623 a5082316 bellard
    cirrus_linear_bitblt_readb,
2624 a5082316 bellard
    cirrus_linear_bitblt_readw,
2625 a5082316 bellard
    cirrus_linear_bitblt_readl,
2626 a5082316 bellard
};
2627 a5082316 bellard
2628 a5082316 bellard
static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2629 a5082316 bellard
    cirrus_linear_bitblt_writeb,
2630 a5082316 bellard
    cirrus_linear_bitblt_writew,
2631 a5082316 bellard
    cirrus_linear_bitblt_writel,
2632 a5082316 bellard
};
2633 a5082316 bellard
2634 2bec46dc aliguori
static void map_linear_vram(CirrusVGAState *s)
2635 2bec46dc aliguori
{
2636 2bec46dc aliguori
2637 2bec46dc aliguori
    if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2638 2bec46dc aliguori
        s->map_addr = s->lfb_addr;
2639 2bec46dc aliguori
        s->map_end = s->lfb_end;
2640 2bec46dc aliguori
        cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2641 2bec46dc aliguori
        vga_dirty_log_start((VGAState *)s);
2642 2bec46dc aliguori
    }
2643 2bec46dc aliguori
2644 2bec46dc aliguori
    if (!s->map_addr)
2645 2bec46dc aliguori
        return;
2646 2bec46dc aliguori
2647 2bec46dc aliguori
    s->lfb_vram_mapped = 0;
2648 2bec46dc aliguori
2649 2bec46dc aliguori
    if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2650 2bec46dc aliguori
        && !((s->sr[0x07] & 0x01) == 0)
2651 2bec46dc aliguori
        && !((s->gr[0x0B] & 0x14) == 0x14)
2652 2bec46dc aliguori
        && !(s->gr[0x0B] & 0x02)) {
2653 2bec46dc aliguori
2654 2bec46dc aliguori
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2655 2bec46dc aliguori
                                    (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2656 2bec46dc aliguori
        cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2657 2bec46dc aliguori
                                    (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2658 2bec46dc aliguori
2659 2bec46dc aliguori
        s->lfb_vram_mapped = 1;
2660 2bec46dc aliguori
        vga_dirty_log_start((VGAState *)s);
2661 2bec46dc aliguori
    }
2662 2bec46dc aliguori
    else {
2663 2bec46dc aliguori
        cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000, s->vga_io_memory);
2664 2bec46dc aliguori
        cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000, s->vga_io_memory);
2665 2bec46dc aliguori
    }
2666 2bec46dc aliguori
2667 2bec46dc aliguori
}
2668 2bec46dc aliguori
2669 2bec46dc aliguori
static void unmap_linear_vram(CirrusVGAState *s)
2670 2bec46dc aliguori
{
2671 2bec46dc aliguori
    if (s->map_addr && s->lfb_addr && s->lfb_end) {
2672 2bec46dc aliguori
        vga_dirty_log_stop((VGAState *)s);
2673 2bec46dc aliguori
        s->map_addr = s->map_end = 0;
2674 2bec46dc aliguori
    }
2675 2bec46dc aliguori
2676 2bec46dc aliguori
    cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2677 2bec46dc aliguori
                                 s->vga_io_memory);
2678 2bec46dc aliguori
}
2679 2bec46dc aliguori
2680 8926b517 bellard
/* Compute the memory access functions */
2681 8926b517 bellard
static void cirrus_update_memory_access(CirrusVGAState *s)
2682 8926b517 bellard
{
2683 8926b517 bellard
    unsigned mode;
2684 8926b517 bellard
2685 8926b517 bellard
    if ((s->sr[0x17] & 0x44) == 0x44) {
2686 8926b517 bellard
        goto generic_io;
2687 8926b517 bellard
    } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2688 8926b517 bellard
        goto generic_io;
2689 8926b517 bellard
    } else {
2690 8926b517 bellard
        if ((s->gr[0x0B] & 0x14) == 0x14) {
2691 8926b517 bellard
            goto generic_io;
2692 8926b517 bellard
        } else if (s->gr[0x0B] & 0x02) {
2693 8926b517 bellard
            goto generic_io;
2694 8926b517 bellard
        }
2695 3b46e624 ths
2696 8926b517 bellard
        mode = s->gr[0x05] & 0x7;
2697 8926b517 bellard
        if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2698 2bec46dc aliguori
            map_linear_vram(s);
2699 8926b517 bellard
            s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2700 8926b517 bellard
            s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2701 8926b517 bellard
            s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2702 8926b517 bellard
        } else {
2703 8926b517 bellard
        generic_io:
2704 2bec46dc aliguori
            unmap_linear_vram(s);
2705 8926b517 bellard
            s->cirrus_linear_write[0] = cirrus_linear_writeb;
2706 8926b517 bellard
            s->cirrus_linear_write[1] = cirrus_linear_writew;
2707 8926b517 bellard
            s->cirrus_linear_write[2] = cirrus_linear_writel;
2708 8926b517 bellard
        }
2709 8926b517 bellard
    }
2710 8926b517 bellard
}
2711 8926b517 bellard
2712 8926b517 bellard
2713 e6e5ad80 bellard
/* I/O ports */
2714 e6e5ad80 bellard
2715 e6e5ad80 bellard
static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2716 e6e5ad80 bellard
{
2717 e6e5ad80 bellard
    CirrusVGAState *s = opaque;
2718 e6e5ad80 bellard
    int val, index;
2719 e6e5ad80 bellard
2720 e6e5ad80 bellard
    /* check port range access depending on color/monochrome mode */
2721 e6e5ad80 bellard
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2722 e6e5ad80 bellard
        || (addr >= 0x3d0 && addr <= 0x3df
2723 e6e5ad80 bellard
            && !(s->msr & MSR_COLOR_EMULATION))) {
2724 e6e5ad80 bellard
        val = 0xff;
2725 e6e5ad80 bellard
    } else {
2726 e6e5ad80 bellard
        switch (addr) {
2727 e6e5ad80 bellard
        case 0x3c0:
2728 e6e5ad80 bellard
            if (s->ar_flip_flop == 0) {
2729 e6e5ad80 bellard
                val = s->ar_index;
2730 e6e5ad80 bellard
            } else {
2731 e6e5ad80 bellard
                val = 0;
2732 e6e5ad80 bellard
            }
2733 e6e5ad80 bellard
            break;
2734 e6e5ad80 bellard
        case 0x3c1:
2735 e6e5ad80 bellard
            index = s->ar_index & 0x1f;
2736 e6e5ad80 bellard
            if (index < 21)
2737 e6e5ad80 bellard
                val = s->ar[index];
2738 e6e5ad80 bellard
            else
2739 e6e5ad80 bellard
                val = 0;
2740 e6e5ad80 bellard
            break;
2741 e6e5ad80 bellard
        case 0x3c2:
2742 e6e5ad80 bellard
            val = s->st00;
2743 e6e5ad80 bellard
            break;
2744 e6e5ad80 bellard
        case 0x3c4:
2745 e6e5ad80 bellard
            val = s->sr_index;
2746 e6e5ad80 bellard
            break;
2747 e6e5ad80 bellard
        case 0x3c5:
2748 e6e5ad80 bellard
            if (cirrus_hook_read_sr(s, s->sr_index, &val))
2749 e6e5ad80 bellard
                break;
2750 e6e5ad80 bellard
            val = s->sr[s->sr_index];
2751 e6e5ad80 bellard
#ifdef DEBUG_VGA_REG
2752 e6e5ad80 bellard
            printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2753 e6e5ad80 bellard
#endif
2754 e6e5ad80 bellard
            break;
2755 e6e5ad80 bellard
        case 0x3c6:
2756 e6e5ad80 bellard
            cirrus_read_hidden_dac(s, &val);
2757 e6e5ad80 bellard
            break;
2758 e6e5ad80 bellard
        case 0x3c7:
2759 e6e5ad80 bellard
            val = s->dac_state;
2760 e6e5ad80 bellard
            break;
2761 ae184e4a bellard
        case 0x3c8:
2762 ae184e4a bellard
            val = s->dac_write_index;
2763 ae184e4a bellard
            s->cirrus_hidden_dac_lockindex = 0;
2764 ae184e4a bellard
            break;
2765 ae184e4a bellard
        case 0x3c9:
2766 e6e5ad80 bellard
            if (cirrus_hook_read_palette(s, &val))
2767 e6e5ad80 bellard
                break;
2768 e6e5ad80 bellard
            val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2769 e6e5ad80 bellard
            if (++s->dac_sub_index == 3) {
2770 e6e5ad80 bellard
                s->dac_sub_index = 0;
2771 e6e5ad80 bellard
                s->dac_read_index++;
2772 e6e5ad80 bellard
            }
2773 e6e5ad80 bellard
            break;
2774 e6e5ad80 bellard
        case 0x3ca:
2775 e6e5ad80 bellard
            val = s->fcr;
2776 e6e5ad80 bellard
            break;
2777 e6e5ad80 bellard
        case 0x3cc:
2778 e6e5ad80 bellard
            val = s->msr;
2779 e6e5ad80 bellard
            break;
2780 e6e5ad80 bellard
        case 0x3ce:
2781 e6e5ad80 bellard
            val = s->gr_index;
2782 e6e5ad80 bellard
            break;
2783 e6e5ad80 bellard
        case 0x3cf:
2784 e6e5ad80 bellard
            if (cirrus_hook_read_gr(s, s->gr_index, &val))
2785 e6e5ad80 bellard
                break;
2786 e6e5ad80 bellard
            val = s->gr[s->gr_index];
2787 e6e5ad80 bellard
#ifdef DEBUG_VGA_REG
2788 e6e5ad80 bellard
            printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2789 e6e5ad80 bellard
#endif
2790 e6e5ad80 bellard
            break;
2791 e6e5ad80 bellard
        case 0x3b4:
2792 e6e5ad80 bellard
        case 0x3d4:
2793 e6e5ad80 bellard
            val = s->cr_index;
2794 e6e5ad80 bellard
            break;
2795 e6e5ad80 bellard
        case 0x3b5:
2796 e6e5ad80 bellard
        case 0x3d5:
2797 e6e5ad80 bellard
            if (cirrus_hook_read_cr(s, s->cr_index, &val))
2798 e6e5ad80 bellard
                break;
2799 e6e5ad80 bellard
            val = s->cr[s->cr_index];
2800 e6e5ad80 bellard
#ifdef DEBUG_VGA_REG
2801 e6e5ad80 bellard
            printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2802 e6e5ad80 bellard
#endif
2803 e6e5ad80 bellard
            break;
2804 e6e5ad80 bellard
        case 0x3ba:
2805 e6e5ad80 bellard
        case 0x3da:
2806 e6e5ad80 bellard
            /* just toggle to fool polling */
2807 cb5a7aa8 malc
            val = s->st01 = s->retrace((VGAState *) s);
2808 e6e5ad80 bellard
            s->ar_flip_flop = 0;
2809 e6e5ad80 bellard
            break;
2810 e6e5ad80 bellard
        default:
2811 e6e5ad80 bellard
            val = 0x00;
2812 e6e5ad80 bellard
            break;
2813 e6e5ad80 bellard
        }
2814 e6e5ad80 bellard
    }
2815 e6e5ad80 bellard
#if defined(DEBUG_VGA)
2816 e6e5ad80 bellard
    printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2817 e6e5ad80 bellard
#endif
2818 e6e5ad80 bellard
    return val;
2819 e6e5ad80 bellard
}
2820 e6e5ad80 bellard
2821 e6e5ad80 bellard
static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2822 e6e5ad80 bellard
{
2823 e6e5ad80 bellard
    CirrusVGAState *s = opaque;
2824 e6e5ad80 bellard
    int index;
2825 e6e5ad80 bellard
2826 e6e5ad80 bellard
    /* check port range access depending on color/monochrome mode */
2827 e6e5ad80 bellard
    if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2828 e6e5ad80 bellard
        || (addr >= 0x3d0 && addr <= 0x3df
2829 e6e5ad80 bellard
            && !(s->msr & MSR_COLOR_EMULATION)))
2830 e6e5ad80 bellard
        return;
2831 e6e5ad80 bellard
2832 e6e5ad80 bellard
#ifdef DEBUG_VGA
2833 e6e5ad80 bellard
    printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2834 e6e5ad80 bellard
#endif
2835 e6e5ad80 bellard
2836 e6e5ad80 bellard
    switch (addr) {
2837 e6e5ad80 bellard
    case 0x3c0:
2838 e6e5ad80 bellard
        if (s->ar_flip_flop == 0) {
2839 e6e5ad80 bellard
            val &= 0x3f;
2840 e6e5ad80 bellard
            s->ar_index = val;
2841 e6e5ad80 bellard
        } else {
2842 e6e5ad80 bellard
            index = s->ar_index & 0x1f;
2843 e6e5ad80 bellard
            switch (index) {
2844 e6e5ad80 bellard
            case 0x00 ... 0x0f:
2845 e6e5ad80 bellard
                s->ar[index] = val & 0x3f;
2846 e6e5ad80 bellard
                break;
2847 e6e5ad80 bellard
            case 0x10:
2848 e6e5ad80 bellard
                s->ar[index] = val & ~0x10;
2849 e6e5ad80 bellard
                break;
2850 e6e5ad80 bellard
            case 0x11:
2851 e6e5ad80 bellard
                s->ar[index] = val;
2852 e6e5ad80 bellard
                break;
2853 e6e5ad80 bellard
            case 0x12:
2854 e6e5ad80 bellard
                s->ar[index] = val & ~0xc0;
2855 e6e5ad80 bellard
                break;
2856 e6e5ad80 bellard
            case 0x13:
2857 e6e5ad80 bellard
                s->ar[index] = val & ~0xf0;
2858 e6e5ad80 bellard
                break;
2859 e6e5ad80 bellard
            case 0x14:
2860 e6e5ad80 bellard
                s->ar[index] = val & ~0xf0;
2861 e6e5ad80 bellard
                break;
2862 e6e5ad80 bellard
            default:
2863 e6e5ad80 bellard
                break;
2864 e6e5ad80 bellard
            }
2865 e6e5ad80 bellard
        }
2866 e6e5ad80 bellard
        s->ar_flip_flop ^= 1;
2867 e6e5ad80 bellard
        break;
2868 e6e5ad80 bellard
    case 0x3c2:
2869 e6e5ad80 bellard
        s->msr = val & ~0x10;
2870 cb5a7aa8 malc
        s->update_retrace_info((VGAState *) s);
2871 e6e5ad80 bellard
        break;
2872 e6e5ad80 bellard
    case 0x3c4:
2873 e6e5ad80 bellard
        s->sr_index = val;
2874 e6e5ad80 bellard
        break;
2875 e6e5ad80 bellard
    case 0x3c5:
2876 e6e5ad80 bellard
        if (cirrus_hook_write_sr(s, s->sr_index, val))
2877 e6e5ad80 bellard
            break;
2878 e6e5ad80 bellard
#ifdef DEBUG_VGA_REG
2879 e6e5ad80 bellard
        printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2880 e6e5ad80 bellard
#endif
2881 e6e5ad80 bellard
        s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2882 cb5a7aa8 malc
        if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2883 e6e5ad80 bellard
        break;
2884 e6e5ad80 bellard
    case 0x3c6:
2885 e6e5ad80 bellard
        cirrus_write_hidden_dac(s, val);
2886 e6e5ad80 bellard
        break;
2887 e6e5ad80 bellard
    case 0x3c7:
2888 e6e5ad80 bellard
        s->dac_read_index = val;
2889 e6e5ad80 bellard
        s->dac_sub_index = 0;
2890 e6e5ad80 bellard
        s->dac_state = 3;
2891 e6e5ad80 bellard
        break;
2892 e6e5ad80 bellard
    case 0x3c8:
2893 e6e5ad80 bellard
        s->dac_write_index = val;
2894 e6e5ad80 bellard
        s->dac_sub_index = 0;
2895 e6e5ad80 bellard
        s->dac_state = 0;
2896 e6e5ad80 bellard
        break;
2897 e6e5ad80 bellard
    case 0x3c9:
2898 e6e5ad80 bellard
        if (cirrus_hook_write_palette(s, val))
2899 e6e5ad80 bellard
            break;
2900 e6e5ad80 bellard
        s->dac_cache[s->dac_sub_index] = val;
2901 e6e5ad80 bellard
        if (++s->dac_sub_index == 3) {
2902 e6e5ad80 bellard
            memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2903 e6e5ad80 bellard
            s->dac_sub_index = 0;
2904 e6e5ad80 bellard
            s->dac_write_index++;
2905 e6e5ad80 bellard
        }
2906 e6e5ad80 bellard
        break;
2907 e6e5ad80 bellard
    case 0x3ce:
2908 e6e5ad80 bellard
        s->gr_index = val;
2909 e6e5ad80 bellard
        break;
2910 e6e5ad80 bellard
    case 0x3cf:
2911 e6e5ad80 bellard
        if (cirrus_hook_write_gr(s, s->gr_index, val))
2912 e6e5ad80 bellard
            break;
2913 e6e5ad80 bellard
#ifdef DEBUG_VGA_REG
2914 e6e5ad80 bellard
        printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2915 e6e5ad80 bellard
#endif
2916 e6e5ad80 bellard
        s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2917 e6e5ad80 bellard
        break;
2918 e6e5ad80 bellard
    case 0x3b4:
2919 e6e5ad80 bellard
    case 0x3d4:
2920 e6e5ad80 bellard
        s->cr_index = val;
2921 e6e5ad80 bellard
        break;
2922 e6e5ad80 bellard
    case 0x3b5:
2923 e6e5ad80 bellard
    case 0x3d5:
2924 e6e5ad80 bellard
        if (cirrus_hook_write_cr(s, s->cr_index, val))
2925 e6e5ad80 bellard
            break;
2926 e6e5ad80 bellard
#ifdef DEBUG_VGA_REG
2927 e6e5ad80 bellard
        printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2928 e6e5ad80 bellard
#endif
2929 e6e5ad80 bellard
        /* handle CR0-7 protection */
2930 9bb34eac bellard
        if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2931 e6e5ad80 bellard
            /* can always write bit 4 of CR7 */
2932 e6e5ad80 bellard
            if (s->cr_index == 7)
2933 e6e5ad80 bellard
                s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2934 e6e5ad80 bellard
            return;
2935 e6e5ad80 bellard
        }
2936 e6e5ad80 bellard
        switch (s->cr_index) {
2937 e6e5ad80 bellard
        case 0x01:                /* horizontal display end */
2938 e6e5ad80 bellard
        case 0x07:
2939 e6e5ad80 bellard
        case 0x09:
2940 e6e5ad80 bellard
        case 0x0c:
2941 e6e5ad80 bellard
        case 0x0d:
2942 e91c8a77 ths
        case 0x12:                /* vertical display end */
2943 e6e5ad80 bellard
            s->cr[s->cr_index] = val;
2944 e6e5ad80 bellard
            break;
2945 e6e5ad80 bellard
2946 e6e5ad80 bellard
        default:
2947 e6e5ad80 bellard
            s->cr[s->cr_index] = val;
2948 e6e5ad80 bellard
            break;
2949 e6e5ad80 bellard
        }
2950 cb5a7aa8 malc
2951 cb5a7aa8 malc
        switch(s->cr_index) {
2952 cb5a7aa8 malc
        case 0x00:
2953 cb5a7aa8 malc
        case 0x04:
2954 cb5a7aa8 malc
        case 0x05:
2955 cb5a7aa8 malc
        case 0x06:
2956 cb5a7aa8 malc
        case 0x07:
2957 cb5a7aa8 malc
        case 0x11:
2958 cb5a7aa8 malc
        case 0x17:
2959 cb5a7aa8 malc
            s->update_retrace_info((VGAState *) s);
2960 cb5a7aa8 malc
            break;
2961 cb5a7aa8 malc
        }
2962 e6e5ad80 bellard
        break;
2963 e6e5ad80 bellard
    case 0x3ba:
2964 e6e5ad80 bellard
    case 0x3da:
2965 e6e5ad80 bellard
        s->fcr = val & 0x10;
2966 e6e5ad80 bellard
        break;
2967 e6e5ad80 bellard
    }
2968 e6e5ad80 bellard
}
2969 e6e5ad80 bellard
2970 e6e5ad80 bellard
/***************************************
2971 e6e5ad80 bellard
 *
2972 e36f36e1 bellard
 *  memory-mapped I/O access
2973 e36f36e1 bellard
 *
2974 e36f36e1 bellard
 ***************************************/
2975 e36f36e1 bellard
2976 e36f36e1 bellard
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2977 e36f36e1 bellard
{
2978 e36f36e1 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
2979 e36f36e1 bellard
2980 e36f36e1 bellard
    addr &= CIRRUS_PNPMMIO_SIZE - 1;
2981 e36f36e1 bellard
2982 e36f36e1 bellard
    if (addr >= 0x100) {
2983 e36f36e1 bellard
        return cirrus_mmio_blt_read(s, addr - 0x100);
2984 e36f36e1 bellard
    } else {
2985 e36f36e1 bellard
        return vga_ioport_read(s, addr + 0x3c0);
2986 e36f36e1 bellard
    }
2987 e36f36e1 bellard
}
2988 e36f36e1 bellard
2989 e36f36e1 bellard
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2990 e36f36e1 bellard
{
2991 e36f36e1 bellard
    uint32_t v;
2992 e36f36e1 bellard
#ifdef TARGET_WORDS_BIGENDIAN
2993 e36f36e1 bellard
    v = cirrus_mmio_readb(opaque, addr) << 8;
2994 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 1);
2995 e36f36e1 bellard
#else
2996 e36f36e1 bellard
    v = cirrus_mmio_readb(opaque, addr);
2997 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2998 e36f36e1 bellard
#endif
2999 e36f36e1 bellard
    return v;
3000 e36f36e1 bellard
}
3001 e36f36e1 bellard
3002 e36f36e1 bellard
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3003 e36f36e1 bellard
{
3004 e36f36e1 bellard
    uint32_t v;
3005 e36f36e1 bellard
#ifdef TARGET_WORDS_BIGENDIAN
3006 e36f36e1 bellard
    v = cirrus_mmio_readb(opaque, addr) << 24;
3007 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3008 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3009 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 3);
3010 e36f36e1 bellard
#else
3011 e36f36e1 bellard
    v = cirrus_mmio_readb(opaque, addr);
3012 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3013 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3014 e36f36e1 bellard
    v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3015 e36f36e1 bellard
#endif
3016 e36f36e1 bellard
    return v;
3017 e36f36e1 bellard
}
3018 e36f36e1 bellard
3019 e36f36e1 bellard
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3020 e36f36e1 bellard
                               uint32_t val)
3021 e36f36e1 bellard
{
3022 e36f36e1 bellard
    CirrusVGAState *s = (CirrusVGAState *) opaque;
3023 e36f36e1 bellard
3024 e36f36e1 bellard
    addr &= CIRRUS_PNPMMIO_SIZE - 1;
3025 e36f36e1 bellard
3026 e36f36e1 bellard
    if (addr >= 0x100) {
3027 e36f36e1 bellard
        cirrus_mmio_blt_write(s, addr - 0x100, val);
3028 e36f36e1 bellard
    } else {
3029 e36f36e1 bellard
        vga_ioport_write(s, addr + 0x3c0, val);
3030 e36f36e1 bellard
    }
3031 e36f36e1 bellard
}
3032 e36f36e1 bellard
3033 e36f36e1 bellard
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3034 e36f36e1 bellard
                               uint32_t val)
3035 e36f36e1 bellard
{
3036 e36f36e1 bellard
#ifdef TARGET_WORDS_BIGENDIAN
3037 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3038 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3039 e36f36e1 bellard
#else
3040 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr, val & 0xff);
3041 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3042 e36f36e1 bellard
#endif
3043 e36f36e1 bellard
}
3044 e36f36e1 bellard
3045 e36f36e1 bellard
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3046 e36f36e1 bellard
                               uint32_t val)
3047 e36f36e1 bellard
{
3048 e36f36e1 bellard
#ifdef TARGET_WORDS_BIGENDIAN
3049 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3050 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3051 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3052 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3053 e36f36e1 bellard
#else
3054 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr, val & 0xff);
3055 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3056 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3057 e36f36e1 bellard
    cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3058 e36f36e1 bellard
#endif
3059 e36f36e1 bellard
}
3060 e36f36e1 bellard
3061 e36f36e1 bellard
3062 e36f36e1 bellard
static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3063 e36f36e1 bellard
    cirrus_mmio_readb,
3064 e36f36e1 bellard
    cirrus_mmio_readw,
3065 e36f36e1 bellard
    cirrus_mmio_readl,
3066 e36f36e1 bellard
};
3067 e36f36e1 bellard
3068 e36f36e1 bellard
static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3069 e36f36e1 bellard
    cirrus_mmio_writeb,
3070 e36f36e1 bellard
    cirrus_mmio_writew,
3071 e36f36e1 bellard
    cirrus_mmio_writel,
3072 e36f36e1 bellard
};
3073 e36f36e1 bellard
3074 2c6ab832 bellard
/* load/save state */
3075 2c6ab832 bellard
3076 2c6ab832 bellard
static void cirrus_vga_save(QEMUFile *f, void *opaque)
3077 2c6ab832 bellard
{
3078 2c6ab832 bellard
    CirrusVGAState *s = opaque;
3079 2c6ab832 bellard
3080 d2269f6f bellard
    if (s->pci_dev)
3081 d2269f6f bellard
        pci_device_save(s->pci_dev, f);
3082 d2269f6f bellard
3083 2c6ab832 bellard
    qemu_put_be32s(f, &s->latch);
3084 2c6ab832 bellard
    qemu_put_8s(f, &s->sr_index);
3085 2c6ab832 bellard
    qemu_put_buffer(f, s->sr, 256);
3086 2c6ab832 bellard
    qemu_put_8s(f, &s->gr_index);
3087 2c6ab832 bellard
    qemu_put_8s(f, &s->cirrus_shadow_gr0);
3088 2c6ab832 bellard
    qemu_put_8s(f, &s->cirrus_shadow_gr1);
3089 2c6ab832 bellard
    qemu_put_buffer(f, s->gr + 2, 254);
3090 2c6ab832 bellard
    qemu_put_8s(f, &s->ar_index);
3091 2c6ab832 bellard
    qemu_put_buffer(f, s->ar, 21);
3092 bee8d684 ths
    qemu_put_be32(f, s->ar_flip_flop);
3093 2c6ab832 bellard
    qemu_put_8s(f, &s->cr_index);
3094 2c6ab832 bellard
    qemu_put_buffer(f, s->cr, 256);
3095 2c6ab832 bellard
    qemu_put_8s(f, &s->msr);
3096 2c6ab832 bellard
    qemu_put_8s(f, &s->fcr);
3097 2c6ab832 bellard
    qemu_put_8s(f, &s->st00);
3098 2c6ab832 bellard
    qemu_put_8s(f, &s->st01);
3099 2c6ab832 bellard
3100 2c6ab832 bellard
    qemu_put_8s(f, &s->dac_state);
3101 2c6ab832 bellard
    qemu_put_8s(f, &s->dac_sub_index);
3102 2c6ab832 bellard
    qemu_put_8s(f, &s->dac_read_index);
3103 2c6ab832 bellard
    qemu_put_8s(f, &s->dac_write_index);
3104 2c6ab832 bellard
    qemu_put_buffer(f, s->dac_cache, 3);
3105 2c6ab832 bellard
    qemu_put_buffer(f, s->palette, 768);
3106 2c6ab832 bellard
3107 bee8d684 ths
    qemu_put_be32(f, s->bank_offset);
3108 2c6ab832 bellard
3109 2c6ab832 bellard
    qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3110 2c6ab832 bellard
    qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3111 2c6ab832 bellard
3112 2c6ab832 bellard
    qemu_put_be32s(f, &s->hw_cursor_x);
3113 2c6ab832 bellard
    qemu_put_be32s(f, &s->hw_cursor_y);
3114 2c6ab832 bellard
    /* XXX: we do not save the bitblt state - we assume we do not save
3115 2c6ab832 bellard
       the state when the blitter is active */
3116 2c6ab832 bellard
}
3117 2c6ab832 bellard
3118 2c6ab832 bellard
static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3119 2c6ab832 bellard
{
3120 2c6ab832 bellard
    CirrusVGAState *s = opaque;
3121 d2269f6f bellard
    int ret;
3122 2c6ab832 bellard
3123 d2269f6f bellard
    if (version_id > 2)
3124 2c6ab832 bellard
        return -EINVAL;
3125 2c6ab832 bellard
3126 d2269f6f bellard
    if (s->pci_dev && version_id >= 2) {
3127 d2269f6f bellard
        ret = pci_device_load(s->pci_dev, f);
3128 d2269f6f bellard
        if (ret < 0)
3129 d2269f6f bellard
            return ret;
3130 d2269f6f bellard
    }
3131 d2269f6f bellard
3132 2c6ab832 bellard
    qemu_get_be32s(f, &s->latch);
3133 2c6ab832 bellard
    qemu_get_8s(f, &s->sr_index);
3134 2c6ab832 bellard
    qemu_get_buffer(f, s->sr, 256);
3135 2c6ab832 bellard
    qemu_get_8s(f, &s->gr_index);
3136 2c6ab832 bellard
    qemu_get_8s(f, &s->cirrus_shadow_gr0);
3137 2c6ab832 bellard
    qemu_get_8s(f, &s->cirrus_shadow_gr1);
3138 2c6ab832 bellard
    s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3139 2c6ab832 bellard
    s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3140 2c6ab832 bellard
    qemu_get_buffer(f, s->gr + 2, 254);
3141 2c6ab832 bellard
    qemu_get_8s(f, &s->ar_index);
3142 2c6ab832 bellard
    qemu_get_buffer(f, s->ar, 21);
3143 bee8d684 ths
    s->ar_flip_flop=qemu_get_be32(f);
3144 2c6ab832 bellard
    qemu_get_8s(f, &s->cr_index);
3145 2c6ab832 bellard
    qemu_get_buffer(f, s->cr, 256);
3146 2c6ab832 bellard
    qemu_get_8s(f, &s->msr);
3147 2c6ab832 bellard
    qemu_get_8s(f, &s->fcr);
3148 2c6ab832 bellard
    qemu_get_8s(f, &s->st00);
3149 2c6ab832 bellard
    qemu_get_8s(f, &s->st01);
3150 2c6ab832 bellard
3151 2c6ab832 bellard
    qemu_get_8s(f, &s->dac_state);
3152 2c6ab832 bellard
    qemu_get_8s(f, &s->dac_sub_index);
3153 2c6ab832 bellard
    qemu_get_8s(f, &s->dac_read_index);
3154 2c6ab832 bellard
    qemu_get_8s(f, &s->dac_write_index);
3155 2c6ab832 bellard
    qemu_get_buffer(f, s->dac_cache, 3);
3156 2c6ab832 bellard
    qemu_get_buffer(f, s->palette, 768);
3157 2c6ab832 bellard
3158 bee8d684 ths
    s->bank_offset=qemu_get_be32(f);
3159 2c6ab832 bellard
3160 2c6ab832 bellard
    qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3161 2c6ab832 bellard
    qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3162 2c6ab832 bellard
3163 2c6ab832 bellard
    qemu_get_be32s(f, &s->hw_cursor_x);
3164 2c6ab832 bellard
    qemu_get_be32s(f, &s->hw_cursor_y);
3165 2c6ab832 bellard
3166 2bec46dc aliguori
    cirrus_update_memory_access(s);
3167 2c6ab832 bellard
    /* force refresh */
3168 2c6ab832 bellard
    s->graphic_mode = -1;
3169 2c6ab832 bellard
    cirrus_update_bank_ptr(s, 0);
3170 2c6ab832 bellard
    cirrus_update_bank_ptr(s, 1);
3171 2c6ab832 bellard
    return 0;
3172 2c6ab832 bellard
}
3173 2c6ab832 bellard
3174 e36f36e1 bellard
/***************************************
3175 e36f36e1 bellard
 *
3176 e6e5ad80 bellard
 *  initialize
3177 e6e5ad80 bellard
 *
3178 e6e5ad80 bellard
 ***************************************/
3179 e6e5ad80 bellard
3180 4abc796d blueswir1
static void cirrus_reset(void *opaque)
3181 e6e5ad80 bellard
{
3182 4abc796d blueswir1
    CirrusVGAState *s = opaque;
3183 e6e5ad80 bellard
3184 4abc796d blueswir1
    vga_reset(s);
3185 e6e5ad80 bellard
    s->sr[0x06] = 0x0f;
3186 4abc796d blueswir1
    if (s->device_id == CIRRUS_ID_CLGD5446) {
3187 78e127ef bellard
        /* 4MB 64 bit memory config, always PCI */
3188 b30d4608 bellard
        s->sr[0x1F] = 0x2d;                // MemClock
3189 b30d4608 bellard
        s->gr[0x18] = 0x0f;             // fastest memory configuration
3190 78e127ef bellard
#if 1
3191 78e127ef bellard
        s->sr[0x0f] = 0x98;
3192 78e127ef bellard
        s->sr[0x17] = 0x20;
3193 78e127ef bellard
        s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3194 78e127ef bellard
        s->real_vram_size = 4096 * 1024;
3195 78e127ef bellard
#else
3196 78e127ef bellard
        s->sr[0x0f] = 0x18;
3197 78e127ef bellard
        s->sr[0x17] = 0x20;
3198 78e127ef bellard
        s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3199 78e127ef bellard
        s->real_vram_size = 2048 * 1024;
3200 78e127ef bellard
#endif
3201 78e127ef bellard
    } else {
3202 b30d4608 bellard
        s->sr[0x1F] = 0x22;                // MemClock
3203 78e127ef bellard
        s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3204 4abc796d blueswir1
        s->sr[0x17] = s->bustype;
3205 78e127ef bellard
        s->real_vram_size = 2048 * 1024;
3206 78e127ef bellard
        s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3207 78e127ef bellard
    }
3208 4abc796d blueswir1
    s->cr[0x27] = s->device_id;
3209 e6e5ad80 bellard
3210 78e127ef bellard
    /* Win2K seems to assume that the pattern buffer is at 0xff
3211 78e127ef bellard
       initially ! */
3212 78e127ef bellard
    memset(s->vram_ptr, 0xff, s->real_vram_size);
3213 78e127ef bellard
3214 e6e5ad80 bellard
    s->cirrus_hidden_dac_lockindex = 5;
3215 e6e5ad80 bellard
    s->cirrus_hidden_dac_data = 0;
3216 e6e5ad80 bellard
3217 e6e5ad80 bellard
    /* I/O handler for LFB */
3218 e6e5ad80 bellard
    s->cirrus_linear_io_addr =
3219 e6e5ad80 bellard
        cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3220 e6e5ad80 bellard
                               s);
3221 8926b517 bellard
    s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3222 8926b517 bellard
3223 a5082316 bellard
    /* I/O handler for LFB */
3224 a5082316 bellard
    s->cirrus_linear_bitblt_io_addr =
3225 a5082316 bellard
        cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3226 a5082316 bellard
                               s);
3227 a5082316 bellard
3228 e6e5ad80 bellard
    /* I/O handler for memory-mapped I/O */
3229 e6e5ad80 bellard
    s->cirrus_mmio_io_addr =
3230 e6e5ad80 bellard
        cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3231 e6e5ad80 bellard
3232 e6e5ad80 bellard
    /* XXX: s->vram_size must be a power of two */
3233 78e127ef bellard
    s->cirrus_addr_mask = s->real_vram_size - 1;
3234 78e127ef bellard
    s->linear_mmio_mask = s->real_vram_size - 256;
3235 e6e5ad80 bellard
3236 e6e5ad80 bellard
    s->get_bpp = cirrus_get_bpp;
3237 e6e5ad80 bellard
    s->get_offsets = cirrus_get_offsets;
3238 78e127ef bellard
    s->get_resolution = cirrus_get_resolution;
3239 a5082316 bellard
    s->cursor_invalidate = cirrus_cursor_invalidate;
3240 a5082316 bellard
    s->cursor_draw_line = cirrus_cursor_draw_line;
3241 4abc796d blueswir1
}
3242 4abc796d blueswir1
3243 4abc796d blueswir1
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3244 4abc796d blueswir1
{
3245 4abc796d blueswir1
    int i;
3246 4abc796d blueswir1
    static int inited;
3247 4abc796d blueswir1
3248 4abc796d blueswir1
    if (!inited) {
3249 4abc796d blueswir1
        inited = 1;
3250 4abc796d blueswir1
        for(i = 0;i < 256; i++)
3251 4abc796d blueswir1
            rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3252 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_0] = 0;
3253 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3254 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOP] = 2;
3255 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3256 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3257 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC] = 5;
3258 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_1] = 6;
3259 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3260 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3261 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3262 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3263 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3264 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3265 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3266 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3267 4abc796d blueswir1
        rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3268 4abc796d blueswir1
        s->device_id = device_id;
3269 4abc796d blueswir1
        if (is_pci)
3270 4abc796d blueswir1
            s->bustype = CIRRUS_BUSTYPE_PCI;
3271 4abc796d blueswir1
        else
3272 4abc796d blueswir1
            s->bustype = CIRRUS_BUSTYPE_ISA;
3273 4abc796d blueswir1
    }
3274 4abc796d blueswir1
3275 4abc796d blueswir1
    register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3276 4abc796d blueswir1
3277 4abc796d blueswir1
    register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3278 4abc796d blueswir1
    register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3279 4abc796d blueswir1
    register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3280 4abc796d blueswir1
    register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3281 4abc796d blueswir1
3282 4abc796d blueswir1
    register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3283 4abc796d blueswir1
3284 4abc796d blueswir1
    register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3285 4abc796d blueswir1
    register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3286 4abc796d blueswir1
    register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3287 4abc796d blueswir1
    register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3288 4abc796d blueswir1
3289 4abc796d blueswir1
    s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3290 4abc796d blueswir1
                                           cirrus_vga_mem_write, s);
3291 4abc796d blueswir1
    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3292 4abc796d blueswir1
                                 s->vga_io_memory);
3293 4abc796d blueswir1
    qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3294 2c6ab832 bellard
3295 4abc796d blueswir1
    qemu_register_reset(cirrus_reset, s);
3296 4abc796d blueswir1
    cirrus_reset(s);
3297 d2269f6f bellard
    register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3298 e6e5ad80 bellard
}
3299 e6e5ad80 bellard
3300 e6e5ad80 bellard
/***************************************
3301 e6e5ad80 bellard
 *
3302 e6e5ad80 bellard
 *  ISA bus support
3303 e6e5ad80 bellard
 *
3304 e6e5ad80 bellard
 ***************************************/
3305 e6e5ad80 bellard
3306 5fafdf24 ths
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3307 4efe2755 aliguori
                         ram_addr_t vga_ram_offset, int vga_ram_size)
3308 e6e5ad80 bellard
{
3309 e6e5ad80 bellard
    CirrusVGAState *s;
3310 e6e5ad80 bellard
3311 e6e5ad80 bellard
    s = qemu_mallocz(sizeof(CirrusVGAState));
3312 3b46e624 ths
3313 5fafdf24 ths
    vga_common_init((VGAState *)s,
3314 e6e5ad80 bellard
                    ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3315 78e127ef bellard
    cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3316 d5529471 aurel32
    s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3317 d5529471 aurel32
                                      s->screen_dump, s->text_update, s);
3318 e6e5ad80 bellard
    /* XXX ISA-LFB support */
3319 e6e5ad80 bellard
}
3320 e6e5ad80 bellard
3321 e6e5ad80 bellard
/***************************************
3322 e6e5ad80 bellard
 *
3323 e6e5ad80 bellard
 *  PCI bus support
3324 e6e5ad80 bellard
 *
3325 e6e5ad80 bellard
 ***************************************/
3326 e6e5ad80 bellard
3327 e6e5ad80 bellard
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3328 e6e5ad80 bellard
                               uint32_t addr, uint32_t size, int type)
3329 e6e5ad80 bellard
{
3330 e6e5ad80 bellard
    CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3331 e6e5ad80 bellard
3332 a5082316 bellard
    /* XXX: add byte swapping apertures */
3333 e6e5ad80 bellard
    cpu_register_physical_memory(addr, s->vram_size,
3334 e6e5ad80 bellard
                                 s->cirrus_linear_io_addr);
3335 a5082316 bellard
    cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3336 a5082316 bellard
                                 s->cirrus_linear_bitblt_io_addr);
3337 2bec46dc aliguori
3338 2bec46dc aliguori
    s->map_addr = s->map_end = 0;
3339 2bec46dc aliguori
    s->lfb_addr = addr & TARGET_PAGE_MASK;
3340 2bec46dc aliguori
    s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3341 2bec46dc aliguori
    /* account for overflow */
3342 2bec46dc aliguori
    if (s->lfb_end < addr + VGA_RAM_SIZE)
3343 2bec46dc aliguori
        s->lfb_end = addr + VGA_RAM_SIZE;
3344 e6e5ad80 bellard
}
3345 e6e5ad80 bellard
3346 e6e5ad80 bellard
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3347 e6e5ad80 bellard
                                uint32_t addr, uint32_t size, int type)
3348 e6e5ad80 bellard
{
3349 e6e5ad80 bellard
    CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3350 e6e5ad80 bellard
3351 e6e5ad80 bellard
    cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3352 e6e5ad80 bellard
                                 s->cirrus_mmio_io_addr);
3353 e6e5ad80 bellard
}
3354 e6e5ad80 bellard
3355 5fafdf24 ths
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3356 4efe2755 aliguori
                         ram_addr_t vga_ram_offset, int vga_ram_size)
3357 e6e5ad80 bellard
{
3358 e6e5ad80 bellard
    PCICirrusVGAState *d;
3359 e6e5ad80 bellard
    uint8_t *pci_conf;
3360 e6e5ad80 bellard
    CirrusVGAState *s;
3361 20ba3ae1 bellard
    int device_id;
3362 3b46e624 ths
3363 20ba3ae1 bellard
    device_id = CIRRUS_ID_CLGD5446;
3364 e6e5ad80 bellard
3365 e6e5ad80 bellard
    /* setup PCI configuration registers */
3366 5fafdf24 ths
    d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3367 5fafdf24 ths
                                                 sizeof(PCICirrusVGAState),
3368 46e50e9d bellard
                                                 -1, NULL, NULL);
3369 e6e5ad80 bellard
    pci_conf = d->dev.config;
3370 e6e5ad80 bellard
    pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3371 e6e5ad80 bellard
    pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3372 20ba3ae1 bellard
    pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3373 20ba3ae1 bellard
    pci_conf[0x03] = (uint8_t) (device_id >> 8);
3374 e6e5ad80 bellard
    pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3375 e6e5ad80 bellard
    pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3376 e6e5ad80 bellard
    pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3377 e6e5ad80 bellard
    pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3378 e6e5ad80 bellard
3379 e6e5ad80 bellard
    /* setup VGA */
3380 e6e5ad80 bellard
    s = &d->cirrus_vga;
3381 5fafdf24 ths
    vga_common_init((VGAState *)s,
3382 e6e5ad80 bellard
                    ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3383 78e127ef bellard
    cirrus_init_common(s, device_id, 1);
3384 d34cab9f ths
3385 c60e08d9 pbrook
    s->console = graphic_console_init(s->ds, s->update, s->invalidate,
3386 c60e08d9 pbrook
                                      s->screen_dump, s->text_update, s);
3387 d34cab9f ths
3388 d2269f6f bellard
    s->pci_dev = (PCIDevice *)d;
3389 e6e5ad80 bellard
3390 e6e5ad80 bellard
    /* setup memory space */
3391 e6e5ad80 bellard
    /* memory #0 LFB */
3392 e6e5ad80 bellard
    /* memory #1 memory-mapped I/O */
3393 e6e5ad80 bellard
    /* XXX: s->vram_size must be a power of two */
3394 a5082316 bellard
    pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3395 a21ae81d bellard
                           PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3396 20ba3ae1 bellard
    if (device_id == CIRRUS_ID_CLGD5446) {
3397 a21ae81d bellard
        pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3398 a21ae81d bellard
                               PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3399 a21ae81d bellard
    }
3400 e6e5ad80 bellard
    /* XXX: ROM BIOS */
3401 e6e5ad80 bellard
}