Revision 10ee2aaa hw/ac97.c
b/hw/ac97.c | ||
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147 | 147 |
} AC97BusMasterRegs; |
148 | 148 |
|
149 | 149 |
typedef struct AC97LinkState { |
150 |
PCIDevice *pci_dev;
|
|
150 |
PCIDevice dev; |
|
151 | 151 |
QEMUSoundCard card; |
152 | 152 |
uint32_t glob_cnt; |
153 | 153 |
uint32_t glob_sta; |
... | ... | |
175 | 175 |
#define dolog(...) |
176 | 176 |
#endif |
177 | 177 |
|
178 |
typedef struct PCIAC97LinkState { |
|
179 |
PCIDevice dev; |
|
180 |
AC97LinkState ac97; |
|
181 |
} PCIAC97LinkState; |
|
182 |
|
|
183 | 178 |
#define MKREGS(prefix, start) \ |
184 | 179 |
enum { \ |
185 | 180 |
prefix ## _BDBAR = start, \ |
... | ... | |
278 | 273 |
if (level) { |
279 | 274 |
s->glob_sta |= masks[r - s->bm_regs]; |
280 | 275 |
dolog ("set irq level=1\n"); |
281 |
qemu_set_irq (s->pci_dev->irq[0], 1);
|
|
276 |
qemu_set_irq (s->dev.irq[0], 1);
|
|
282 | 277 |
} |
283 | 278 |
else { |
284 | 279 |
s->glob_sta &= ~masks[r - s->bm_regs]; |
285 | 280 |
dolog ("set irq level=0\n"); |
286 |
qemu_set_irq (s->pci_dev->irq[0], 0);
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|
281 |
qemu_set_irq (s->dev.irq[0], 0);
|
|
287 | 282 |
} |
288 | 283 |
} |
289 | 284 |
|
... | ... | |
578 | 573 |
*/ |
579 | 574 |
static uint32_t nam_readb (void *opaque, uint32_t addr) |
580 | 575 |
{ |
581 |
PCIAC97LinkState *d = opaque; |
|
582 |
AC97LinkState *s = &d->ac97; |
|
576 |
AC97LinkState *s = opaque; |
|
583 | 577 |
dolog ("U nam readb %#x\n", addr); |
584 | 578 |
s->cas = 0; |
585 | 579 |
return ~0U; |
... | ... | |
587 | 581 |
|
588 | 582 |
static uint32_t nam_readw (void *opaque, uint32_t addr) |
589 | 583 |
{ |
590 |
PCIAC97LinkState *d = opaque; |
|
591 |
AC97LinkState *s = &d->ac97; |
|
584 |
AC97LinkState *s = opaque; |
|
592 | 585 |
uint32_t val = ~0U; |
593 | 586 |
uint32_t index = addr - s->base[0]; |
594 | 587 |
s->cas = 0; |
... | ... | |
598 | 591 |
|
599 | 592 |
static uint32_t nam_readl (void *opaque, uint32_t addr) |
600 | 593 |
{ |
601 |
PCIAC97LinkState *d = opaque; |
|
602 |
AC97LinkState *s = &d->ac97; |
|
594 |
AC97LinkState *s = opaque; |
|
603 | 595 |
dolog ("U nam readl %#x\n", addr); |
604 | 596 |
s->cas = 0; |
605 | 597 |
return ~0U; |
... | ... | |
611 | 603 |
*/ |
612 | 604 |
static void nam_writeb (void *opaque, uint32_t addr, uint32_t val) |
613 | 605 |
{ |
614 |
PCIAC97LinkState *d = opaque; |
|
615 |
AC97LinkState *s = &d->ac97; |
|
606 |
AC97LinkState *s = opaque; |
|
616 | 607 |
dolog ("U nam writeb %#x <- %#x\n", addr, val); |
617 | 608 |
s->cas = 0; |
618 | 609 |
} |
619 | 610 |
|
620 | 611 |
static void nam_writew (void *opaque, uint32_t addr, uint32_t val) |
621 | 612 |
{ |
622 |
PCIAC97LinkState *d = opaque; |
|
623 |
AC97LinkState *s = &d->ac97; |
|
613 |
AC97LinkState *s = opaque; |
|
624 | 614 |
uint32_t index = addr - s->base[0]; |
625 | 615 |
s->cas = 0; |
626 | 616 |
switch (index) { |
... | ... | |
711 | 701 |
|
712 | 702 |
static void nam_writel (void *opaque, uint32_t addr, uint32_t val) |
713 | 703 |
{ |
714 |
PCIAC97LinkState *d = opaque; |
|
715 |
AC97LinkState *s = &d->ac97; |
|
704 |
AC97LinkState *s = opaque; |
|
716 | 705 |
dolog ("U nam writel %#x <- %#x\n", addr, val); |
717 | 706 |
s->cas = 0; |
718 | 707 |
} |
... | ... | |
723 | 712 |
*/ |
724 | 713 |
static uint32_t nabm_readb (void *opaque, uint32_t addr) |
725 | 714 |
{ |
726 |
PCIAC97LinkState *d = opaque; |
|
727 |
AC97LinkState *s = &d->ac97; |
|
715 |
AC97LinkState *s = opaque; |
|
728 | 716 |
AC97BusMasterRegs *r = NULL; |
729 | 717 |
uint32_t index = addr - s->base[1]; |
730 | 718 |
uint32_t val = ~0U; |
... | ... | |
779 | 767 |
|
780 | 768 |
static uint32_t nabm_readw (void *opaque, uint32_t addr) |
781 | 769 |
{ |
782 |
PCIAC97LinkState *d = opaque; |
|
783 |
AC97LinkState *s = &d->ac97; |
|
770 |
AC97LinkState *s = opaque; |
|
784 | 771 |
AC97BusMasterRegs *r = NULL; |
785 | 772 |
uint32_t index = addr - s->base[1]; |
786 | 773 |
uint32_t val = ~0U; |
... | ... | |
809 | 796 |
|
810 | 797 |
static uint32_t nabm_readl (void *opaque, uint32_t addr) |
811 | 798 |
{ |
812 |
PCIAC97LinkState *d = opaque; |
|
813 |
AC97LinkState *s = &d->ac97; |
|
799 |
AC97LinkState *s = opaque; |
|
814 | 800 |
AC97BusMasterRegs *r = NULL; |
815 | 801 |
uint32_t index = addr - s->base[1]; |
816 | 802 |
uint32_t val = ~0U; |
... | ... | |
860 | 846 |
*/ |
861 | 847 |
static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) |
862 | 848 |
{ |
863 |
PCIAC97LinkState *d = opaque; |
|
864 |
AC97LinkState *s = &d->ac97; |
|
849 |
AC97LinkState *s = opaque; |
|
865 | 850 |
AC97BusMasterRegs *r = NULL; |
866 | 851 |
uint32_t index = addr - s->base[1]; |
867 | 852 |
switch (index) { |
... | ... | |
917 | 902 |
|
918 | 903 |
static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) |
919 | 904 |
{ |
920 |
PCIAC97LinkState *d = opaque; |
|
921 |
AC97LinkState *s = &d->ac97; |
|
905 |
AC97LinkState *s = opaque; |
|
922 | 906 |
AC97BusMasterRegs *r = NULL; |
923 | 907 |
uint32_t index = addr - s->base[1]; |
924 | 908 |
switch (index) { |
... | ... | |
938 | 922 |
|
939 | 923 |
static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) |
940 | 924 |
{ |
941 |
PCIAC97LinkState *d = opaque; |
|
942 |
AC97LinkState *s = &d->ac97; |
|
925 |
AC97LinkState *s = opaque; |
|
943 | 926 |
AC97BusMasterRegs *r = NULL; |
944 | 927 |
uint32_t index = addr - s->base[1]; |
945 | 928 |
switch (index) { |
... | ... | |
1190 | 1173 |
uint8_t active[LAST_INDEX]; |
1191 | 1174 |
AC97LinkState *s = opaque; |
1192 | 1175 |
|
1193 |
pci_device_save (s->pci_dev, f);
|
|
1176 |
pci_device_save (&s->dev, f);
|
|
1194 | 1177 |
|
1195 | 1178 |
qemu_put_be32s (f, &s->glob_cnt); |
1196 | 1179 |
qemu_put_be32s (f, &s->glob_sta); |
... | ... | |
1227 | 1210 |
if (version_id != 2) |
1228 | 1211 |
return -EINVAL; |
1229 | 1212 |
|
1230 |
ret = pci_device_load (s->pci_dev, f);
|
|
1213 |
ret = pci_device_load (&s->dev, f);
|
|
1231 | 1214 |
if (ret) |
1232 | 1215 |
return ret; |
1233 | 1216 |
|
... | ... | |
1269 | 1252 |
static void ac97_map (PCIDevice *pci_dev, int region_num, |
1270 | 1253 |
uint32_t addr, uint32_t size, int type) |
1271 | 1254 |
{ |
1272 |
PCIAC97LinkState *d = (PCIAC97LinkState *) pci_dev;
|
|
1273 |
AC97LinkState *s = &d->ac97;
|
|
1255 |
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
|
|
1256 |
PCIDevice *d = &s->dev;
|
|
1274 | 1257 |
|
1275 | 1258 |
if (!region_num) { |
1276 | 1259 |
s->base[0] = addr; |
... | ... | |
1310 | 1293 |
|
1311 | 1294 |
static void ac97_initfn (PCIDevice *dev) |
1312 | 1295 |
{ |
1313 |
PCIAC97LinkState *d = DO_UPCAST (PCIAC97LinkState, dev, dev); |
|
1314 |
AC97LinkState *s = &d->ac97; |
|
1315 |
uint8_t *c = d->dev.config; |
|
1296 |
AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev); |
|
1297 |
uint8_t *c = s->dev.config; |
|
1316 | 1298 |
|
1317 |
s->pci_dev = &d->dev; |
|
1318 | 1299 |
pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */ |
1319 | 1300 |
pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */ |
1320 | 1301 |
|
... | ... | |
1350 | 1331 |
c[0x3c] = 0x00; /* intr_ln interrupt line rw */ |
1351 | 1332 |
c[0x3d] = 0x01; /* intr_pn interrupt pin ro */ |
1352 | 1333 |
|
1353 |
pci_register_bar (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
|
|
1354 |
pci_register_bar (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
|
|
1334 |
pci_register_bar (&s->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
|
|
1335 |
pci_register_bar (&s->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
|
|
1355 | 1336 |
register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s); |
1356 | 1337 |
qemu_register_reset (ac97_on_reset, s); |
1357 | 1338 |
AUD_register_card ("ac97", &s->card); |
... | ... | |
1367 | 1348 |
static PCIDeviceInfo ac97_info = { |
1368 | 1349 |
.qdev.name = "AC97", |
1369 | 1350 |
.qdev.desc = "Intel 82801AA AC97 Audio", |
1370 |
.qdev.size = sizeof (PCIAC97LinkState),
|
|
1351 |
.qdev.size = sizeof (AC97LinkState), |
|
1371 | 1352 |
.init = ac97_initfn, |
1372 | 1353 |
}; |
1373 | 1354 |
|
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