root / hw / axis_dev88.c @ 11d6dded
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1 | 10c144e2 | edgar_igl | /*
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2 | 10c144e2 | edgar_igl | * QEMU model for the AXIS devboard 88.
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3 | 10c144e2 | edgar_igl | *
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4 | 10c144e2 | edgar_igl | * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
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5 | 10c144e2 | edgar_igl | *
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6 | 10c144e2 | edgar_igl | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 10c144e2 | edgar_igl | * of this software and associated documentation files (the "Software"), to deal
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8 | 10c144e2 | edgar_igl | * in the Software without restriction, including without limitation the rights
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9 | 10c144e2 | edgar_igl | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 10c144e2 | edgar_igl | * copies of the Software, and to permit persons to whom the Software is
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11 | 10c144e2 | edgar_igl | * furnished to do so, subject to the following conditions:
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12 | 10c144e2 | edgar_igl | *
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13 | 10c144e2 | edgar_igl | * The above copyright notice and this permission notice shall be included in
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14 | 10c144e2 | edgar_igl | * all copies or substantial portions of the Software.
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15 | 10c144e2 | edgar_igl | *
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16 | 10c144e2 | edgar_igl | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 10c144e2 | edgar_igl | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 10c144e2 | edgar_igl | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 10c144e2 | edgar_igl | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 10c144e2 | edgar_igl | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 10c144e2 | edgar_igl | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 10c144e2 | edgar_igl | * THE SOFTWARE.
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23 | 10c144e2 | edgar_igl | */
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24 | 4b816985 | Edgar E. Iglesias | |
25 | 4b816985 | Edgar E. Iglesias | #include "sysbus.h" |
26 | 10c144e2 | edgar_igl | #include "net.h" |
27 | 10c144e2 | edgar_igl | #include "flash.h" |
28 | 10c144e2 | edgar_igl | #include "boards.h" |
29 | 10c144e2 | edgar_igl | #include "etraxfs.h" |
30 | ca20cf32 | Blue Swirl | #include "loader.h" |
31 | ca20cf32 | Blue Swirl | #include "elf.h" |
32 | 77d4f95e | Edgar E. Iglesias | #include "cris-boot.h" |
33 | 522f253c | Peter Maydell | #include "blockdev.h" |
34 | 10c144e2 | edgar_igl | |
35 | 10c144e2 | edgar_igl | #define D(x)
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36 | 10c144e2 | edgar_igl | #define DNAND(x)
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37 | 10c144e2 | edgar_igl | |
38 | 10c144e2 | edgar_igl | struct nand_state_t
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39 | 10c144e2 | edgar_igl | { |
40 | d4220389 | Juha Riihimäki | DeviceState *nand; |
41 | 10c144e2 | edgar_igl | unsigned int rdy:1; |
42 | 10c144e2 | edgar_igl | unsigned int ale:1; |
43 | 10c144e2 | edgar_igl | unsigned int cle:1; |
44 | 10c144e2 | edgar_igl | unsigned int ce:1; |
45 | 10c144e2 | edgar_igl | }; |
46 | 10c144e2 | edgar_igl | |
47 | 10c144e2 | edgar_igl | static struct nand_state_t nand_state; |
48 | c227f099 | Anthony Liguori | static uint32_t nand_readl (void *opaque, target_phys_addr_t addr) |
49 | 10c144e2 | edgar_igl | { |
50 | 10c144e2 | edgar_igl | struct nand_state_t *s = opaque;
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51 | 10c144e2 | edgar_igl | uint32_t r; |
52 | 10c144e2 | edgar_igl | int rdy;
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53 | 10c144e2 | edgar_igl | |
54 | 10c144e2 | edgar_igl | r = nand_getio(s->nand); |
55 | 10c144e2 | edgar_igl | nand_getpins(s->nand, &rdy); |
56 | 10c144e2 | edgar_igl | s->rdy = rdy; |
57 | 10c144e2 | edgar_igl | |
58 | 10c144e2 | edgar_igl | DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
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59 | 10c144e2 | edgar_igl | return r;
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60 | 10c144e2 | edgar_igl | } |
61 | 10c144e2 | edgar_igl | |
62 | 10c144e2 | edgar_igl | static void |
63 | c227f099 | Anthony Liguori | nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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64 | 10c144e2 | edgar_igl | { |
65 | 10c144e2 | edgar_igl | struct nand_state_t *s = opaque;
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66 | 10c144e2 | edgar_igl | int rdy;
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67 | 10c144e2 | edgar_igl | |
68 | 10c144e2 | edgar_igl | DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
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69 | 10c144e2 | edgar_igl | nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0); |
70 | 10c144e2 | edgar_igl | nand_setio(s->nand, value); |
71 | 10c144e2 | edgar_igl | nand_getpins(s->nand, &rdy); |
72 | 10c144e2 | edgar_igl | s->rdy = rdy; |
73 | 10c144e2 | edgar_igl | } |
74 | 10c144e2 | edgar_igl | |
75 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const nand_read[] = { |
76 | 10c144e2 | edgar_igl | &nand_readl, |
77 | 10c144e2 | edgar_igl | &nand_readl, |
78 | 10c144e2 | edgar_igl | &nand_readl, |
79 | 10c144e2 | edgar_igl | }; |
80 | 10c144e2 | edgar_igl | |
81 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const nand_write[] = { |
82 | 10c144e2 | edgar_igl | &nand_writel, |
83 | 10c144e2 | edgar_igl | &nand_writel, |
84 | 10c144e2 | edgar_igl | &nand_writel, |
85 | 10c144e2 | edgar_igl | }; |
86 | 10c144e2 | edgar_igl | |
87 | 4a1e6bea | edgar_igl | |
88 | 4a1e6bea | edgar_igl | struct tempsensor_t
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89 | 4a1e6bea | edgar_igl | { |
90 | 4a1e6bea | edgar_igl | unsigned int shiftreg; |
91 | 4a1e6bea | edgar_igl | unsigned int count; |
92 | 4a1e6bea | edgar_igl | enum {
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93 | 4a1e6bea | edgar_igl | ST_OUT, ST_IN, ST_Z |
94 | 4a1e6bea | edgar_igl | } state; |
95 | 4a1e6bea | edgar_igl | |
96 | 4a1e6bea | edgar_igl | uint16_t regs[3];
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97 | 4a1e6bea | edgar_igl | }; |
98 | 4a1e6bea | edgar_igl | |
99 | 4a1e6bea | edgar_igl | static void tempsensor_clkedge(struct tempsensor_t *s, |
100 | 4a1e6bea | edgar_igl | unsigned int clk, unsigned int data_in) |
101 | 4a1e6bea | edgar_igl | { |
102 | 4a1e6bea | edgar_igl | D(printf("%s clk=%d state=%d sr=%x\n", __func__,
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103 | 4a1e6bea | edgar_igl | clk, s->state, s->shiftreg)); |
104 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
105 | 4a1e6bea | edgar_igl | s->count = 16;
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106 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
107 | 4a1e6bea | edgar_igl | } |
108 | 4a1e6bea | edgar_igl | switch (s->state) {
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109 | 4a1e6bea | edgar_igl | case ST_OUT:
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110 | 4a1e6bea | edgar_igl | /* Output reg is clocked at negedge. */
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111 | 4a1e6bea | edgar_igl | if (!clk) {
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112 | 4a1e6bea | edgar_igl | s->count--; |
113 | 4a1e6bea | edgar_igl | s->shiftreg <<= 1;
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114 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
115 | 4a1e6bea | edgar_igl | s->shiftreg = 0;
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116 | 4a1e6bea | edgar_igl | s->state = ST_IN; |
117 | 4a1e6bea | edgar_igl | s->count = 16;
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118 | 4a1e6bea | edgar_igl | } |
119 | 4a1e6bea | edgar_igl | } |
120 | 4a1e6bea | edgar_igl | break;
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121 | 4a1e6bea | edgar_igl | case ST_Z:
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122 | 4a1e6bea | edgar_igl | if (clk) {
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123 | 4a1e6bea | edgar_igl | s->count--; |
124 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
125 | 4a1e6bea | edgar_igl | s->shiftreg = 0;
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126 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
127 | 4a1e6bea | edgar_igl | s->count = 16;
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128 | 4a1e6bea | edgar_igl | } |
129 | 4a1e6bea | edgar_igl | } |
130 | 4a1e6bea | edgar_igl | break;
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131 | 4a1e6bea | edgar_igl | case ST_IN:
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132 | 4a1e6bea | edgar_igl | /* Indata is sampled at posedge. */
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133 | 4a1e6bea | edgar_igl | if (clk) {
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134 | 4a1e6bea | edgar_igl | s->count--; |
135 | 4a1e6bea | edgar_igl | s->shiftreg <<= 1;
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136 | 4a1e6bea | edgar_igl | s->shiftreg |= data_in & 1;
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137 | 4a1e6bea | edgar_igl | if (s->count == 0) { |
138 | 4a1e6bea | edgar_igl | D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
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139 | 4a1e6bea | edgar_igl | s->regs[0] = s->shiftreg;
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140 | 4a1e6bea | edgar_igl | s->state = ST_OUT; |
141 | 4a1e6bea | edgar_igl | s->count = 16;
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142 | 4a1e6bea | edgar_igl | |
143 | 4a1e6bea | edgar_igl | if ((s->regs[0] & 0xff) == 0) { |
144 | 4a1e6bea | edgar_igl | /* 25 degrees celcius. */
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145 | 4a1e6bea | edgar_igl | s->shiftreg = 0x0b9f;
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146 | 4a1e6bea | edgar_igl | } else if ((s->regs[0] & 0xff) == 0xff) { |
147 | 4a1e6bea | edgar_igl | /* Sensor ID, 0x8100 LM70. */
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148 | 4a1e6bea | edgar_igl | s->shiftreg = 0x8100;
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149 | 4a1e6bea | edgar_igl | } else
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150 | 4a1e6bea | edgar_igl | printf("Invalid tempsens state %x\n", s->regs[0]); |
151 | 4a1e6bea | edgar_igl | } |
152 | 4a1e6bea | edgar_igl | } |
153 | 4a1e6bea | edgar_igl | break;
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154 | 4a1e6bea | edgar_igl | } |
155 | 4a1e6bea | edgar_igl | } |
156 | 4a1e6bea | edgar_igl | |
157 | 4a1e6bea | edgar_igl | |
158 | 4a1e6bea | edgar_igl | #define RW_PA_DOUT 0x00 |
159 | 4a1e6bea | edgar_igl | #define R_PA_DIN 0x01 |
160 | 4a1e6bea | edgar_igl | #define RW_PA_OE 0x02 |
161 | 4a1e6bea | edgar_igl | #define RW_PD_DOUT 0x10 |
162 | 4a1e6bea | edgar_igl | #define R_PD_DIN 0x11 |
163 | 4a1e6bea | edgar_igl | #define RW_PD_OE 0x12 |
164 | 4a1e6bea | edgar_igl | |
165 | 4a1e6bea | edgar_igl | static struct gpio_state_t |
166 | 10c144e2 | edgar_igl | { |
167 | 10c144e2 | edgar_igl | struct nand_state_t *nand;
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168 | 4a1e6bea | edgar_igl | struct tempsensor_t tempsensor;
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169 | 10c144e2 | edgar_igl | uint32_t regs[0x5c / 4]; |
170 | 10c144e2 | edgar_igl | } gpio_state; |
171 | 10c144e2 | edgar_igl | |
172 | c227f099 | Anthony Liguori | static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) |
173 | 10c144e2 | edgar_igl | { |
174 | 10c144e2 | edgar_igl | struct gpio_state_t *s = opaque;
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175 | 10c144e2 | edgar_igl | uint32_t r = 0;
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176 | 10c144e2 | edgar_igl | |
177 | 10c144e2 | edgar_igl | addr >>= 2;
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178 | 10c144e2 | edgar_igl | switch (addr)
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179 | 10c144e2 | edgar_igl | { |
180 | 10c144e2 | edgar_igl | case R_PA_DIN:
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181 | 10c144e2 | edgar_igl | r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE]; |
182 | 10c144e2 | edgar_igl | |
183 | 10c144e2 | edgar_igl | /* Encode pins from the nand. */
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184 | 10c144e2 | edgar_igl | r |= s->nand->rdy << 7;
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185 | 10c144e2 | edgar_igl | break;
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186 | 4a1e6bea | edgar_igl | case R_PD_DIN:
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187 | 4a1e6bea | edgar_igl | r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE]; |
188 | 4a1e6bea | edgar_igl | |
189 | 4a1e6bea | edgar_igl | /* Encode temp sensor pins. */
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190 | 4a1e6bea | edgar_igl | r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4; |
191 | 4a1e6bea | edgar_igl | break;
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192 | 4a1e6bea | edgar_igl | |
193 | 10c144e2 | edgar_igl | default:
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194 | 10c144e2 | edgar_igl | r = s->regs[addr]; |
195 | 10c144e2 | edgar_igl | break;
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196 | 10c144e2 | edgar_igl | } |
197 | 10c144e2 | edgar_igl | return r;
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198 | 10c144e2 | edgar_igl | D(printf("%s %x=%x\n", __func__, addr, r));
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199 | 10c144e2 | edgar_igl | } |
200 | 10c144e2 | edgar_igl | |
201 | c227f099 | Anthony Liguori | static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
202 | 10c144e2 | edgar_igl | { |
203 | 10c144e2 | edgar_igl | struct gpio_state_t *s = opaque;
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204 | 10c144e2 | edgar_igl | D(printf("%s %x=%x\n", __func__, addr, value));
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205 | 10c144e2 | edgar_igl | |
206 | 10c144e2 | edgar_igl | addr >>= 2;
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207 | 10c144e2 | edgar_igl | switch (addr)
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208 | 10c144e2 | edgar_igl | { |
209 | 10c144e2 | edgar_igl | case RW_PA_DOUT:
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210 | 10c144e2 | edgar_igl | /* Decode nand pins. */
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211 | 10c144e2 | edgar_igl | s->nand->ale = !!(value & (1 << 6)); |
212 | 10c144e2 | edgar_igl | s->nand->cle = !!(value & (1 << 5)); |
213 | 10c144e2 | edgar_igl | s->nand->ce = !!(value & (1 << 4)); |
214 | 10c144e2 | edgar_igl | |
215 | 10c144e2 | edgar_igl | s->regs[addr] = value; |
216 | 10c144e2 | edgar_igl | break;
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217 | 4a1e6bea | edgar_igl | |
218 | 4a1e6bea | edgar_igl | case RW_PD_DOUT:
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219 | 4a1e6bea | edgar_igl | /* Temp sensor clk. */
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220 | 4a1e6bea | edgar_igl | if ((s->regs[addr] ^ value) & 2) |
221 | 4a1e6bea | edgar_igl | tempsensor_clkedge(&s->tempsensor, !!(value & 2),
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222 | 4a1e6bea | edgar_igl | !!(value & 16));
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223 | 4a1e6bea | edgar_igl | s->regs[addr] = value; |
224 | 4a1e6bea | edgar_igl | break;
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225 | 4a1e6bea | edgar_igl | |
226 | 10c144e2 | edgar_igl | default:
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227 | 10c144e2 | edgar_igl | s->regs[addr] = value; |
228 | 10c144e2 | edgar_igl | break;
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229 | 10c144e2 | edgar_igl | } |
230 | 10c144e2 | edgar_igl | } |
231 | 10c144e2 | edgar_igl | |
232 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const gpio_read[] = { |
233 | 10c144e2 | edgar_igl | NULL, NULL, |
234 | 10c144e2 | edgar_igl | &gpio_readl, |
235 | 10c144e2 | edgar_igl | }; |
236 | 10c144e2 | edgar_igl | |
237 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const gpio_write[] = { |
238 | 10c144e2 | edgar_igl | NULL, NULL, |
239 | 10c144e2 | edgar_igl | &gpio_writel, |
240 | 10c144e2 | edgar_igl | }; |
241 | 10c144e2 | edgar_igl | |
242 | 10c144e2 | edgar_igl | #define INTMEM_SIZE (128 * 1024) |
243 | 10c144e2 | edgar_igl | |
244 | 77d4f95e | Edgar E. Iglesias | static struct cris_load_info li; |
245 | 409dbce5 | Aurelien Jarno | |
246 | 10c144e2 | edgar_igl | static
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247 | c227f099 | Anthony Liguori | void axisdev88_init (ram_addr_t ram_size,
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248 | ef998233 | edgar_igl | const char *boot_device, |
249 | 10c144e2 | edgar_igl | const char *kernel_filename, const char *kernel_cmdline, |
250 | 10c144e2 | edgar_igl | const char *initrd_filename, const char *cpu_model) |
251 | 10c144e2 | edgar_igl | { |
252 | 10c144e2 | edgar_igl | CPUState *env; |
253 | fd6dc90b | Edgar E. Iglesias | DeviceState *dev; |
254 | fd6dc90b | Edgar E. Iglesias | SysBusDevice *s; |
255 | 522f253c | Peter Maydell | DriveInfo *nand; |
256 | fd6dc90b | Edgar E. Iglesias | qemu_irq irq[30], nmi[2], *cpu_irq; |
257 | 10c144e2 | edgar_igl | void *etraxfs_dmac;
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258 | 1da005b3 | Edgar E. Iglesias | struct etraxfs_dma_client *dma_eth;
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259 | 10c144e2 | edgar_igl | int i;
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260 | 10c144e2 | edgar_igl | int nand_regs;
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261 | 10c144e2 | edgar_igl | int gpio_regs;
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262 | 01e0451a | Anthony Liguori | ram_addr_t phys_ram; |
263 | 01e0451a | Anthony Liguori | ram_addr_t phys_intmem; |
264 | 10c144e2 | edgar_igl | |
265 | 10c144e2 | edgar_igl | /* init CPUs */
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266 | 10c144e2 | edgar_igl | if (cpu_model == NULL) { |
267 | 10c144e2 | edgar_igl | cpu_model = "crisv32";
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268 | 10c144e2 | edgar_igl | } |
269 | 10c144e2 | edgar_igl | env = cpu_init(cpu_model); |
270 | 10c144e2 | edgar_igl | |
271 | 10c144e2 | edgar_igl | /* allocate RAM */
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272 | 01e0451a | Anthony Liguori | phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size); |
273 | 01e0451a | Anthony Liguori | cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
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274 | 10c144e2 | edgar_igl | |
275 | 10c144e2 | edgar_igl | /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
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276 | 10c144e2 | edgar_igl | internal memory. */
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277 | 01e0451a | Anthony Liguori | phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE); |
278 | 01e0451a | Anthony Liguori | cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
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279 | 01e0451a | Anthony Liguori | phys_intmem | IO_MEM_RAM); |
280 | 01e0451a | Anthony Liguori | |
281 | 10c144e2 | edgar_igl | |
282 | 10c144e2 | edgar_igl | /* Attach a NAND flash to CS1. */
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283 | 522f253c | Peter Maydell | nand = drive_get(IF_MTD, 0, 0); |
284 | 522f253c | Peter Maydell | nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
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285 | 522f253c | Peter Maydell | NAND_MFR_STMICRO, 0x39);
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286 | 2507c12a | Alexander Graf | nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state, |
287 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
288 | 10c144e2 | edgar_igl | cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); |
289 | 10c144e2 | edgar_igl | |
290 | 10c144e2 | edgar_igl | gpio_state.nand = &nand_state; |
291 | 2507c12a | Alexander Graf | gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state, |
292 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
293 | 4a1e6bea | edgar_igl | cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); |
294 | 10c144e2 | edgar_igl | |
295 | 10c144e2 | edgar_igl | |
296 | fd6dc90b | Edgar E. Iglesias | cpu_irq = cris_pic_init_cpu(env); |
297 | fd6dc90b | Edgar E. Iglesias | dev = qdev_create(NULL, "etraxfs,pic"); |
298 | fd6dc90b | Edgar E. Iglesias | /* FIXME: Is there a proper way to signal vectors to the CPU core? */
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299 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
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300 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
301 | fd6dc90b | Edgar E. Iglesias | s = sysbus_from_qdev(dev); |
302 | fd6dc90b | Edgar E. Iglesias | sysbus_mmio_map(s, 0, 0x3001c000); |
303 | fd6dc90b | Edgar E. Iglesias | sysbus_connect_irq(s, 0, cpu_irq[0]); |
304 | fd6dc90b | Edgar E. Iglesias | sysbus_connect_irq(s, 1, cpu_irq[1]); |
305 | fd6dc90b | Edgar E. Iglesias | for (i = 0; i < 30; i++) { |
306 | 067a3ddc | Paul Brook | irq[i] = qdev_get_gpio_in(dev, i); |
307 | fd6dc90b | Edgar E. Iglesias | } |
308 | 067a3ddc | Paul Brook | nmi[0] = qdev_get_gpio_in(dev, 30); |
309 | 067a3ddc | Paul Brook | nmi[1] = qdev_get_gpio_in(dev, 31); |
310 | 73cfd29f | Edgar E. Iglesias | |
311 | ba494313 | Edgar E. Iglesias | etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10); |
312 | 10c144e2 | edgar_igl | for (i = 0; i < 10; i++) { |
313 | 10c144e2 | edgar_igl | /* On ETRAX, odd numbered channels are inputs. */
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314 | 73cfd29f | Edgar E. Iglesias | etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1); |
315 | 10c144e2 | edgar_igl | } |
316 | 10c144e2 | edgar_igl | |
317 | 10c144e2 | edgar_igl | /* Add the two ethernet blocks. */
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318 | 7267c094 | Anthony Liguori | dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */ |
319 | 1da005b3 | Edgar E. Iglesias | etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]); |
320 | 1da005b3 | Edgar E. Iglesias | if (nb_nics > 1) { |
321 | 1da005b3 | Edgar E. Iglesias | etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]); |
322 | 1da005b3 | Edgar E. Iglesias | } |
323 | 10c144e2 | edgar_igl | |
324 | 10c144e2 | edgar_igl | /* The DMA Connector block is missing, hardwire things for now. */
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325 | 1da005b3 | Edgar E. Iglesias | etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]); |
326 | 1da005b3 | Edgar E. Iglesias | etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]); |
327 | 1da005b3 | Edgar E. Iglesias | if (nb_nics > 1) { |
328 | 1da005b3 | Edgar E. Iglesias | etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]); |
329 | 1da005b3 | Edgar E. Iglesias | etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]); |
330 | 10c144e2 | edgar_igl | } |
331 | 10c144e2 | edgar_igl | |
332 | 10c144e2 | edgar_igl | /* 2 timers. */
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333 | 3b1fd90e | Edgar E. Iglesias | sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL); |
334 | 3b1fd90e | Edgar E. Iglesias | sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL); |
335 | 10c144e2 | edgar_igl | |
336 | 10c144e2 | edgar_igl | for (i = 0; i < 4; i++) { |
337 | 4b816985 | Edgar E. Iglesias | sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000, |
338 | 3b1fd90e | Edgar E. Iglesias | irq[0x14 + i]);
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339 | 10c144e2 | edgar_igl | } |
340 | 10c144e2 | edgar_igl | |
341 | 77d4f95e | Edgar E. Iglesias | if (!kernel_filename) {
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342 | 77d4f95e | Edgar E. Iglesias | fprintf(stderr, "Kernel image must be specified\n");
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343 | 77d4f95e | Edgar E. Iglesias | exit(1);
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344 | 10c144e2 | edgar_igl | } |
345 | 77d4f95e | Edgar E. Iglesias | |
346 | 77d4f95e | Edgar E. Iglesias | li.image_filename = kernel_filename; |
347 | 77d4f95e | Edgar E. Iglesias | li.cmdline = kernel_cmdline; |
348 | 77d4f95e | Edgar E. Iglesias | cris_load_image(env, &li); |
349 | 10c144e2 | edgar_igl | } |
350 | 10c144e2 | edgar_igl | |
351 | f80f9ec9 | Anthony Liguori | static QEMUMachine axisdev88_machine = {
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352 | 10c144e2 | edgar_igl | .name = "axis-dev88",
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353 | 10c144e2 | edgar_igl | .desc = "AXIS devboard 88",
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354 | 10c144e2 | edgar_igl | .init = axisdev88_init, |
355 | bbea04df | Edgar E. Iglesias | .is_default = 1,
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356 | 10c144e2 | edgar_igl | }; |
357 | f80f9ec9 | Anthony Liguori | |
358 | f80f9ec9 | Anthony Liguori | static void axisdev88_machine_init(void) |
359 | f80f9ec9 | Anthony Liguori | { |
360 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&axisdev88_machine); |
361 | f80f9ec9 | Anthony Liguori | } |
362 | f80f9ec9 | Anthony Liguori | |
363 | f80f9ec9 | Anthony Liguori | machine_init(axisdev88_machine_init); |