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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "monitor.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "loader.h" |
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#include "qemu-objects.h" |
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0) |
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#endif
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struct PCIBus {
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BusState qbus; |
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int devfn_min;
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pci_set_irq_fn set_irq; |
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pci_map_irq_fn map_irq; |
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pci_hotplug_fn hotplug; |
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DeviceState *hotplug_qdev; |
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void *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev; |
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target_phys_addr_t mem_base; |
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QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
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QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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}; |
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
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static struct BusInfo pci_bus_info = { |
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print, |
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.props = (Property[]) { |
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
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DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
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DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
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DEFINE_PROP_END_OF_LIST() |
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} |
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}; |
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
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static int pci_add_option_rom(PCIDevice *pdev); |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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struct PCIHostBus {
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int domain;
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struct PCIBus *bus;
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QLIST_ENTRY(PCIHostBus) next; |
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}; |
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static QLIST_HEAD(, PCIHostBus) host_buses;
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static const VMStateDescription vmstate_pcibus = { |
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_EQUAL(nirq, PCIBus), |
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VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int pci_bar(PCIDevice *d, int reg) |
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{ |
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uint8_t type; |
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4; |
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type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
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return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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} |
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static inline int pci_irq_state(PCIDevice *d, int irq_num) |
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{ |
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return (d->irq_state >> irq_num) & 0x1; |
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} |
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static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) |
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{ |
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d->irq_state &= ~(0x1 << irq_num);
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d->irq_state |= level << irq_num; |
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} |
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static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) |
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{ |
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PCIBus *bus; |
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for (;;) {
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bus = pci_dev->bus; |
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irq_num = bus->map_irq(pci_dev, irq_num); |
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if (bus->set_irq)
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break;
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pci_dev = bus->parent_dev; |
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} |
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bus->irq_count[irq_num] += change; |
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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} |
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/* Update interrupt status bit in config space on interrupt
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* state change. */
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static void pci_update_irq_status(PCIDevice *dev) |
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{ |
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if (dev->irq_state) {
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dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; |
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} else {
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dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
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} |
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} |
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static void pci_device_reset(PCIDevice *dev) |
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{ |
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int r;
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dev->irq_state = 0;
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pci_update_irq_status(dev); |
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dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
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PCI_COMMAND_MASTER); |
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
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if (!dev->io_regions[r].size) {
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continue;
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} |
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pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
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} |
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pci_update_mappings(dev); |
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} |
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static void pci_bus_reset(void *opaque) |
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{ |
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PCIBus *bus = opaque; |
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int i;
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
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if (bus->devices[i]) {
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pci_device_reset(bus->devices[i]); |
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} |
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} |
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} |
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static void pci_host_bus_register(int domain, PCIBus *bus) |
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{ |
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struct PCIHostBus *host;
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host = qemu_mallocz(sizeof(*host));
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host->domain = domain; |
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host->bus = bus; |
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QLIST_INSERT_HEAD(&host_buses, host, next); |
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} |
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PCIBus *pci_find_root_bus(int domain)
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{ |
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struct PCIHostBus *host;
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QLIST_FOREACH(host, &host_buses, next) { |
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if (host->domain == domain) {
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return host->bus;
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} |
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} |
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return NULL; |
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} |
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int pci_find_domain(const PCIBus *bus) |
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{ |
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PCIDevice *d; |
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struct PCIHostBus *host;
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/* obtain root bus */
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while ((d = bus->parent_dev) != NULL) { |
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bus = d->bus; |
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} |
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QLIST_FOREACH(host, &host_buses, next) { |
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if (host->bus == bus) {
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return host->domain;
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} |
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} |
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abort(); /* should not be reached */
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return -1; |
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} |
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, int devfn_min) |
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{ |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
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bus->devfn_min = devfn_min; |
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/* host bridge */
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QLIST_INIT(&bus->child); |
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pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ |
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vmstate_register(-1, &vmstate_pcibus, bus);
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qemu_register_reset(pci_bus_reset, bus); |
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} |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) |
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(*bus));
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bus->qbus.qdev_allocated = 1;
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pci_bus_new_inplace(bus, parent, name, devfn_min); |
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return bus;
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} |
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq) |
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{ |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = irq_opaque; |
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bus->nirq = nirq; |
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
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} |
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
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{ |
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bus->qbus.allow_hotplug = 1;
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bus->hotplug = hotplug; |
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bus->hotplug_qdev = qdev; |
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} |
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void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
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{ |
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bus->mem_base = base; |
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} |
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque, int devfn_min, int nirq) |
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{ |
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PCIBus *bus; |
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bus = pci_bus_new(parent, name, devfn_min); |
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pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
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return bus;
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} |
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static void pci_register_secondary_bus(PCIBus *parent, |
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PCIBus *bus, |
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PCIDevice *dev, |
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pci_map_irq_fn map_irq, |
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const char *name) |
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{ |
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qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
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bus->map_irq = map_irq; |
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bus->parent_dev = dev; |
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QLIST_INIT(&bus->child); |
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QLIST_INSERT_HEAD(&parent->child, bus, sibling); |
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} |
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static void pci_unregister_secondary_bus(PCIBus *bus) |
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{ |
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assert(QLIST_EMPTY(&bus->child)); |
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QLIST_REMOVE(bus, sibling); |
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} |
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int pci_bus_num(PCIBus *s)
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{ |
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if (!s->parent_dev)
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return 0; /* pci host bridge */ |
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return s->parent_dev->config[PCI_SECONDARY_BUS];
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} |
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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, config); |
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uint8_t *config; |
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int i;
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assert(size == pci_config_size(s)); |
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config = qemu_malloc(size); |
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qemu_get_buffer(f, config, size); |
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for (i = 0; i < size; ++i) { |
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
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qemu_free(config); |
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return -EINVAL;
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} |
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} |
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memcpy(s->config, config, size); |
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pci_update_mappings(s); |
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qemu_free(config); |
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return 0; |
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} |
330 |
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/* just put buffer */
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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const uint8_t **v = pv;
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assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
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qemu_put_buffer(f, *v, size); |
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} |
338 |
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static VMStateInfo vmstate_info_pci_config = {
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.name = "pci config",
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.get = get_pci_config_device, |
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.put = put_pci_config_device, |
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}; |
344 |
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static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
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uint32_t irq_state[PCI_NUM_PINS]; |
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int i;
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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irq_state[i] = qemu_get_be32(f); |
352 |
if (irq_state[i] != 0x1 && irq_state[i] != 0) { |
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fprintf(stderr, "irq state %d: must be 0 or 1.\n",
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irq_state[i]); |
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return -EINVAL;
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} |
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} |
358 |
|
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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pci_set_irq_state(s, i, irq_state[i]); |
361 |
} |
362 |
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return 0; |
364 |
} |
365 |
|
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static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
367 |
{ |
368 |
int i;
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PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
370 |
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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qemu_put_be32(f, pci_irq_state(s, i)); |
373 |
} |
374 |
} |
375 |
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static VMStateInfo vmstate_info_pci_irq_state = {
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.name = "pci irq state",
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.get = get_pci_irq_state, |
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.put = put_pci_irq_state, |
380 |
}; |
381 |
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const VMStateDescription vmstate_pci_device = {
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.name = "PCIDevice",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_LE(version_id, PCIDevice), |
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VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
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vmstate_info_pci_config, |
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PCI_CONFIG_SPACE_SIZE), |
392 |
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
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vmstate_info_pci_irq_state, |
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PCI_NUM_PINS * sizeof(int32_t)),
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VMSTATE_END_OF_LIST() |
396 |
} |
397 |
}; |
398 |
|
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const VMStateDescription vmstate_pcie_device = {
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.name = "PCIDevice",
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.version_id = 2,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
405 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
406 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
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vmstate_info_pci_config, |
408 |
PCIE_CONFIG_SPACE_SIZE), |
409 |
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
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vmstate_info_pci_irq_state, |
411 |
PCI_NUM_PINS * sizeof(int32_t)),
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VMSTATE_END_OF_LIST() |
413 |
} |
414 |
}; |
415 |
|
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static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
417 |
{ |
418 |
return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
|
419 |
} |
420 |
|
421 |
void pci_device_save(PCIDevice *s, QEMUFile *f)
|
422 |
{ |
423 |
/* Clear interrupt status bit: it is implicit
|
424 |
* in irq_state which we are saving.
|
425 |
* This makes us compatible with old devices
|
426 |
* which never set or clear this bit. */
|
427 |
s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
428 |
vmstate_save_state(f, pci_get_vmstate(s), s); |
429 |
/* Restore the interrupt status bit. */
|
430 |
pci_update_irq_status(s); |
431 |
} |
432 |
|
433 |
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
434 |
{ |
435 |
int ret;
|
436 |
ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); |
437 |
/* Restore the interrupt status bit. */
|
438 |
pci_update_irq_status(s); |
439 |
return ret;
|
440 |
} |
441 |
|
442 |
static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
443 |
{ |
444 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
445 |
pci_default_sub_vendor_id); |
446 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
447 |
pci_default_sub_device_id); |
448 |
} |
449 |
|
450 |
/*
|
451 |
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
|
452 |
*/
|
453 |
static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
454 |
{ |
455 |
const char *p; |
456 |
char *e;
|
457 |
unsigned long val; |
458 |
unsigned long dom = 0, bus = 0; |
459 |
unsigned slot = 0; |
460 |
|
461 |
p = addr; |
462 |
val = strtoul(p, &e, 16);
|
463 |
if (e == p)
|
464 |
return -1; |
465 |
if (*e == ':') { |
466 |
bus = val; |
467 |
p = e + 1;
|
468 |
val = strtoul(p, &e, 16);
|
469 |
if (e == p)
|
470 |
return -1; |
471 |
if (*e == ':') { |
472 |
dom = bus; |
473 |
bus = val; |
474 |
p = e + 1;
|
475 |
val = strtoul(p, &e, 16);
|
476 |
if (e == p)
|
477 |
return -1; |
478 |
} |
479 |
} |
480 |
|
481 |
if (dom > 0xffff || bus > 0xff || val > 0x1f) |
482 |
return -1; |
483 |
|
484 |
slot = val; |
485 |
|
486 |
if (*e)
|
487 |
return -1; |
488 |
|
489 |
/* Note: QEMU doesn't implement domains other than 0 */
|
490 |
if (!pci_find_bus(pci_find_root_bus(dom), bus))
|
491 |
return -1; |
492 |
|
493 |
*domp = dom; |
494 |
*busp = bus; |
495 |
*slotp = slot; |
496 |
return 0; |
497 |
} |
498 |
|
499 |
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
500 |
unsigned *slotp)
|
501 |
{ |
502 |
/* strip legacy tag */
|
503 |
if (!strncmp(addr, "pci_addr=", 9)) { |
504 |
addr += 9;
|
505 |
} |
506 |
if (pci_parse_devaddr(addr, domp, busp, slotp)) {
|
507 |
monitor_printf(mon, "Invalid pci address\n");
|
508 |
return -1; |
509 |
} |
510 |
return 0; |
511 |
} |
512 |
|
513 |
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
514 |
{ |
515 |
int dom, bus;
|
516 |
unsigned slot;
|
517 |
|
518 |
if (!devaddr) {
|
519 |
*devfnp = -1;
|
520 |
return pci_find_bus(pci_find_root_bus(0), 0); |
521 |
} |
522 |
|
523 |
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
524 |
return NULL; |
525 |
} |
526 |
|
527 |
*devfnp = slot << 3;
|
528 |
return pci_find_bus(pci_find_root_bus(dom), bus);
|
529 |
} |
530 |
|
531 |
static void pci_init_cmask(PCIDevice *dev) |
532 |
{ |
533 |
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
|
534 |
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
|
535 |
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
536 |
dev->cmask[PCI_REVISION_ID] = 0xff;
|
537 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
|
538 |
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
539 |
dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
540 |
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
541 |
} |
542 |
|
543 |
static void pci_init_wmask(PCIDevice *dev) |
544 |
{ |
545 |
int config_size = pci_config_size(dev);
|
546 |
|
547 |
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
548 |
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
|
549 |
pci_set_word(dev->wmask + PCI_COMMAND, |
550 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
551 |
PCI_COMMAND_INTX_DISABLE); |
552 |
|
553 |
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
|
554 |
config_size - PCI_CONFIG_HEADER_SIZE); |
555 |
} |
556 |
|
557 |
static void pci_init_wmask_bridge(PCIDevice *d) |
558 |
{ |
559 |
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
|
560 |
PCI_SEC_LETENCY_TIMER */
|
561 |
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); |
562 |
|
563 |
/* base and limit */
|
564 |
d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
|
565 |
d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
|
566 |
pci_set_word(d->wmask + PCI_MEMORY_BASE, |
567 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
568 |
pci_set_word(d->wmask + PCI_MEMORY_LIMIT, |
569 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
570 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, |
571 |
PCI_PREF_RANGE_MASK & 0xffff);
|
572 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, |
573 |
PCI_PREF_RANGE_MASK & 0xffff);
|
574 |
|
575 |
/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
|
576 |
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); |
577 |
|
578 |
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
|
579 |
} |
580 |
|
581 |
static void pci_config_alloc(PCIDevice *pci_dev) |
582 |
{ |
583 |
int config_size = pci_config_size(pci_dev);
|
584 |
|
585 |
pci_dev->config = qemu_mallocz(config_size); |
586 |
pci_dev->cmask = qemu_mallocz(config_size); |
587 |
pci_dev->wmask = qemu_mallocz(config_size); |
588 |
pci_dev->used = qemu_mallocz(config_size); |
589 |
} |
590 |
|
591 |
static void pci_config_free(PCIDevice *pci_dev) |
592 |
{ |
593 |
qemu_free(pci_dev->config); |
594 |
qemu_free(pci_dev->cmask); |
595 |
qemu_free(pci_dev->wmask); |
596 |
qemu_free(pci_dev->used); |
597 |
} |
598 |
|
599 |
/* -1 for devfn means auto assign */
|
600 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
|
601 |
const char *name, int devfn, |
602 |
PCIConfigReadFunc *config_read, |
603 |
PCIConfigWriteFunc *config_write, |
604 |
uint8_t header_type) |
605 |
{ |
606 |
if (devfn < 0) { |
607 |
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
|
608 |
devfn += 8) {
|
609 |
if (!bus->devices[devfn])
|
610 |
goto found;
|
611 |
} |
612 |
error_report("PCI: no slot/function available for %s, all in use", name);
|
613 |
return NULL; |
614 |
found: ;
|
615 |
} else if (bus->devices[devfn]) { |
616 |
error_report("PCI: slot %d function %d not available for %s, in use by %s",
|
617 |
PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); |
618 |
return NULL; |
619 |
} |
620 |
pci_dev->bus = bus; |
621 |
pci_dev->devfn = devfn; |
622 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
623 |
pci_dev->irq_state = 0;
|
624 |
pci_config_alloc(pci_dev); |
625 |
|
626 |
header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
627 |
if (header_type == PCI_HEADER_TYPE_NORMAL) {
|
628 |
pci_set_default_subsystem_id(pci_dev); |
629 |
} |
630 |
pci_init_cmask(pci_dev); |
631 |
pci_init_wmask(pci_dev); |
632 |
if (header_type == PCI_HEADER_TYPE_BRIDGE) {
|
633 |
pci_init_wmask_bridge(pci_dev); |
634 |
} |
635 |
|
636 |
if (!config_read)
|
637 |
config_read = pci_default_read_config; |
638 |
if (!config_write)
|
639 |
config_write = pci_default_write_config; |
640 |
pci_dev->config_read = config_read; |
641 |
pci_dev->config_write = config_write; |
642 |
bus->devices[devfn] = pci_dev; |
643 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
644 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
645 |
return pci_dev;
|
646 |
} |
647 |
|
648 |
static void do_pci_unregister_device(PCIDevice *pci_dev) |
649 |
{ |
650 |
qemu_free_irqs(pci_dev->irq); |
651 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
652 |
pci_config_free(pci_dev); |
653 |
} |
654 |
|
655 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
656 |
int instance_size, int devfn, |
657 |
PCIConfigReadFunc *config_read, |
658 |
PCIConfigWriteFunc *config_write) |
659 |
{ |
660 |
PCIDevice *pci_dev; |
661 |
|
662 |
pci_dev = qemu_mallocz(instance_size); |
663 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
664 |
config_read, config_write, |
665 |
PCI_HEADER_TYPE_NORMAL); |
666 |
if (pci_dev == NULL) { |
667 |
hw_error("PCI: can't register device\n");
|
668 |
} |
669 |
return pci_dev;
|
670 |
} |
671 |
|
672 |
static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
|
673 |
target_phys_addr_t addr) |
674 |
{ |
675 |
return addr + bus->mem_base;
|
676 |
} |
677 |
|
678 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
679 |
{ |
680 |
PCIIORegion *r; |
681 |
int i;
|
682 |
|
683 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
684 |
r = &pci_dev->io_regions[i]; |
685 |
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
|
686 |
continue;
|
687 |
if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
|
688 |
isa_unassign_ioport(r->addr, r->filtered_size); |
689 |
} else {
|
690 |
cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, |
691 |
r->addr), |
692 |
r->filtered_size, |
693 |
IO_MEM_UNASSIGNED); |
694 |
} |
695 |
} |
696 |
} |
697 |
|
698 |
static int pci_unregister_device(DeviceState *dev) |
699 |
{ |
700 |
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
701 |
PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
702 |
int ret = 0; |
703 |
|
704 |
if (info->exit)
|
705 |
ret = info->exit(pci_dev); |
706 |
if (ret)
|
707 |
return ret;
|
708 |
|
709 |
pci_unregister_io_regions(pci_dev); |
710 |
do_pci_unregister_device(pci_dev); |
711 |
return 0; |
712 |
} |
713 |
|
714 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
715 |
pcibus_t size, int type,
|
716 |
PCIMapIORegionFunc *map_func) |
717 |
{ |
718 |
PCIIORegion *r; |
719 |
uint32_t addr; |
720 |
pcibus_t wmask; |
721 |
|
722 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
723 |
return;
|
724 |
|
725 |
if (size & (size-1)) { |
726 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
727 |
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
728 |
exit(1);
|
729 |
} |
730 |
|
731 |
r = &pci_dev->io_regions[region_num]; |
732 |
r->addr = PCI_BAR_UNMAPPED; |
733 |
r->size = size; |
734 |
r->filtered_size = size; |
735 |
r->type = type; |
736 |
r->map_func = map_func; |
737 |
|
738 |
wmask = ~(size - 1);
|
739 |
addr = pci_bar(pci_dev, region_num); |
740 |
if (region_num == PCI_ROM_SLOT) {
|
741 |
/* ROM enable bit is writeable */
|
742 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
743 |
} |
744 |
pci_set_long(pci_dev->config + addr, type); |
745 |
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
|
746 |
r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
747 |
pci_set_quad(pci_dev->wmask + addr, wmask); |
748 |
pci_set_quad(pci_dev->cmask + addr, ~0ULL);
|
749 |
} else {
|
750 |
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
751 |
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
|
752 |
} |
753 |
} |
754 |
|
755 |
static uint32_t pci_config_get_io_base(PCIDevice *d,
|
756 |
uint32_t base, uint32_t base_upper16) |
757 |
{ |
758 |
uint32_t val; |
759 |
|
760 |
val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
|
761 |
if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
|
762 |
val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
|
763 |
} |
764 |
return val;
|
765 |
} |
766 |
|
767 |
static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
|
768 |
{ |
769 |
return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
|
770 |
<< 16;
|
771 |
} |
772 |
|
773 |
static pcibus_t pci_config_get_pref_base(PCIDevice *d,
|
774 |
uint32_t base, uint32_t upper) |
775 |
{ |
776 |
pcibus_t tmp; |
777 |
pcibus_t val; |
778 |
|
779 |
tmp = (pcibus_t)pci_get_word(d->config + base); |
780 |
val = (tmp & PCI_PREF_RANGE_MASK) << 16;
|
781 |
if (tmp & PCI_PREF_RANGE_TYPE_64) {
|
782 |
val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
|
783 |
} |
784 |
return val;
|
785 |
} |
786 |
|
787 |
static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
|
788 |
{ |
789 |
pcibus_t base; |
790 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
791 |
base = pci_config_get_io_base(bridge, |
792 |
PCI_IO_BASE, PCI_IO_BASE_UPPER16); |
793 |
} else {
|
794 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
795 |
base = pci_config_get_pref_base( |
796 |
bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); |
797 |
} else {
|
798 |
base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); |
799 |
} |
800 |
} |
801 |
|
802 |
return base;
|
803 |
} |
804 |
|
805 |
static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
|
806 |
{ |
807 |
pcibus_t limit; |
808 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
809 |
limit = pci_config_get_io_base(bridge, |
810 |
PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); |
811 |
limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ |
812 |
} else {
|
813 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
814 |
limit = pci_config_get_pref_base( |
815 |
bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); |
816 |
} else {
|
817 |
limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); |
818 |
} |
819 |
limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ |
820 |
} |
821 |
return limit;
|
822 |
} |
823 |
|
824 |
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, |
825 |
uint8_t type) |
826 |
{ |
827 |
pcibus_t base = *addr; |
828 |
pcibus_t limit = *addr + *size - 1;
|
829 |
PCIDevice *br; |
830 |
|
831 |
for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
|
832 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
833 |
|
834 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
835 |
if (!(cmd & PCI_COMMAND_IO)) {
|
836 |
goto no_map;
|
837 |
} |
838 |
} else {
|
839 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
840 |
goto no_map;
|
841 |
} |
842 |
} |
843 |
|
844 |
base = MAX(base, pci_bridge_get_base(br, type)); |
845 |
limit = MIN(limit, pci_bridge_get_limit(br, type)); |
846 |
} |
847 |
|
848 |
if (base > limit) {
|
849 |
goto no_map;
|
850 |
} |
851 |
*addr = base; |
852 |
*size = limit - base + 1;
|
853 |
return;
|
854 |
no_map:
|
855 |
*addr = PCI_BAR_UNMAPPED; |
856 |
*size = 0;
|
857 |
} |
858 |
|
859 |
static pcibus_t pci_bar_address(PCIDevice *d,
|
860 |
int reg, uint8_t type, pcibus_t size)
|
861 |
{ |
862 |
pcibus_t new_addr, last_addr; |
863 |
int bar = pci_bar(d, reg);
|
864 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
865 |
|
866 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
867 |
if (!(cmd & PCI_COMMAND_IO)) {
|
868 |
return PCI_BAR_UNMAPPED;
|
869 |
} |
870 |
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
|
871 |
last_addr = new_addr + size - 1;
|
872 |
/* NOTE: we have only 64K ioports on PC */
|
873 |
if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { |
874 |
return PCI_BAR_UNMAPPED;
|
875 |
} |
876 |
return new_addr;
|
877 |
} |
878 |
|
879 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
880 |
return PCI_BAR_UNMAPPED;
|
881 |
} |
882 |
if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
883 |
new_addr = pci_get_quad(d->config + bar); |
884 |
} else {
|
885 |
new_addr = pci_get_long(d->config + bar); |
886 |
} |
887 |
/* the ROM slot has a specific enable bit */
|
888 |
if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
|
889 |
return PCI_BAR_UNMAPPED;
|
890 |
} |
891 |
new_addr &= ~(size - 1);
|
892 |
last_addr = new_addr + size - 1;
|
893 |
/* NOTE: we do not support wrapping */
|
894 |
/* XXX: as we cannot support really dynamic
|
895 |
mappings, we handle specific values as invalid
|
896 |
mappings. */
|
897 |
if (last_addr <= new_addr || new_addr == 0 || |
898 |
last_addr == PCI_BAR_UNMAPPED) { |
899 |
return PCI_BAR_UNMAPPED;
|
900 |
} |
901 |
|
902 |
/* Now pcibus_t is 64bit.
|
903 |
* Check if 32 bit BAR wraps around explicitly.
|
904 |
* Without this, PC ide doesn't work well.
|
905 |
* TODO: remove this work around.
|
906 |
*/
|
907 |
if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
|
908 |
return PCI_BAR_UNMAPPED;
|
909 |
} |
910 |
|
911 |
/*
|
912 |
* OS is allowed to set BAR beyond its addressable
|
913 |
* bits. For example, 32 bit OS can set 64bit bar
|
914 |
* to >4G. Check it. TODO: we might need to support
|
915 |
* it in the future for e.g. PAE.
|
916 |
*/
|
917 |
if (last_addr >= TARGET_PHYS_ADDR_MAX) {
|
918 |
return PCI_BAR_UNMAPPED;
|
919 |
} |
920 |
|
921 |
return new_addr;
|
922 |
} |
923 |
|
924 |
static void pci_update_mappings(PCIDevice *d) |
925 |
{ |
926 |
PCIIORegion *r; |
927 |
int i;
|
928 |
pcibus_t new_addr, filtered_size; |
929 |
|
930 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
931 |
r = &d->io_regions[i]; |
932 |
|
933 |
/* this region isn't registered */
|
934 |
if (!r->size)
|
935 |
continue;
|
936 |
|
937 |
new_addr = pci_bar_address(d, i, r->type, r->size); |
938 |
|
939 |
/* bridge filtering */
|
940 |
filtered_size = r->size; |
941 |
if (new_addr != PCI_BAR_UNMAPPED) {
|
942 |
pci_bridge_filter(d, &new_addr, &filtered_size, r->type); |
943 |
} |
944 |
|
945 |
/* This bar isn't changed */
|
946 |
if (new_addr == r->addr && filtered_size == r->filtered_size)
|
947 |
continue;
|
948 |
|
949 |
/* now do the real mapping */
|
950 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
951 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
952 |
int class;
|
953 |
/* NOTE: specific hack for IDE in PC case:
|
954 |
only one byte must be mapped. */
|
955 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
956 |
if (class == 0x0101 && r->size == 4) { |
957 |
isa_unassign_ioport(r->addr + 2, 1); |
958 |
} else {
|
959 |
isa_unassign_ioport(r->addr, r->filtered_size); |
960 |
} |
961 |
} else {
|
962 |
cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr), |
963 |
r->filtered_size, |
964 |
IO_MEM_UNASSIGNED); |
965 |
qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
966 |
} |
967 |
} |
968 |
r->addr = new_addr; |
969 |
r->filtered_size = filtered_size; |
970 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
971 |
/*
|
972 |
* TODO: currently almost all the map funcions assumes
|
973 |
* filtered_size == size and addr & ~(size - 1) == addr.
|
974 |
* However with bridge filtering, they aren't always true.
|
975 |
* Teach them such cases, such that filtered_size < size and
|
976 |
* addr & (size - 1) != 0.
|
977 |
*/
|
978 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
979 |
r->map_func(d, i, r->addr, r->filtered_size, r->type); |
980 |
} else {
|
981 |
r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr), |
982 |
r->filtered_size, r->type); |
983 |
} |
984 |
} |
985 |
} |
986 |
} |
987 |
|
988 |
static inline int pci_irq_disabled(PCIDevice *d) |
989 |
{ |
990 |
return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
|
991 |
} |
992 |
|
993 |
/* Called after interrupt disabled field update in config space,
|
994 |
* assert/deassert interrupts if necessary.
|
995 |
* Gets original interrupt disable bit value (before update). */
|
996 |
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) |
997 |
{ |
998 |
int i, disabled = pci_irq_disabled(d);
|
999 |
if (disabled == was_irq_disabled)
|
1000 |
return;
|
1001 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
1002 |
int state = pci_irq_state(d, i);
|
1003 |
pci_change_irq_level(d, i, disabled ? -state : state); |
1004 |
} |
1005 |
} |
1006 |
|
1007 |
uint32_t pci_default_read_config(PCIDevice *d, |
1008 |
uint32_t address, int len)
|
1009 |
{ |
1010 |
uint32_t val = 0;
|
1011 |
assert(len == 1 || len == 2 || len == 4); |
1012 |
len = MIN(len, pci_config_size(d) - address); |
1013 |
memcpy(&val, d->config + address, len); |
1014 |
return le32_to_cpu(val);
|
1015 |
} |
1016 |
|
1017 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
1018 |
{ |
1019 |
int i, was_irq_disabled = pci_irq_disabled(d);
|
1020 |
uint32_t config_size = pci_config_size(d); |
1021 |
|
1022 |
for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
1023 |
uint8_t wmask = d->wmask[addr + i]; |
1024 |
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
1025 |
} |
1026 |
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
1027 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
1028 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
|
1029 |
range_covers_byte(addr, l, PCI_COMMAND)) |
1030 |
pci_update_mappings(d); |
1031 |
|
1032 |
if (range_covers_byte(addr, l, PCI_COMMAND))
|
1033 |
pci_update_irq_disabled(d, was_irq_disabled); |
1034 |
} |
1035 |
|
1036 |
/***********************************************************/
|
1037 |
/* generic PCI irq support */
|
1038 |
|
1039 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1040 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
1041 |
{ |
1042 |
PCIDevice *pci_dev = opaque; |
1043 |
int change;
|
1044 |
|
1045 |
change = level - pci_irq_state(pci_dev, irq_num); |
1046 |
if (!change)
|
1047 |
return;
|
1048 |
|
1049 |
pci_set_irq_state(pci_dev, irq_num, level); |
1050 |
pci_update_irq_status(pci_dev); |
1051 |
if (pci_irq_disabled(pci_dev))
|
1052 |
return;
|
1053 |
pci_change_irq_level(pci_dev, irq_num, change); |
1054 |
} |
1055 |
|
1056 |
/***********************************************************/
|
1057 |
/* monitor info on PCI */
|
1058 |
|
1059 |
typedef struct { |
1060 |
uint16_t class; |
1061 |
const char *desc; |
1062 |
} pci_class_desc; |
1063 |
|
1064 |
static const pci_class_desc pci_class_descriptions[] = |
1065 |
{ |
1066 |
{ 0x0100, "SCSI controller"}, |
1067 |
{ 0x0101, "IDE controller"}, |
1068 |
{ 0x0102, "Floppy controller"}, |
1069 |
{ 0x0103, "IPI controller"}, |
1070 |
{ 0x0104, "RAID controller"}, |
1071 |
{ 0x0106, "SATA controller"}, |
1072 |
{ 0x0107, "SAS controller"}, |
1073 |
{ 0x0180, "Storage controller"}, |
1074 |
{ 0x0200, "Ethernet controller"}, |
1075 |
{ 0x0201, "Token Ring controller"}, |
1076 |
{ 0x0202, "FDDI controller"}, |
1077 |
{ 0x0203, "ATM controller"}, |
1078 |
{ 0x0280, "Network controller"}, |
1079 |
{ 0x0300, "VGA controller"}, |
1080 |
{ 0x0301, "XGA controller"}, |
1081 |
{ 0x0302, "3D controller"}, |
1082 |
{ 0x0380, "Display controller"}, |
1083 |
{ 0x0400, "Video controller"}, |
1084 |
{ 0x0401, "Audio controller"}, |
1085 |
{ 0x0402, "Phone"}, |
1086 |
{ 0x0480, "Multimedia controller"}, |
1087 |
{ 0x0500, "RAM controller"}, |
1088 |
{ 0x0501, "Flash controller"}, |
1089 |
{ 0x0580, "Memory controller"}, |
1090 |
{ 0x0600, "Host bridge"}, |
1091 |
{ 0x0601, "ISA bridge"}, |
1092 |
{ 0x0602, "EISA bridge"}, |
1093 |
{ 0x0603, "MC bridge"}, |
1094 |
{ 0x0604, "PCI bridge"}, |
1095 |
{ 0x0605, "PCMCIA bridge"}, |
1096 |
{ 0x0606, "NUBUS bridge"}, |
1097 |
{ 0x0607, "CARDBUS bridge"}, |
1098 |
{ 0x0608, "RACEWAY bridge"}, |
1099 |
{ 0x0680, "Bridge"}, |
1100 |
{ 0x0c03, "USB controller"}, |
1101 |
{ 0, NULL} |
1102 |
}; |
1103 |
|
1104 |
static void pci_for_each_device_under_bus(PCIBus *bus, |
1105 |
void (*fn)(PCIBus *b, PCIDevice *d))
|
1106 |
{ |
1107 |
PCIDevice *d; |
1108 |
int devfn;
|
1109 |
|
1110 |
for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1111 |
d = bus->devices[devfn]; |
1112 |
if (d) {
|
1113 |
fn(bus, d); |
1114 |
} |
1115 |
} |
1116 |
} |
1117 |
|
1118 |
void pci_for_each_device(PCIBus *bus, int bus_num, |
1119 |
void (*fn)(PCIBus *b, PCIDevice *d))
|
1120 |
{ |
1121 |
bus = pci_find_bus(bus, bus_num); |
1122 |
|
1123 |
if (bus) {
|
1124 |
pci_for_each_device_under_bus(bus, fn); |
1125 |
} |
1126 |
} |
1127 |
|
1128 |
static void pci_device_print(Monitor *mon, QDict *device) |
1129 |
{ |
1130 |
QDict *qdict; |
1131 |
QListEntry *entry; |
1132 |
uint64_t addr, size; |
1133 |
|
1134 |
monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus")); |
1135 |
monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n", |
1136 |
qdict_get_int(device, "slot"),
|
1137 |
qdict_get_int(device, "function"));
|
1138 |
monitor_printf(mon, " ");
|
1139 |
|
1140 |
qdict = qdict_get_qdict(device, "class_info");
|
1141 |
if (qdict_haskey(qdict, "desc")) { |
1142 |
monitor_printf(mon, "%s", qdict_get_str(qdict, "desc")); |
1143 |
} else {
|
1144 |
monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class")); |
1145 |
} |
1146 |
|
1147 |
qdict = qdict_get_qdict(device, "id");
|
1148 |
monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n", |
1149 |
qdict_get_int(qdict, "device"),
|
1150 |
qdict_get_int(qdict, "vendor"));
|
1151 |
|
1152 |
if (qdict_haskey(device, "irq")) { |
1153 |
monitor_printf(mon, " IRQ %" PRId64 ".\n", |
1154 |
qdict_get_int(device, "irq"));
|
1155 |
} |
1156 |
|
1157 |
if (qdict_haskey(device, "pci_bridge")) { |
1158 |
QDict *info; |
1159 |
|
1160 |
qdict = qdict_get_qdict(device, "pci_bridge");
|
1161 |
|
1162 |
info = qdict_get_qdict(qdict, "bus");
|
1163 |
monitor_printf(mon, " BUS %" PRId64 ".\n", |
1164 |
qdict_get_int(info, "number"));
|
1165 |
monitor_printf(mon, " secondary bus %" PRId64 ".\n", |
1166 |
qdict_get_int(info, "secondary"));
|
1167 |
monitor_printf(mon, " subordinate bus %" PRId64 ".\n", |
1168 |
qdict_get_int(info, "subordinate"));
|
1169 |
|
1170 |
info = qdict_get_qdict(qdict, "io_range");
|
1171 |
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
1172 |
qdict_get_int(info, "base"),
|
1173 |
qdict_get_int(info, "limit"));
|
1174 |
|
1175 |
info = qdict_get_qdict(qdict, "memory_range");
|
1176 |
monitor_printf(mon, |
1177 |
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1178 |
qdict_get_int(info, "base"),
|
1179 |
qdict_get_int(info, "limit"));
|
1180 |
|
1181 |
info = qdict_get_qdict(qdict, "prefetchable_range");
|
1182 |
monitor_printf(mon, " prefetchable memory range "
|
1183 |
"[0x%08"PRIx64", 0x%08"PRIx64"]\n", |
1184 |
qdict_get_int(info, "base"),
|
1185 |
qdict_get_int(info, "limit"));
|
1186 |
} |
1187 |
|
1188 |
QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
|
1189 |
qdict = qobject_to_qdict(qlist_entry_obj(entry)); |
1190 |
monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar")); |
1191 |
|
1192 |
addr = qdict_get_int(qdict, "address");
|
1193 |
size = qdict_get_int(qdict, "size");
|
1194 |
|
1195 |
if (!strcmp(qdict_get_str(qdict, "type"), "io")) { |
1196 |
monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
|
1197 |
" [0x%04"FMT_PCIBUS"].\n", |
1198 |
addr, addr + size - 1);
|
1199 |
} else {
|
1200 |
monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
|
1201 |
" [0x%08"FMT_PCIBUS"].\n", |
1202 |
qdict_get_bool(qdict, "mem_type_64") ? 64 : 32, |
1203 |
qdict_get_bool(qdict, "prefetch") ?
|
1204 |
" prefetchable" : "", addr, addr + size - 1); |
1205 |
} |
1206 |
} |
1207 |
|
1208 |
monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id")); |
1209 |
|
1210 |
if (qdict_haskey(device, "pci_bridge")) { |
1211 |
qdict = qdict_get_qdict(device, "pci_bridge");
|
1212 |
if (qdict_haskey(qdict, "devices")) { |
1213 |
QListEntry *dev; |
1214 |
QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
|
1215 |
pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); |
1216 |
} |
1217 |
} |
1218 |
} |
1219 |
} |
1220 |
|
1221 |
void do_pci_info_print(Monitor *mon, const QObject *data) |
1222 |
{ |
1223 |
QListEntry *bus, *dev; |
1224 |
|
1225 |
QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) { |
1226 |
QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus)); |
1227 |
QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
|
1228 |
pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev))); |
1229 |
} |
1230 |
} |
1231 |
} |
1232 |
|
1233 |
static QObject *pci_get_dev_class(const PCIDevice *dev) |
1234 |
{ |
1235 |
int class;
|
1236 |
const pci_class_desc *desc;
|
1237 |
|
1238 |
class = pci_get_word(dev->config + PCI_CLASS_DEVICE); |
1239 |
desc = pci_class_descriptions; |
1240 |
while (desc->desc && class != desc->class)
|
1241 |
desc++; |
1242 |
|
1243 |
if (desc->desc) {
|
1244 |
return qobject_from_jsonf("{ 'desc': %s, 'class': %d }", |
1245 |
desc->desc, class); |
1246 |
} else {
|
1247 |
return qobject_from_jsonf("{ 'class': %d }", class); |
1248 |
} |
1249 |
} |
1250 |
|
1251 |
static QObject *pci_get_dev_id(const PCIDevice *dev) |
1252 |
{ |
1253 |
return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }", |
1254 |
pci_get_word(dev->config + PCI_VENDOR_ID), |
1255 |
pci_get_word(dev->config + PCI_DEVICE_ID)); |
1256 |
} |
1257 |
|
1258 |
static QObject *pci_get_regions_list(const PCIDevice *dev) |
1259 |
{ |
1260 |
int i;
|
1261 |
QList *regions_list; |
1262 |
|
1263 |
regions_list = qlist_new(); |
1264 |
|
1265 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1266 |
QObject *obj; |
1267 |
const PCIIORegion *r = &dev->io_regions[i];
|
1268 |
|
1269 |
if (!r->size) {
|
1270 |
continue;
|
1271 |
} |
1272 |
|
1273 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
1274 |
obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
|
1275 |
"'address': %" PRId64 ", " |
1276 |
"'size': %" PRId64 " }", |
1277 |
i, r->addr, r->size); |
1278 |
} else {
|
1279 |
int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
|
1280 |
|
1281 |
obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
|
1282 |
"'mem_type_64': %i, 'prefetch': %i, "
|
1283 |
"'address': %" PRId64 ", " |
1284 |
"'size': %" PRId64 " }", |
1285 |
i, mem_type_64, |
1286 |
r->type & PCI_BASE_ADDRESS_MEM_PREFETCH, |
1287 |
r->addr, r->size); |
1288 |
} |
1289 |
|
1290 |
qlist_append_obj(regions_list, obj); |
1291 |
} |
1292 |
|
1293 |
return QOBJECT(regions_list);
|
1294 |
} |
1295 |
|
1296 |
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num); |
1297 |
|
1298 |
static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num) |
1299 |
{ |
1300 |
uint8_t type; |
1301 |
QObject *obj; |
1302 |
|
1303 |
obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p," |
1304 |
" 'qdev_id': %s }",
|
1305 |
bus_num, |
1306 |
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), |
1307 |
pci_get_dev_class(dev), pci_get_dev_id(dev), |
1308 |
pci_get_regions_list(dev), |
1309 |
dev->qdev.id ? dev->qdev.id : "");
|
1310 |
|
1311 |
if (dev->config[PCI_INTERRUPT_PIN] != 0) { |
1312 |
QDict *qdict = qobject_to_qdict(obj); |
1313 |
qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
|
1314 |
} |
1315 |
|
1316 |
type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1317 |
if (type == PCI_HEADER_TYPE_BRIDGE) {
|
1318 |
QDict *qdict; |
1319 |
QObject *pci_bridge; |
1320 |
|
1321 |
pci_bridge = qobject_from_jsonf("{ 'bus': "
|
1322 |
"{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
|
1323 |
"'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " |
1324 |
"'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, " |
1325 |
"'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }", |
1326 |
dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS], |
1327 |
dev->config[PCI_SUBORDINATE_BUS], |
1328 |
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO), |
1329 |
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO), |
1330 |
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), |
1331 |
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY), |
1332 |
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | |
1333 |
PCI_BASE_ADDRESS_MEM_PREFETCH), |
1334 |
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY | |
1335 |
PCI_BASE_ADDRESS_MEM_PREFETCH)); |
1336 |
|
1337 |
if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1338 |
PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]); |
1339 |
|
1340 |
if (child_bus) {
|
1341 |
qdict = qobject_to_qdict(pci_bridge); |
1342 |
qdict_put_obj(qdict, "devices",
|
1343 |
pci_get_devices_list(child_bus, |
1344 |
dev->config[PCI_SECONDARY_BUS])); |
1345 |
} |
1346 |
} |
1347 |
qdict = qobject_to_qdict(obj); |
1348 |
qdict_put_obj(qdict, "pci_bridge", pci_bridge);
|
1349 |
} |
1350 |
|
1351 |
return obj;
|
1352 |
} |
1353 |
|
1354 |
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num) |
1355 |
{ |
1356 |
int devfn;
|
1357 |
PCIDevice *dev; |
1358 |
QList *dev_list; |
1359 |
|
1360 |
dev_list = qlist_new(); |
1361 |
|
1362 |
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1363 |
dev = bus->devices[devfn]; |
1364 |
if (dev) {
|
1365 |
qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num)); |
1366 |
} |
1367 |
} |
1368 |
|
1369 |
return QOBJECT(dev_list);
|
1370 |
} |
1371 |
|
1372 |
static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num) |
1373 |
{ |
1374 |
bus = pci_find_bus(bus, bus_num); |
1375 |
if (bus) {
|
1376 |
return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }", |
1377 |
bus_num, pci_get_devices_list(bus, bus_num)); |
1378 |
} |
1379 |
|
1380 |
return NULL; |
1381 |
} |
1382 |
|
1383 |
void do_pci_info(Monitor *mon, QObject **ret_data)
|
1384 |
{ |
1385 |
QList *bus_list; |
1386 |
struct PCIHostBus *host;
|
1387 |
|
1388 |
bus_list = qlist_new(); |
1389 |
|
1390 |
QLIST_FOREACH(host, &host_buses, next) { |
1391 |
QObject *obj = pci_get_bus_dict(host->bus, 0);
|
1392 |
if (obj) {
|
1393 |
qlist_append_obj(bus_list, obj); |
1394 |
} |
1395 |
} |
1396 |
|
1397 |
*ret_data = QOBJECT(bus_list); |
1398 |
} |
1399 |
|
1400 |
static const char * const pci_nic_models[] = { |
1401 |
"ne2k_pci",
|
1402 |
"i82551",
|
1403 |
"i82557b",
|
1404 |
"i82559er",
|
1405 |
"rtl8139",
|
1406 |
"e1000",
|
1407 |
"pcnet",
|
1408 |
"virtio",
|
1409 |
NULL
|
1410 |
}; |
1411 |
|
1412 |
static const char * const pci_nic_names[] = { |
1413 |
"ne2k_pci",
|
1414 |
"i82551",
|
1415 |
"i82557b",
|
1416 |
"i82559er",
|
1417 |
"rtl8139",
|
1418 |
"e1000",
|
1419 |
"pcnet",
|
1420 |
"virtio-net-pci",
|
1421 |
NULL
|
1422 |
}; |
1423 |
|
1424 |
/* Initialize a PCI NIC. */
|
1425 |
/* FIXME callers should check for failure, but don't */
|
1426 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1427 |
const char *default_devaddr) |
1428 |
{ |
1429 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
1430 |
PCIBus *bus; |
1431 |
int devfn;
|
1432 |
PCIDevice *pci_dev; |
1433 |
DeviceState *dev; |
1434 |
int i;
|
1435 |
|
1436 |
i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1437 |
if (i < 0) |
1438 |
return NULL; |
1439 |
|
1440 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
1441 |
if (!bus) {
|
1442 |
error_report("Invalid PCI device address %s for device %s",
|
1443 |
devaddr, pci_nic_names[i]); |
1444 |
return NULL; |
1445 |
} |
1446 |
|
1447 |
pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
1448 |
dev = &pci_dev->qdev; |
1449 |
qdev_set_nic_properties(dev, nd); |
1450 |
if (qdev_init(dev) < 0) |
1451 |
return NULL; |
1452 |
return pci_dev;
|
1453 |
} |
1454 |
|
1455 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1456 |
const char *default_devaddr) |
1457 |
{ |
1458 |
PCIDevice *res; |
1459 |
|
1460 |
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
1461 |
exit(0);
|
1462 |
|
1463 |
res = pci_nic_init(nd, default_model, default_devaddr); |
1464 |
if (!res)
|
1465 |
exit(1);
|
1466 |
return res;
|
1467 |
} |
1468 |
|
1469 |
typedef struct { |
1470 |
PCIDevice dev; |
1471 |
PCIBus bus; |
1472 |
uint32_t vid; |
1473 |
uint32_t did; |
1474 |
} PCIBridge; |
1475 |
|
1476 |
|
1477 |
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) |
1478 |
{ |
1479 |
pci_update_mappings(d); |
1480 |
} |
1481 |
|
1482 |
static void pci_bridge_update_mappings(PCIBus *b) |
1483 |
{ |
1484 |
PCIBus *child; |
1485 |
|
1486 |
pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); |
1487 |
|
1488 |
QLIST_FOREACH(child, &b->child, sibling) { |
1489 |
pci_bridge_update_mappings(child); |
1490 |
} |
1491 |
} |
1492 |
|
1493 |
static void pci_bridge_write_config(PCIDevice *d, |
1494 |
uint32_t address, uint32_t val, int len)
|
1495 |
{ |
1496 |
pci_default_write_config(d, address, val, len); |
1497 |
|
1498 |
if (/* io base/limit */ |
1499 |
ranges_overlap(address, len, PCI_IO_BASE, 2) ||
|
1500 |
|
1501 |
/* memory base/limit, prefetchable base/limit and
|
1502 |
io base/limit upper 16 */
|
1503 |
ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
|
1504 |
pci_bridge_update_mappings(d->bus); |
1505 |
} |
1506 |
} |
1507 |
|
1508 |
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
|
1509 |
{ |
1510 |
PCIBus *sec; |
1511 |
|
1512 |
if (!bus) {
|
1513 |
return NULL; |
1514 |
} |
1515 |
|
1516 |
if (pci_bus_num(bus) == bus_num) {
|
1517 |
return bus;
|
1518 |
} |
1519 |
|
1520 |
/* try child bus */
|
1521 |
if (!bus->parent_dev /* host pci bridge */ || |
1522 |
(bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num && |
1523 |
bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) { |
1524 |
for (; bus; bus = sec) {
|
1525 |
QLIST_FOREACH(sec, &bus->child, sibling) { |
1526 |
assert(sec->parent_dev); |
1527 |
if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
|
1528 |
return sec;
|
1529 |
} |
1530 |
if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
|
1531 |
bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) { |
1532 |
break;
|
1533 |
} |
1534 |
} |
1535 |
} |
1536 |
} |
1537 |
|
1538 |
return NULL; |
1539 |
} |
1540 |
|
1541 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
1542 |
{ |
1543 |
bus = pci_find_bus(bus, bus_num); |
1544 |
|
1545 |
if (!bus)
|
1546 |
return NULL; |
1547 |
|
1548 |
return bus->devices[PCI_DEVFN(slot, function)];
|
1549 |
} |
1550 |
|
1551 |
static int pci_bridge_initfn(PCIDevice *dev) |
1552 |
{ |
1553 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
1554 |
|
1555 |
pci_config_set_vendor_id(s->dev.config, s->vid); |
1556 |
pci_config_set_device_id(s->dev.config, s->did); |
1557 |
|
1558 |
pci_set_word(dev->config + PCI_STATUS, |
1559 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
1560 |
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); |
1561 |
dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; |
1562 |
pci_set_word(dev->config + PCI_SEC_STATUS, |
1563 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
1564 |
return 0; |
1565 |
} |
1566 |
|
1567 |
static int pci_bridge_exitfn(PCIDevice *pci_dev) |
1568 |
{ |
1569 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); |
1570 |
PCIBus *bus = &s->bus; |
1571 |
pci_unregister_secondary_bus(bus); |
1572 |
return 0; |
1573 |
} |
1574 |
|
1575 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
1576 |
pci_map_irq_fn map_irq, const char *name) |
1577 |
{ |
1578 |
PCIDevice *dev; |
1579 |
PCIBridge *s; |
1580 |
|
1581 |
dev = pci_create(bus, devfn, "pci-bridge");
|
1582 |
qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
|
1583 |
qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
|
1584 |
qdev_init_nofail(&dev->qdev); |
1585 |
|
1586 |
s = DO_UPCAST(PCIBridge, dev, dev); |
1587 |
pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
1588 |
return &s->bus;
|
1589 |
} |
1590 |
|
1591 |
PCIDevice *pci_bridge_get_device(PCIBus *bus) |
1592 |
{ |
1593 |
return bus->parent_dev;
|
1594 |
} |
1595 |
|
1596 |
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
1597 |
{ |
1598 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
1599 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
1600 |
PCIBus *bus; |
1601 |
int devfn, rc;
|
1602 |
|
1603 |
/* initialize cap_present for pci_is_express() and pci_config_size() */
|
1604 |
if (info->is_express) {
|
1605 |
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1606 |
} |
1607 |
|
1608 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
1609 |
devfn = pci_dev->devfn; |
1610 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
1611 |
info->config_read, info->config_write, |
1612 |
info->header_type); |
1613 |
if (pci_dev == NULL) |
1614 |
return -1; |
1615 |
rc = info->init(pci_dev); |
1616 |
if (rc != 0) { |
1617 |
do_pci_unregister_device(pci_dev); |
1618 |
return rc;
|
1619 |
} |
1620 |
|
1621 |
/* rom loading */
|
1622 |
if (pci_dev->romfile == NULL && info->romfile != NULL) |
1623 |
pci_dev->romfile = qemu_strdup(info->romfile); |
1624 |
pci_add_option_rom(pci_dev); |
1625 |
|
1626 |
if (qdev->hotplugged)
|
1627 |
bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
|
1628 |
return 0; |
1629 |
} |
1630 |
|
1631 |
static int pci_unplug_device(DeviceState *qdev) |
1632 |
{ |
1633 |
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
1634 |
|
1635 |
dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
|
1636 |
return 0; |
1637 |
} |
1638 |
|
1639 |
void pci_qdev_register(PCIDeviceInfo *info)
|
1640 |
{ |
1641 |
info->qdev.init = pci_qdev_init; |
1642 |
info->qdev.unplug = pci_unplug_device; |
1643 |
info->qdev.exit = pci_unregister_device; |
1644 |
info->qdev.bus_info = &pci_bus_info; |
1645 |
qdev_register(&info->qdev); |
1646 |
} |
1647 |
|
1648 |
void pci_qdev_register_many(PCIDeviceInfo *info)
|
1649 |
{ |
1650 |
while (info->qdev.name) {
|
1651 |
pci_qdev_register(info); |
1652 |
info++; |
1653 |
} |
1654 |
} |
1655 |
|
1656 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1657 |
{ |
1658 |
DeviceState *dev; |
1659 |
|
1660 |
dev = qdev_create(&bus->qbus, name); |
1661 |
qdev_prop_set_uint32(dev, "addr", devfn);
|
1662 |
return DO_UPCAST(PCIDevice, qdev, dev);
|
1663 |
} |
1664 |
|
1665 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1666 |
{ |
1667 |
PCIDevice *dev = pci_create(bus, devfn, name); |
1668 |
qdev_init_nofail(&dev->qdev); |
1669 |
return dev;
|
1670 |
} |
1671 |
|
1672 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
1673 |
{ |
1674 |
int config_size = pci_config_size(pdev);
|
1675 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
1676 |
int i;
|
1677 |
for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
|
1678 |
if (pdev->used[i])
|
1679 |
offset = i + 1;
|
1680 |
else if (i - offset + 1 == size) |
1681 |
return offset;
|
1682 |
return 0; |
1683 |
} |
1684 |
|
1685 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
1686 |
uint8_t *prev_p) |
1687 |
{ |
1688 |
uint8_t next, prev; |
1689 |
|
1690 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
1691 |
return 0; |
1692 |
|
1693 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1694 |
prev = next + PCI_CAP_LIST_NEXT) |
1695 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
1696 |
break;
|
1697 |
|
1698 |
if (prev_p)
|
1699 |
*prev_p = prev; |
1700 |
return next;
|
1701 |
} |
1702 |
|
1703 |
static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type) |
1704 |
{ |
1705 |
cpu_register_physical_memory(addr, size, pdev->rom_offset); |
1706 |
} |
1707 |
|
1708 |
/* Add an option rom for the device */
|
1709 |
static int pci_add_option_rom(PCIDevice *pdev) |
1710 |
{ |
1711 |
int size;
|
1712 |
char *path;
|
1713 |
void *ptr;
|
1714 |
|
1715 |
if (!pdev->romfile)
|
1716 |
return 0; |
1717 |
if (strlen(pdev->romfile) == 0) |
1718 |
return 0; |
1719 |
|
1720 |
if (!pdev->rom_bar) {
|
1721 |
/*
|
1722 |
* Load rom via fw_cfg instead of creating a rom bar,
|
1723 |
* for 0.11 compatibility.
|
1724 |
*/
|
1725 |
int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
|
1726 |
if (class == 0x0300) { |
1727 |
rom_add_vga(pdev->romfile); |
1728 |
} else {
|
1729 |
rom_add_option(pdev->romfile); |
1730 |
} |
1731 |
return 0; |
1732 |
} |
1733 |
|
1734 |
path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
1735 |
if (path == NULL) { |
1736 |
path = qemu_strdup(pdev->romfile); |
1737 |
} |
1738 |
|
1739 |
size = get_image_size(path); |
1740 |
if (size < 0) { |
1741 |
error_report("%s: failed to find romfile \"%s\"",
|
1742 |
__FUNCTION__, pdev->romfile); |
1743 |
return -1; |
1744 |
} |
1745 |
if (size & (size - 1)) { |
1746 |
size = 1 << qemu_fls(size);
|
1747 |
} |
1748 |
|
1749 |
pdev->rom_offset = qemu_ram_alloc(size); |
1750 |
|
1751 |
ptr = qemu_get_ram_ptr(pdev->rom_offset); |
1752 |
load_image(path, ptr); |
1753 |
qemu_free(path); |
1754 |
|
1755 |
pci_register_bar(pdev, PCI_ROM_SLOT, size, |
1756 |
0, pci_map_option_rom);
|
1757 |
|
1758 |
return 0; |
1759 |
} |
1760 |
|
1761 |
/* Reserve space and add capability to the linked list in pci config space */
|
1762 |
int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
|
1763 |
uint8_t offset, uint8_t size) |
1764 |
{ |
1765 |
uint8_t *config = pdev->config + offset; |
1766 |
config[PCI_CAP_LIST_ID] = cap_id; |
1767 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
1768 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
1769 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
1770 |
memset(pdev->used + offset, 0xFF, size);
|
1771 |
/* Make capability read-only by default */
|
1772 |
memset(pdev->wmask + offset, 0, size);
|
1773 |
/* Check capability by default */
|
1774 |
memset(pdev->cmask + offset, 0xFF, size);
|
1775 |
return offset;
|
1776 |
} |
1777 |
|
1778 |
/* Find and reserve space and add capability to the linked list
|
1779 |
* in pci config space */
|
1780 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1781 |
{ |
1782 |
uint8_t offset = pci_find_space(pdev, size); |
1783 |
if (!offset) {
|
1784 |
return -ENOSPC;
|
1785 |
} |
1786 |
return pci_add_capability_at_offset(pdev, cap_id, offset, size);
|
1787 |
} |
1788 |
|
1789 |
/* Unlink capability from the pci config space. */
|
1790 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
1791 |
{ |
1792 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
1793 |
if (!offset)
|
1794 |
return;
|
1795 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
1796 |
/* Make capability writeable again */
|
1797 |
memset(pdev->wmask + offset, 0xff, size);
|
1798 |
/* Clear cmask as device-specific registers can't be checked */
|
1799 |
memset(pdev->cmask + offset, 0, size);
|
1800 |
memset(pdev->used + offset, 0, size);
|
1801 |
|
1802 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
1803 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
1804 |
} |
1805 |
|
1806 |
/* Reserve space for capability at a known offset (to call after load). */
|
1807 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
1808 |
{ |
1809 |
memset(pdev->used + offset, 0xff, size);
|
1810 |
} |
1811 |
|
1812 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
1813 |
{ |
1814 |
return pci_find_capability_list(pdev, cap_id, NULL); |
1815 |
} |
1816 |
|
1817 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
1818 |
{ |
1819 |
PCIDevice *d = (PCIDevice *)dev; |
1820 |
const pci_class_desc *desc;
|
1821 |
char ctxt[64]; |
1822 |
PCIIORegion *r; |
1823 |
int i, class;
|
1824 |
|
1825 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
1826 |
desc = pci_class_descriptions; |
1827 |
while (desc->desc && class != desc->class)
|
1828 |
desc++; |
1829 |
if (desc->desc) {
|
1830 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
1831 |
} else {
|
1832 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
1833 |
} |
1834 |
|
1835 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
1836 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
1837 |
indent, "", ctxt,
|
1838 |
d->config[PCI_SECONDARY_BUS], |
1839 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
1840 |
pci_get_word(d->config + PCI_VENDOR_ID), |
1841 |
pci_get_word(d->config + PCI_DEVICE_ID), |
1842 |
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), |
1843 |
pci_get_word(d->config + PCI_SUBSYSTEM_ID)); |
1844 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1845 |
r = &d->io_regions[i]; |
1846 |
if (!r->size)
|
1847 |
continue;
|
1848 |
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
|
1849 |
" [0x%"FMT_PCIBUS"]\n", |
1850 |
indent, "",
|
1851 |
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
1852 |
r->addr, r->addr + r->size - 1);
|
1853 |
} |
1854 |
} |
1855 |
|
1856 |
static PCIDeviceInfo bridge_info = {
|
1857 |
.qdev.name = "pci-bridge",
|
1858 |
.qdev.size = sizeof(PCIBridge),
|
1859 |
.init = pci_bridge_initfn, |
1860 |
.exit = pci_bridge_exitfn, |
1861 |
.config_write = pci_bridge_write_config, |
1862 |
.header_type = PCI_HEADER_TYPE_BRIDGE, |
1863 |
.qdev.props = (Property[]) { |
1864 |
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), |
1865 |
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), |
1866 |
DEFINE_PROP_END_OF_LIST(), |
1867 |
} |
1868 |
}; |
1869 |
|
1870 |
static void pci_register_devices(void) |
1871 |
{ |
1872 |
pci_qdev_register(&bridge_info); |
1873 |
} |
1874 |
|
1875 |
device_init(pci_register_devices) |