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1 | ab93bbe2 | bellard | /*
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2 | ab93bbe2 | bellard | * common defines for all CPUs
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3 | ab93bbe2 | bellard | *
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4 | ab93bbe2 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | ab93bbe2 | bellard | *
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6 | ab93bbe2 | bellard | * This library is free software; you can redistribute it and/or
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7 | ab93bbe2 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | ab93bbe2 | bellard | * License as published by the Free Software Foundation; either
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9 | ab93bbe2 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | ab93bbe2 | bellard | *
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11 | ab93bbe2 | bellard | * This library is distributed in the hope that it will be useful,
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12 | ab93bbe2 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ab93bbe2 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ab93bbe2 | bellard | * Lesser General Public License for more details.
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15 | ab93bbe2 | bellard | *
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16 | ab93bbe2 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | ab93bbe2 | bellard | * License along with this library; if not, write to the Free Software
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18 | ab93bbe2 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | ab93bbe2 | bellard | */
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20 | ab93bbe2 | bellard | #ifndef CPU_DEFS_H
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21 | ab93bbe2 | bellard | #define CPU_DEFS_H
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22 | ab93bbe2 | bellard | |
23 | ab93bbe2 | bellard | #include "config.h" |
24 | ab93bbe2 | bellard | #include <setjmp.h> |
25 | ed1c0bcb | bellard | #include <inttypes.h> |
26 | ed1c0bcb | bellard | #include "osdep.h" |
27 | ab93bbe2 | bellard | |
28 | 35b66fc4 | bellard | #ifndef TARGET_LONG_BITS
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29 | 35b66fc4 | bellard | #error TARGET_LONG_BITS must be defined before including this header
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30 | 35b66fc4 | bellard | #endif
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31 | 35b66fc4 | bellard | |
32 | ab6d960f | bellard | #ifndef TARGET_PHYS_ADDR_BITS
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33 | 4f2ac237 | bellard | #if TARGET_LONG_BITS >= HOST_LONG_BITS
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34 | ab6d960f | bellard | #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
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35 | 4f2ac237 | bellard | #else
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36 | 4f2ac237 | bellard | #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
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37 | 4f2ac237 | bellard | #endif
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38 | ab6d960f | bellard | #endif
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39 | ab6d960f | bellard | |
40 | 35b66fc4 | bellard | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
41 | 35b66fc4 | bellard | |
42 | ab6d960f | bellard | /* target_ulong is the type of a virtual address */
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43 | 35b66fc4 | bellard | #if TARGET_LONG_SIZE == 4 |
44 | 35b66fc4 | bellard | typedef int32_t target_long;
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45 | 35b66fc4 | bellard | typedef uint32_t target_ulong;
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46 | c27004ec | bellard | #define TARGET_FMT_lx "%08x" |
47 | 35b66fc4 | bellard | #elif TARGET_LONG_SIZE == 8 |
48 | 35b66fc4 | bellard | typedef int64_t target_long;
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49 | 35b66fc4 | bellard | typedef uint64_t target_ulong;
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50 | c27004ec | bellard | #define TARGET_FMT_lx "%016llx" |
51 | 35b66fc4 | bellard | #else
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52 | 35b66fc4 | bellard | #error TARGET_LONG_SIZE undefined
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53 | 35b66fc4 | bellard | #endif
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54 | 35b66fc4 | bellard | |
55 | ab6d960f | bellard | /* target_phys_addr_t is the type of a physical address (its size can
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56 | 4f2ac237 | bellard | be different from 'target_ulong'). We have sizeof(target_phys_addr)
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57 | 4f2ac237 | bellard | = max(sizeof(unsigned long),
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58 | 4f2ac237 | bellard | sizeof(size_of_target_physical_address)) because we must pass a
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59 | 4f2ac237 | bellard | host pointer to memory operations in some cases */
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60 | 4f2ac237 | bellard | |
61 | ab6d960f | bellard | #if TARGET_PHYS_ADDR_BITS == 32 |
62 | ab6d960f | bellard | typedef uint32_t target_phys_addr_t;
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63 | ab6d960f | bellard | #elif TARGET_PHYS_ADDR_BITS == 64 |
64 | ab6d960f | bellard | typedef uint64_t target_phys_addr_t;
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65 | ab6d960f | bellard | #else
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66 | ab6d960f | bellard | #error TARGET_PHYS_ADDR_BITS undefined
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67 | ab6d960f | bellard | #endif
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68 | ab6d960f | bellard | |
69 | ff7b8f5b | bellard | /* address in the RAM (different from a physical address) */
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70 | ff7b8f5b | bellard | typedef unsigned long ram_addr_t; |
71 | ff7b8f5b | bellard | |
72 | f193c797 | bellard | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
73 | f193c797 | bellard | |
74 | 2be0071f | bellard | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
75 | 2be0071f | bellard | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
76 | 2be0071f | bellard | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
77 | 5a1e3cfc | bellard | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
78 | ab93bbe2 | bellard | #define MAX_BREAKPOINTS 32 |
79 | ab93bbe2 | bellard | |
80 | a316d335 | bellard | #define TB_JMP_CACHE_BITS 12 |
81 | a316d335 | bellard | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
82 | a316d335 | bellard | |
83 | 84b7b8e7 | bellard | #define CPU_TLB_BITS 8 |
84 | 84b7b8e7 | bellard | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
85 | ab93bbe2 | bellard | |
86 | ab93bbe2 | bellard | typedef struct CPUTLBEntry { |
87 | db8d7466 | bellard | /* bit 31 to TARGET_PAGE_BITS : virtual address
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88 | db8d7466 | bellard | bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
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89 | db8d7466 | bellard | zone number
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90 | db8d7466 | bellard | bit 3 : indicates that the entry is invalid
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91 | db8d7466 | bellard | bit 2..0 : zero
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92 | db8d7466 | bellard | */
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93 | 84b7b8e7 | bellard | target_ulong addr_read; |
94 | 84b7b8e7 | bellard | target_ulong addr_write; |
95 | 84b7b8e7 | bellard | target_ulong addr_code; |
96 | db8d7466 | bellard | /* addend to virtual address to get physical address */
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97 | 4f2ac237 | bellard | target_phys_addr_t addend; |
98 | ab93bbe2 | bellard | } CPUTLBEntry; |
99 | ab93bbe2 | bellard | |
100 | a316d335 | bellard | #define CPU_COMMON \
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101 | a316d335 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
102 | a316d335 | bellard | /* soft mmu support */ \
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103 | a316d335 | bellard | /* in order to avoid passing too many arguments to the memory \
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104 | a316d335 | bellard | write helpers, we store some rarely used information in the CPU \
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105 | a316d335 | bellard | context) */ \
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106 | a316d335 | bellard | unsigned long mem_write_pc; /* host pc at which the memory was \ |
107 | a316d335 | bellard | written */ \
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108 | a316d335 | bellard | target_ulong mem_write_vaddr; /* target virtual addr at which the \
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109 | a316d335 | bellard | memory was written */ \
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110 | a316d335 | bellard | /* 0 = kernel, 1 = user */ \
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111 | 84b7b8e7 | bellard | CPUTLBEntry tlb_table[2][CPU_TLB_SIZE]; \
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112 | a316d335 | bellard | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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113 | a316d335 | bellard | \ |
114 | a316d335 | bellard | /* from this point: preserved by CPU reset */ \
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115 | a316d335 | bellard | /* ice debug support */ \
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116 | a316d335 | bellard | target_ulong breakpoints[MAX_BREAKPOINTS]; \ |
117 | a316d335 | bellard | int nb_breakpoints; \
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118 | a316d335 | bellard | int singlestep_enabled; \
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119 | a316d335 | bellard | \ |
120 | 6a00d601 | bellard | void *next_cpu; /* next CPU sharing TB cache */ \ |
121 | 6a00d601 | bellard | int cpu_index; /* CPU index (informative) */ \ |
122 | a316d335 | bellard | /* user data */ \
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123 | a316d335 | bellard | void *opaque;
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124 | a316d335 | bellard | |
125 | ab93bbe2 | bellard | #endif |