root / target-mips / op_helper.c @ 1247c5f7
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1 | 6af0bf9c | bellard | /*
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2 | 6af0bf9c | bellard | * MIPS emulation helpers for qemu.
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3 | 6af0bf9c | bellard | *
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4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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5 | 6af0bf9c | bellard | *
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6 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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7 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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9 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 6af0bf9c | bellard | *
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11 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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12 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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15 | 6af0bf9c | bellard | *
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16 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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18 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 6af0bf9c | bellard | */
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20 | 6af0bf9c | bellard | #include <math.h> |
21 | 6af0bf9c | bellard | #include "exec.h" |
22 | 6af0bf9c | bellard | |
23 | 6af0bf9c | bellard | #define MIPS_DEBUG_DISAS
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24 | 6af0bf9c | bellard | |
25 | 4ad40f36 | bellard | #define GETPC() (__builtin_return_address(0)) |
26 | 4ad40f36 | bellard | |
27 | 6af0bf9c | bellard | /*****************************************************************************/
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28 | 6af0bf9c | bellard | /* Exceptions processing helpers */
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29 | 6af0bf9c | bellard | void cpu_loop_exit(void) |
30 | 6af0bf9c | bellard | { |
31 | 6af0bf9c | bellard | longjmp(env->jmp_env, 1);
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32 | 6af0bf9c | bellard | } |
33 | 6af0bf9c | bellard | |
34 | 6af0bf9c | bellard | void do_raise_exception_err (uint32_t exception, int error_code) |
35 | 6af0bf9c | bellard | { |
36 | 6af0bf9c | bellard | #if 1 |
37 | 6af0bf9c | bellard | if (logfile && exception < 0x100) |
38 | 6af0bf9c | bellard | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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39 | 6af0bf9c | bellard | #endif
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40 | 6af0bf9c | bellard | env->exception_index = exception; |
41 | 6af0bf9c | bellard | env->error_code = error_code; |
42 | 6af0bf9c | bellard | T0 = 0;
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43 | 6af0bf9c | bellard | cpu_loop_exit(); |
44 | 6af0bf9c | bellard | } |
45 | 6af0bf9c | bellard | |
46 | 6af0bf9c | bellard | void do_raise_exception (uint32_t exception)
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47 | 6af0bf9c | bellard | { |
48 | 6af0bf9c | bellard | do_raise_exception_err(exception, 0);
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49 | 6af0bf9c | bellard | } |
50 | 6af0bf9c | bellard | |
51 | 4ad40f36 | bellard | void do_restore_state (void *pc_ptr) |
52 | 4ad40f36 | bellard | { |
53 | 4ad40f36 | bellard | TranslationBlock *tb; |
54 | 4ad40f36 | bellard | unsigned long pc = (unsigned long) pc_ptr; |
55 | 4ad40f36 | bellard | |
56 | 4ad40f36 | bellard | tb = tb_find_pc (pc); |
57 | 4ad40f36 | bellard | cpu_restore_state (tb, env, pc, NULL);
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58 | 4ad40f36 | bellard | } |
59 | 4ad40f36 | bellard | |
60 | 4ad40f36 | bellard | void do_raise_exception_direct (uint32_t exception)
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61 | 4ad40f36 | bellard | { |
62 | 4ad40f36 | bellard | do_restore_state (GETPC ()); |
63 | 4ad40f36 | bellard | do_raise_exception_err (exception, 0);
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64 | 4ad40f36 | bellard | } |
65 | 4ad40f36 | bellard | |
66 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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67 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
68 | 6af0bf9c | bellard | #undef MEMSUFFIX
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69 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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70 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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71 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
72 | 6af0bf9c | bellard | #undef MEMSUFFIX
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73 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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74 | 6af0bf9c | bellard | #include "op_helper_mem.c" |
75 | 6af0bf9c | bellard | #undef MEMSUFFIX
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76 | 6af0bf9c | bellard | #endif
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77 | 6af0bf9c | bellard | |
78 | 6af0bf9c | bellard | /* 64 bits arithmetic for 32 bits hosts */
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79 | 6af0bf9c | bellard | #if (HOST_LONG_BITS == 32) |
80 | 6af0bf9c | bellard | static inline uint64_t get_HILO (void) |
81 | 6af0bf9c | bellard | { |
82 | 6af0bf9c | bellard | return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; |
83 | 6af0bf9c | bellard | } |
84 | 6af0bf9c | bellard | |
85 | 6af0bf9c | bellard | static inline void set_HILO (uint64_t HILO) |
86 | 6af0bf9c | bellard | { |
87 | 6af0bf9c | bellard | env->LO = HILO & 0xFFFFFFFF;
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88 | 6af0bf9c | bellard | env->HI = HILO >> 32;
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89 | 6af0bf9c | bellard | } |
90 | 6af0bf9c | bellard | |
91 | 6af0bf9c | bellard | void do_mult (void) |
92 | 6af0bf9c | bellard | { |
93 | 4ad40f36 | bellard | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
94 | 6af0bf9c | bellard | } |
95 | 6af0bf9c | bellard | |
96 | 6af0bf9c | bellard | void do_multu (void) |
97 | 6af0bf9c | bellard | { |
98 | 6af0bf9c | bellard | set_HILO((uint64_t)T0 * (uint64_t)T1); |
99 | 6af0bf9c | bellard | } |
100 | 6af0bf9c | bellard | |
101 | 6af0bf9c | bellard | void do_madd (void) |
102 | 6af0bf9c | bellard | { |
103 | 6af0bf9c | bellard | int64_t tmp; |
104 | 6af0bf9c | bellard | |
105 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
106 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() + tmp); |
107 | 6af0bf9c | bellard | } |
108 | 6af0bf9c | bellard | |
109 | 6af0bf9c | bellard | void do_maddu (void) |
110 | 6af0bf9c | bellard | { |
111 | 6af0bf9c | bellard | uint64_t tmp; |
112 | 6af0bf9c | bellard | |
113 | 6af0bf9c | bellard | tmp = ((uint64_t)T0 * (uint64_t)T1); |
114 | 6af0bf9c | bellard | set_HILO(get_HILO() + tmp); |
115 | 6af0bf9c | bellard | } |
116 | 6af0bf9c | bellard | |
117 | 6af0bf9c | bellard | void do_msub (void) |
118 | 6af0bf9c | bellard | { |
119 | 6af0bf9c | bellard | int64_t tmp; |
120 | 6af0bf9c | bellard | |
121 | 4ad40f36 | bellard | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
122 | 6af0bf9c | bellard | set_HILO((int64_t)get_HILO() - tmp); |
123 | 6af0bf9c | bellard | } |
124 | 6af0bf9c | bellard | |
125 | 6af0bf9c | bellard | void do_msubu (void) |
126 | 6af0bf9c | bellard | { |
127 | 6af0bf9c | bellard | uint64_t tmp; |
128 | 6af0bf9c | bellard | |
129 | 6af0bf9c | bellard | tmp = ((uint64_t)T0 * (uint64_t)T1); |
130 | 6af0bf9c | bellard | set_HILO(get_HILO() - tmp); |
131 | 6af0bf9c | bellard | } |
132 | 6af0bf9c | bellard | #endif
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133 | 6af0bf9c | bellard | |
134 | 048f6b4d | bellard | #if defined(CONFIG_USER_ONLY)
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135 | 048f6b4d | bellard | void do_mfc0 (int reg, int sel) |
136 | 048f6b4d | bellard | { |
137 | 048f6b4d | bellard | cpu_abort(env, "mfc0 reg=%d sel=%d\n", reg, sel);
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138 | 048f6b4d | bellard | } |
139 | 048f6b4d | bellard | void do_mtc0 (int reg, int sel) |
140 | 048f6b4d | bellard | { |
141 | 048f6b4d | bellard | cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel);
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142 | 048f6b4d | bellard | } |
143 | 048f6b4d | bellard | |
144 | 048f6b4d | bellard | void do_tlbwi (void) |
145 | 048f6b4d | bellard | { |
146 | 048f6b4d | bellard | cpu_abort(env, "tlbwi\n");
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147 | 048f6b4d | bellard | } |
148 | 048f6b4d | bellard | |
149 | 048f6b4d | bellard | void do_tlbwr (void) |
150 | 048f6b4d | bellard | { |
151 | 048f6b4d | bellard | cpu_abort(env, "tlbwr\n");
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152 | 048f6b4d | bellard | } |
153 | 048f6b4d | bellard | |
154 | 048f6b4d | bellard | void do_tlbp (void) |
155 | 048f6b4d | bellard | { |
156 | 048f6b4d | bellard | cpu_abort(env, "tlbp\n");
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157 | 048f6b4d | bellard | } |
158 | 048f6b4d | bellard | |
159 | 048f6b4d | bellard | void do_tlbr (void) |
160 | 048f6b4d | bellard | { |
161 | 048f6b4d | bellard | cpu_abort(env, "tlbr\n");
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162 | 048f6b4d | bellard | } |
163 | 048f6b4d | bellard | #else
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164 | 048f6b4d | bellard | |
165 | 6af0bf9c | bellard | /* CP0 helpers */
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166 | 6af0bf9c | bellard | void do_mfc0 (int reg, int sel) |
167 | 6af0bf9c | bellard | { |
168 | 6af0bf9c | bellard | const unsigned char *rn; |
169 | 6af0bf9c | bellard | |
170 | 6af0bf9c | bellard | if (sel != 0 && reg != 16 && reg != 28) { |
171 | 6af0bf9c | bellard | rn = "invalid";
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172 | 6af0bf9c | bellard | goto print;
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173 | 6af0bf9c | bellard | } |
174 | 6af0bf9c | bellard | switch (reg) {
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175 | 6af0bf9c | bellard | case 0: |
176 | 6af0bf9c | bellard | T0 = env->CP0_index; |
177 | 6af0bf9c | bellard | rn = "Index";
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178 | 6af0bf9c | bellard | break;
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179 | 6af0bf9c | bellard | case 1: |
180 | 6af0bf9c | bellard | T0 = cpu_mips_get_random(env); |
181 | 6af0bf9c | bellard | rn = "Random";
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182 | 6af0bf9c | bellard | break;
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183 | 6af0bf9c | bellard | case 2: |
184 | 6af0bf9c | bellard | T0 = env->CP0_EntryLo0; |
185 | 6af0bf9c | bellard | rn = "EntryLo0";
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186 | 6af0bf9c | bellard | break;
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187 | 6af0bf9c | bellard | case 3: |
188 | 6af0bf9c | bellard | T0 = env->CP0_EntryLo1; |
189 | 6af0bf9c | bellard | rn = "EntryLo1";
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190 | 6af0bf9c | bellard | break;
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191 | 6af0bf9c | bellard | case 4: |
192 | 6af0bf9c | bellard | T0 = env->CP0_Context; |
193 | 6af0bf9c | bellard | rn = "Context";
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194 | 6af0bf9c | bellard | break;
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195 | 6af0bf9c | bellard | case 5: |
196 | 6af0bf9c | bellard | T0 = env->CP0_PageMask; |
197 | 6af0bf9c | bellard | rn = "PageMask";
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198 | 6af0bf9c | bellard | break;
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199 | 6af0bf9c | bellard | case 6: |
200 | 6af0bf9c | bellard | T0 = env->CP0_Wired; |
201 | 6af0bf9c | bellard | rn = "Wired";
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202 | 6af0bf9c | bellard | break;
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203 | 6af0bf9c | bellard | case 8: |
204 | 6af0bf9c | bellard | T0 = env->CP0_BadVAddr; |
205 | 6af0bf9c | bellard | rn = "BadVaddr";
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206 | 6af0bf9c | bellard | break;
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207 | 6af0bf9c | bellard | case 9: |
208 | 6af0bf9c | bellard | T0 = cpu_mips_get_count(env); |
209 | 6af0bf9c | bellard | rn = "Count";
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210 | 6af0bf9c | bellard | break;
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211 | 6af0bf9c | bellard | case 10: |
212 | 6af0bf9c | bellard | T0 = env->CP0_EntryHi; |
213 | 6af0bf9c | bellard | rn = "EntryHi";
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214 | 6af0bf9c | bellard | break;
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215 | 6af0bf9c | bellard | case 11: |
216 | 6af0bf9c | bellard | T0 = env->CP0_Compare; |
217 | 6af0bf9c | bellard | rn = "Compare";
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218 | 6af0bf9c | bellard | break;
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219 | 6af0bf9c | bellard | case 12: |
220 | 6af0bf9c | bellard | T0 = env->CP0_Status; |
221 | 6af0bf9c | bellard | if (env->hflags & MIPS_HFLAG_UM)
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222 | 90b37806 | bellard | T0 |= (1 << CP0St_UM);
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223 | 6af0bf9c | bellard | if (env->hflags & MIPS_HFLAG_ERL)
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224 | 90b37806 | bellard | T0 |= (1 << CP0St_ERL);
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225 | 6af0bf9c | bellard | if (env->hflags & MIPS_HFLAG_EXL)
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226 | 90b37806 | bellard | T0 |= (1 << CP0St_EXL);
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227 | 6af0bf9c | bellard | rn = "Status";
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228 | 6af0bf9c | bellard | break;
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229 | 6af0bf9c | bellard | case 13: |
230 | 6af0bf9c | bellard | T0 = env->CP0_Cause; |
231 | 6af0bf9c | bellard | rn = "Cause";
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232 | 6af0bf9c | bellard | break;
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233 | 6af0bf9c | bellard | case 14: |
234 | 6af0bf9c | bellard | T0 = env->CP0_EPC; |
235 | 6af0bf9c | bellard | rn = "EPC";
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236 | 6af0bf9c | bellard | break;
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237 | 6af0bf9c | bellard | case 15: |
238 | 6af0bf9c | bellard | T0 = env->CP0_PRid; |
239 | 6af0bf9c | bellard | rn = "PRid";
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240 | 6af0bf9c | bellard | break;
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241 | 6af0bf9c | bellard | case 16: |
242 | 6af0bf9c | bellard | switch (sel) {
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243 | 6af0bf9c | bellard | case 0: |
244 | 6af0bf9c | bellard | T0 = env->CP0_Config0; |
245 | 6af0bf9c | bellard | rn = "Config";
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246 | 6af0bf9c | bellard | break;
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247 | 6af0bf9c | bellard | case 1: |
248 | 6af0bf9c | bellard | T0 = env->CP0_Config1; |
249 | 6af0bf9c | bellard | rn = "Config1";
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250 | 6af0bf9c | bellard | break;
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251 | 6af0bf9c | bellard | default:
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252 | 6af0bf9c | bellard | rn = "Unknown config register";
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253 | 6af0bf9c | bellard | break;
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254 | 6af0bf9c | bellard | } |
255 | 6af0bf9c | bellard | break;
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256 | 6af0bf9c | bellard | case 17: |
257 | 6af0bf9c | bellard | T0 = env->CP0_LLAddr >> 4;
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258 | 6af0bf9c | bellard | rn = "LLAddr";
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259 | 6af0bf9c | bellard | break;
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260 | 6af0bf9c | bellard | case 18: |
261 | 6af0bf9c | bellard | T0 = env->CP0_WatchLo; |
262 | 6af0bf9c | bellard | rn = "WatchLo";
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263 | 6af0bf9c | bellard | break;
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264 | 6af0bf9c | bellard | case 19: |
265 | 6af0bf9c | bellard | T0 = env->CP0_WatchHi; |
266 | 6af0bf9c | bellard | rn = "WatchHi";
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267 | 6af0bf9c | bellard | break;
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268 | 6af0bf9c | bellard | case 23: |
269 | 6af0bf9c | bellard | T0 = env->CP0_Debug; |
270 | 6af0bf9c | bellard | if (env->hflags & MIPS_HFLAG_DM)
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271 | 6af0bf9c | bellard | T0 |= 1 << CP0DB_DM;
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272 | 6af0bf9c | bellard | rn = "Debug";
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273 | 6af0bf9c | bellard | break;
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274 | 6af0bf9c | bellard | case 24: |
275 | 6af0bf9c | bellard | T0 = env->CP0_DEPC; |
276 | 6af0bf9c | bellard | rn = "DEPC";
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277 | 6af0bf9c | bellard | break;
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278 | 6af0bf9c | bellard | case 28: |
279 | 6af0bf9c | bellard | switch (sel) {
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280 | 6af0bf9c | bellard | case 0: |
281 | 6af0bf9c | bellard | T0 = env->CP0_TagLo; |
282 | 6af0bf9c | bellard | rn = "TagLo";
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283 | 6af0bf9c | bellard | break;
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284 | 6af0bf9c | bellard | case 1: |
285 | 6af0bf9c | bellard | T0 = env->CP0_DataLo; |
286 | 6af0bf9c | bellard | rn = "DataLo";
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287 | 6af0bf9c | bellard | break;
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288 | 6af0bf9c | bellard | default:
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289 | 6af0bf9c | bellard | rn = "unknown sel";
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290 | 6af0bf9c | bellard | break;
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291 | 6af0bf9c | bellard | } |
292 | 6af0bf9c | bellard | break;
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293 | 6af0bf9c | bellard | case 30: |
294 | 6af0bf9c | bellard | T0 = env->CP0_ErrorEPC; |
295 | 6af0bf9c | bellard | rn = "ErrorEPC";
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296 | 6af0bf9c | bellard | break;
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297 | 6af0bf9c | bellard | case 31: |
298 | 6af0bf9c | bellard | T0 = env->CP0_DESAVE; |
299 | 6af0bf9c | bellard | rn = "DESAVE";
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300 | 6af0bf9c | bellard | break;
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301 | 6af0bf9c | bellard | default:
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302 | 6af0bf9c | bellard | rn = "unknown";
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303 | 6af0bf9c | bellard | break;
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304 | 6af0bf9c | bellard | } |
305 | 6af0bf9c | bellard | print:
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306 | 6af0bf9c | bellard | #if defined MIPS_DEBUG_DISAS
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307 | 6af0bf9c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
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308 | 6af0bf9c | bellard | fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n",
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309 | 6af0bf9c | bellard | env->PC, rn, T0, reg, sel); |
310 | 6af0bf9c | bellard | } |
311 | 6af0bf9c | bellard | #endif
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312 | 6af0bf9c | bellard | return;
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313 | 6af0bf9c | bellard | } |
314 | 6af0bf9c | bellard | |
315 | 6af0bf9c | bellard | void do_mtc0 (int reg, int sel) |
316 | 6af0bf9c | bellard | { |
317 | 6af0bf9c | bellard | const unsigned char *rn; |
318 | 6af0bf9c | bellard | uint32_t val, old, mask; |
319 | 6af0bf9c | bellard | |
320 | 6af0bf9c | bellard | if (sel != 0 && reg != 16 && reg != 28) { |
321 | 6af0bf9c | bellard | val = -1;
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322 | 6af0bf9c | bellard | old = -1;
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323 | 6af0bf9c | bellard | rn = "invalid";
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324 | 6af0bf9c | bellard | goto print;
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325 | 6af0bf9c | bellard | } |
326 | 6af0bf9c | bellard | switch (reg) {
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327 | 6af0bf9c | bellard | case 0: |
328 | 6af0bf9c | bellard | val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F); |
329 | 6af0bf9c | bellard | old = env->CP0_index; |
330 | 6af0bf9c | bellard | env->CP0_index = val; |
331 | 6af0bf9c | bellard | rn = "Index";
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332 | 6af0bf9c | bellard | break;
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333 | 6af0bf9c | bellard | case 2: |
334 | 6af0bf9c | bellard | val = T0 & 0x03FFFFFFF;
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335 | 6af0bf9c | bellard | old = env->CP0_EntryLo0; |
336 | 6af0bf9c | bellard | env->CP0_EntryLo0 = val; |
337 | 6af0bf9c | bellard | rn = "EntryLo0";
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338 | 6af0bf9c | bellard | break;
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339 | 6af0bf9c | bellard | case 3: |
340 | 6af0bf9c | bellard | val = T0 & 0x03FFFFFFF;
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341 | 6af0bf9c | bellard | old = env->CP0_EntryLo1; |
342 | 6af0bf9c | bellard | env->CP0_EntryLo1 = val; |
343 | 6af0bf9c | bellard | rn = "EntryLo1";
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344 | 6af0bf9c | bellard | break;
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345 | 6af0bf9c | bellard | case 4: |
346 | 6af0bf9c | bellard | val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0); |
347 | 6af0bf9c | bellard | old = env->CP0_Context; |
348 | 6af0bf9c | bellard | env->CP0_Context = val; |
349 | 6af0bf9c | bellard | rn = "Context";
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350 | 6af0bf9c | bellard | break;
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351 | 6af0bf9c | bellard | case 5: |
352 | 6af0bf9c | bellard | val = T0 & 0x01FFE000;
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353 | 6af0bf9c | bellard | old = env->CP0_PageMask; |
354 | 6af0bf9c | bellard | env->CP0_PageMask = val; |
355 | 6af0bf9c | bellard | rn = "PageMask";
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356 | 6af0bf9c | bellard | break;
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357 | 6af0bf9c | bellard | case 6: |
358 | 6af0bf9c | bellard | val = T0 & 0x0000000F;
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359 | 6af0bf9c | bellard | old = env->CP0_Wired; |
360 | 6af0bf9c | bellard | env->CP0_Wired = val; |
361 | 6af0bf9c | bellard | rn = "Wired";
|
362 | 6af0bf9c | bellard | break;
|
363 | 6af0bf9c | bellard | case 9: |
364 | 6af0bf9c | bellard | val = T0; |
365 | 6af0bf9c | bellard | old = cpu_mips_get_count(env); |
366 | 6af0bf9c | bellard | cpu_mips_store_count(env, val); |
367 | 6af0bf9c | bellard | rn = "Count";
|
368 | 6af0bf9c | bellard | break;
|
369 | 6af0bf9c | bellard | case 10: |
370 | 6af0bf9c | bellard | val = T0 & 0xFFFFF0FF;
|
371 | 6af0bf9c | bellard | old = env->CP0_EntryHi; |
372 | 6af0bf9c | bellard | env->CP0_EntryHi = val; |
373 | 4ad40f36 | bellard | /* If the ASID changes, flush qemu's TLB. */
|
374 | 4ad40f36 | bellard | if ((old & 0xFF) != (val & 0xFF)) |
375 | 4ad40f36 | bellard | tlb_flush (env, 1);
|
376 | 6af0bf9c | bellard | rn = "EntryHi";
|
377 | 6af0bf9c | bellard | break;
|
378 | 6af0bf9c | bellard | case 11: |
379 | 6af0bf9c | bellard | val = T0; |
380 | 6af0bf9c | bellard | old = env->CP0_Compare; |
381 | 6af0bf9c | bellard | cpu_mips_store_compare(env, val); |
382 | 6af0bf9c | bellard | rn = "Compare";
|
383 | 6af0bf9c | bellard | break;
|
384 | 6af0bf9c | bellard | case 12: |
385 | 6af0bf9c | bellard | val = T0 & 0xFA78FF01;
|
386 | 6af0bf9c | bellard | if (T0 & (1 << CP0St_UM)) |
387 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_UM; |
388 | 6af0bf9c | bellard | else
|
389 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_UM; |
390 | 6af0bf9c | bellard | if (T0 & (1 << CP0St_ERL)) |
391 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_ERL; |
392 | 6af0bf9c | bellard | else
|
393 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_ERL; |
394 | 6af0bf9c | bellard | if (T0 & (1 << CP0St_EXL)) |
395 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_EXL; |
396 | 6af0bf9c | bellard | else
|
397 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_EXL; |
398 | 6af0bf9c | bellard | old = env->CP0_Status; |
399 | 6af0bf9c | bellard | env->CP0_Status = val; |
400 | 6af0bf9c | bellard | /* If we unmasked an asserted IRQ, raise it */
|
401 | ae022501 | bellard | mask = 0x0000FF00;
|
402 | 6af0bf9c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
403 | 6af0bf9c | bellard | fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
|
404 | 6af0bf9c | bellard | old, val, env->CP0_Cause, old & mask, val & mask, |
405 | 6af0bf9c | bellard | env->CP0_Cause & mask); |
406 | 6af0bf9c | bellard | } |
407 | 6af0bf9c | bellard | #if 1 |
408 | 6af0bf9c | bellard | if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) && |
409 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_EXL) && |
410 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_ERL) && |
411 | 6af0bf9c | bellard | !(env->hflags & MIPS_HFLAG_DM) && |
412 | e1d9a508 | bellard | (env->CP0_Status & env->CP0_Cause & mask)) { |
413 | 6af0bf9c | bellard | if (logfile)
|
414 | 6af0bf9c | bellard | fprintf(logfile, "Raise pending IRQs\n");
|
415 | 6af0bf9c | bellard | env->interrupt_request |= CPU_INTERRUPT_HARD; |
416 | 6af0bf9c | bellard | do_raise_exception(EXCP_EXT_INTERRUPT); |
417 | 6af0bf9c | bellard | } else if (!(val & 0x00000001) && (old & 0x00000001)) { |
418 | 6af0bf9c | bellard | env->interrupt_request &= ~CPU_INTERRUPT_HARD; |
419 | 6af0bf9c | bellard | } |
420 | 6af0bf9c | bellard | #endif
|
421 | 6af0bf9c | bellard | rn = "Status";
|
422 | 6af0bf9c | bellard | break;
|
423 | 6af0bf9c | bellard | case 13: |
424 | 6af0bf9c | bellard | val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300); |
425 | 6af0bf9c | bellard | old = env->CP0_Cause; |
426 | 6af0bf9c | bellard | env->CP0_Cause = val; |
427 | 6af0bf9c | bellard | #if 0
|
428 | e37e863f | bellard | {
|
429 | e37e863f | bellard | int i;
|
430 | e37e863f | bellard | /* Check if we ever asserted a software IRQ */
|
431 | e37e863f | bellard | for (i = 0; i < 2; i++) {
|
432 | e37e863f | bellard | mask = 0x100 << i;
|
433 | e37e863f | bellard | if ((val & mask) & !(old & mask))
|
434 | e37e863f | bellard | mips_set_irq(i);
|
435 | e37e863f | bellard | }
|
436 | 6af0bf9c | bellard | }
|
437 | 6af0bf9c | bellard | #endif
|
438 | 6af0bf9c | bellard | rn = "Cause";
|
439 | 6af0bf9c | bellard | break;
|
440 | 6af0bf9c | bellard | case 14: |
441 | 6af0bf9c | bellard | val = T0; |
442 | 6af0bf9c | bellard | old = env->CP0_EPC; |
443 | 6af0bf9c | bellard | env->CP0_EPC = val; |
444 | 6af0bf9c | bellard | rn = "EPC";
|
445 | 6af0bf9c | bellard | break;
|
446 | 6af0bf9c | bellard | case 16: |
447 | 6af0bf9c | bellard | switch (sel) {
|
448 | 6af0bf9c | bellard | case 0: |
449 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
|
450 | 6af0bf9c | bellard | val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001); |
451 | 6af0bf9c | bellard | #else
|
452 | 6af0bf9c | bellard | val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001); |
453 | 6af0bf9c | bellard | #endif
|
454 | 6af0bf9c | bellard | old = env->CP0_Config0; |
455 | 6af0bf9c | bellard | env->CP0_Config0 = val; |
456 | 6af0bf9c | bellard | rn = "Config0";
|
457 | 6af0bf9c | bellard | break;
|
458 | 6af0bf9c | bellard | default:
|
459 | 6af0bf9c | bellard | val = -1;
|
460 | 6af0bf9c | bellard | old = -1;
|
461 | 6af0bf9c | bellard | rn = "bad config selector";
|
462 | 6af0bf9c | bellard | break;
|
463 | 6af0bf9c | bellard | } |
464 | 6af0bf9c | bellard | break;
|
465 | 6af0bf9c | bellard | case 18: |
466 | 6af0bf9c | bellard | val = T0; |
467 | 6af0bf9c | bellard | old = env->CP0_WatchLo; |
468 | 6af0bf9c | bellard | env->CP0_WatchLo = val; |
469 | 6af0bf9c | bellard | rn = "WatchLo";
|
470 | 6af0bf9c | bellard | break;
|
471 | 6af0bf9c | bellard | case 19: |
472 | 6af0bf9c | bellard | val = T0 & 0x40FF0FF8;
|
473 | 6af0bf9c | bellard | old = env->CP0_WatchHi; |
474 | 6af0bf9c | bellard | env->CP0_WatchHi = val; |
475 | 6af0bf9c | bellard | rn = "WatchHi";
|
476 | 6af0bf9c | bellard | break;
|
477 | 6af0bf9c | bellard | case 23: |
478 | 6af0bf9c | bellard | val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
479 | 6af0bf9c | bellard | if (T0 & (1 << CP0DB_DM)) |
480 | 6af0bf9c | bellard | env->hflags |= MIPS_HFLAG_DM; |
481 | 6af0bf9c | bellard | else
|
482 | 6af0bf9c | bellard | env->hflags &= ~MIPS_HFLAG_DM; |
483 | 6af0bf9c | bellard | old = env->CP0_Debug; |
484 | 6af0bf9c | bellard | env->CP0_Debug = val; |
485 | 6af0bf9c | bellard | rn = "Debug";
|
486 | 6af0bf9c | bellard | break;
|
487 | 6af0bf9c | bellard | case 24: |
488 | 6af0bf9c | bellard | val = T0; |
489 | 6af0bf9c | bellard | old = env->CP0_DEPC; |
490 | 6af0bf9c | bellard | env->CP0_DEPC = val; |
491 | 6af0bf9c | bellard | rn = "DEPC";
|
492 | 6af0bf9c | bellard | break;
|
493 | 6af0bf9c | bellard | case 28: |
494 | 6af0bf9c | bellard | switch (sel) {
|
495 | 6af0bf9c | bellard | case 0: |
496 | 6af0bf9c | bellard | val = T0 & 0xFFFFFCF6;
|
497 | 6af0bf9c | bellard | old = env->CP0_TagLo; |
498 | 6af0bf9c | bellard | env->CP0_TagLo = val; |
499 | 6af0bf9c | bellard | rn = "TagLo";
|
500 | 6af0bf9c | bellard | break;
|
501 | 6af0bf9c | bellard | default:
|
502 | 6af0bf9c | bellard | val = -1;
|
503 | 6af0bf9c | bellard | old = -1;
|
504 | 6af0bf9c | bellard | rn = "invalid sel";
|
505 | 6af0bf9c | bellard | break;
|
506 | 6af0bf9c | bellard | } |
507 | 6af0bf9c | bellard | break;
|
508 | 6af0bf9c | bellard | case 30: |
509 | 6af0bf9c | bellard | val = T0; |
510 | 6af0bf9c | bellard | old = env->CP0_ErrorEPC; |
511 | 6af0bf9c | bellard | env->CP0_ErrorEPC = val; |
512 | 6af0bf9c | bellard | rn = "EPC";
|
513 | 6af0bf9c | bellard | break;
|
514 | 6af0bf9c | bellard | case 31: |
515 | 6af0bf9c | bellard | val = T0; |
516 | 6af0bf9c | bellard | old = env->CP0_DESAVE; |
517 | 6af0bf9c | bellard | env->CP0_DESAVE = val; |
518 | 6af0bf9c | bellard | rn = "DESAVE";
|
519 | 6af0bf9c | bellard | break;
|
520 | 6af0bf9c | bellard | default:
|
521 | 6af0bf9c | bellard | val = -1;
|
522 | 6af0bf9c | bellard | old = -1;
|
523 | 6af0bf9c | bellard | rn = "unknown";
|
524 | 6af0bf9c | bellard | break;
|
525 | 6af0bf9c | bellard | } |
526 | 6af0bf9c | bellard | print:
|
527 | 6af0bf9c | bellard | #if defined MIPS_DEBUG_DISAS
|
528 | 6af0bf9c | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
529 | 6af0bf9c | bellard | fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
|
530 | 6af0bf9c | bellard | env->PC, rn, T0, val, reg, sel, old); |
531 | 6af0bf9c | bellard | } |
532 | 6af0bf9c | bellard | #endif
|
533 | 6af0bf9c | bellard | return;
|
534 | 6af0bf9c | bellard | } |
535 | 6af0bf9c | bellard | |
536 | 6af0bf9c | bellard | /* TLB management */
|
537 | 6af0bf9c | bellard | #if defined(MIPS_USES_R4K_TLB)
|
538 | 6af0bf9c | bellard | static void invalidate_tb (int idx) |
539 | 6af0bf9c | bellard | { |
540 | 6af0bf9c | bellard | tlb_t *tlb; |
541 | 6af0bf9c | bellard | target_ulong addr, end; |
542 | 6af0bf9c | bellard | |
543 | 6af0bf9c | bellard | tlb = &env->tlb[idx]; |
544 | 6af0bf9c | bellard | if (tlb->V[0]) { |
545 | 6af0bf9c | bellard | addr = tlb->PFN[0];
|
546 | 6af0bf9c | bellard | end = addr + (tlb->end - tlb->VPN); |
547 | 6af0bf9c | bellard | tb_invalidate_page_range(addr, end); |
548 | 4ad40f36 | bellard | /* FIXME: Might be faster to just invalidate the whole "tlb" here
|
549 | 4ad40f36 | bellard | and refill it on demand from our simulated TLB. */
|
550 | 4ad40f36 | bellard | addr = tlb->VPN; |
551 | 4ad40f36 | bellard | while (addr < tlb->end) {
|
552 | 4ad40f36 | bellard | tlb_flush_page (env, addr); |
553 | 4ad40f36 | bellard | addr += TARGET_PAGE_SIZE; |
554 | 4ad40f36 | bellard | } |
555 | 6af0bf9c | bellard | } |
556 | 6af0bf9c | bellard | if (tlb->V[1]) { |
557 | 6af0bf9c | bellard | addr = tlb->PFN[1];
|
558 | 6af0bf9c | bellard | end = addr + (tlb->end - tlb->VPN); |
559 | 6af0bf9c | bellard | tb_invalidate_page_range(addr, end); |
560 | 4ad40f36 | bellard | /* FIXME: Might be faster to just invalidate the whole "tlb" here
|
561 | 4ad40f36 | bellard | and refill it on demand from our simulated TLB. */
|
562 | 4ad40f36 | bellard | addr = tlb->end; |
563 | 4ad40f36 | bellard | while (addr < tlb->end2) {
|
564 | 4ad40f36 | bellard | tlb_flush_page (env, addr); |
565 | 4ad40f36 | bellard | addr += TARGET_PAGE_SIZE; |
566 | 4ad40f36 | bellard | } |
567 | 6af0bf9c | bellard | } |
568 | 6af0bf9c | bellard | } |
569 | 6af0bf9c | bellard | |
570 | 6af0bf9c | bellard | static void fill_tb (int idx) |
571 | 6af0bf9c | bellard | { |
572 | 6af0bf9c | bellard | tlb_t *tlb; |
573 | 6af0bf9c | bellard | int size;
|
574 | 6af0bf9c | bellard | |
575 | 6af0bf9c | bellard | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
|
576 | 6af0bf9c | bellard | tlb = &env->tlb[idx]; |
577 | 6af0bf9c | bellard | tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
|
578 | 6af0bf9c | bellard | tlb->ASID = env->CP0_EntryHi & 0x000000FF;
|
579 | 6af0bf9c | bellard | size = env->CP0_PageMask >> 13;
|
580 | 6af0bf9c | bellard | size = 4 * (size + 1); |
581 | 6af0bf9c | bellard | tlb->end = tlb->VPN + (1 << (8 + size)); |
582 | 4ad40f36 | bellard | tlb->end2 = tlb->end + (1 << (8 + size)); |
583 | 6af0bf9c | bellard | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
|
584 | 6af0bf9c | bellard | tlb->V[0] = env->CP0_EntryLo0 & 2; |
585 | 6af0bf9c | bellard | tlb->D[0] = env->CP0_EntryLo0 & 4; |
586 | 6af0bf9c | bellard | tlb->C[0] = (env->CP0_EntryLo0 >> 3) & 0x7; |
587 | 6af0bf9c | bellard | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
588 | 6af0bf9c | bellard | tlb->V[1] = env->CP0_EntryLo1 & 2; |
589 | 6af0bf9c | bellard | tlb->D[1] = env->CP0_EntryLo1 & 4; |
590 | 6af0bf9c | bellard | tlb->C[1] = (env->CP0_EntryLo1 >> 3) & 0x7; |
591 | 6af0bf9c | bellard | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
592 | 6af0bf9c | bellard | } |
593 | 6af0bf9c | bellard | |
594 | 6af0bf9c | bellard | void do_tlbwi (void) |
595 | 6af0bf9c | bellard | { |
596 | 7a962d30 | bellard | /* Wildly undefined effects for CP0_index containing a too high value and
|
597 | 7a962d30 | bellard | MIPS_TLB_NB not being a power of two. But so does real silicon. */
|
598 | 7a962d30 | bellard | invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1));
|
599 | 7a962d30 | bellard | fill_tb(env->CP0_index & (MIPS_TLB_NB - 1));
|
600 | 6af0bf9c | bellard | } |
601 | 6af0bf9c | bellard | |
602 | 6af0bf9c | bellard | void do_tlbwr (void) |
603 | 6af0bf9c | bellard | { |
604 | 6af0bf9c | bellard | int r = cpu_mips_get_random(env);
|
605 | 6af0bf9c | bellard | |
606 | 6af0bf9c | bellard | invalidate_tb(r); |
607 | 6af0bf9c | bellard | fill_tb(r); |
608 | 6af0bf9c | bellard | } |
609 | 6af0bf9c | bellard | |
610 | 6af0bf9c | bellard | void do_tlbp (void) |
611 | 6af0bf9c | bellard | { |
612 | 6af0bf9c | bellard | tlb_t *tlb; |
613 | 6af0bf9c | bellard | target_ulong tag; |
614 | 6af0bf9c | bellard | uint8_t ASID; |
615 | 6af0bf9c | bellard | int i;
|
616 | 6af0bf9c | bellard | |
617 | 6af0bf9c | bellard | tag = (env->CP0_EntryHi & 0xFFFFE000);
|
618 | 6af0bf9c | bellard | ASID = env->CP0_EntryHi & 0x000000FF;
|
619 | 7a962d30 | bellard | for (i = 0; i < MIPS_TLB_NB; i++) { |
620 | 6af0bf9c | bellard | tlb = &env->tlb[i]; |
621 | 6af0bf9c | bellard | /* Check ASID, virtual page number & size */
|
622 | 6af0bf9c | bellard | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
623 | 6af0bf9c | bellard | /* TLB match */
|
624 | 6af0bf9c | bellard | env->CP0_index = i; |
625 | 6af0bf9c | bellard | break;
|
626 | 6af0bf9c | bellard | } |
627 | 6af0bf9c | bellard | } |
628 | 7a962d30 | bellard | if (i == MIPS_TLB_NB) {
|
629 | 6af0bf9c | bellard | env->CP0_index |= 0x80000000;
|
630 | 6af0bf9c | bellard | } |
631 | 6af0bf9c | bellard | } |
632 | 6af0bf9c | bellard | |
633 | 6af0bf9c | bellard | void do_tlbr (void) |
634 | 6af0bf9c | bellard | { |
635 | 6af0bf9c | bellard | tlb_t *tlb; |
636 | 6af0bf9c | bellard | int size;
|
637 | 6af0bf9c | bellard | |
638 | 7a962d30 | bellard | tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
|
639 | 4ad40f36 | bellard | |
640 | 4ad40f36 | bellard | /* If this will change the current ASID, flush qemu's TLB. */
|
641 | 4ad40f36 | bellard | /* FIXME: Could avoid flushing things which match global entries... */
|
642 | 4ad40f36 | bellard | if ((env->CP0_EntryHi & 0xFF) != tlb->ASID) |
643 | 4ad40f36 | bellard | tlb_flush (env, 1);
|
644 | 4ad40f36 | bellard | |
645 | 6af0bf9c | bellard | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
646 | 6af0bf9c | bellard | size = (tlb->end - tlb->VPN) >> 12;
|
647 | 6af0bf9c | bellard | env->CP0_PageMask = (size - 1) << 13; |
648 | 6af0bf9c | bellard | env->CP0_EntryLo0 = tlb->V[0] | tlb->D[0] | (tlb->C[0] << 3) | |
649 | 6af0bf9c | bellard | (tlb->PFN[0] >> 6); |
650 | 6af0bf9c | bellard | env->CP0_EntryLo1 = tlb->V[1] | tlb->D[1] | (tlb->C[1] << 3) | |
651 | 6af0bf9c | bellard | (tlb->PFN[1] >> 6); |
652 | 6af0bf9c | bellard | } |
653 | 6af0bf9c | bellard | #endif
|
654 | 6af0bf9c | bellard | |
655 | 048f6b4d | bellard | #endif /* !CONFIG_USER_ONLY */ |
656 | 048f6b4d | bellard | |
657 | 6af0bf9c | bellard | void op_dump_ldst (const unsigned char *func) |
658 | 6af0bf9c | bellard | { |
659 | 6af0bf9c | bellard | if (loglevel)
|
660 | 6af0bf9c | bellard | fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1);
|
661 | 6af0bf9c | bellard | } |
662 | 6af0bf9c | bellard | |
663 | 6af0bf9c | bellard | void dump_sc (void) |
664 | 6af0bf9c | bellard | { |
665 | 6af0bf9c | bellard | if (loglevel) {
|
666 | 6af0bf9c | bellard | fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__,
|
667 | 6af0bf9c | bellard | T1, T0, env->CP0_LLAddr); |
668 | 6af0bf9c | bellard | } |
669 | 6af0bf9c | bellard | } |
670 | 6af0bf9c | bellard | |
671 | 6af0bf9c | bellard | void debug_eret (void) |
672 | 6af0bf9c | bellard | { |
673 | 6af0bf9c | bellard | if (loglevel) {
|
674 | 6af0bf9c | bellard | fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
|
675 | 6af0bf9c | bellard | env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
676 | 6af0bf9c | bellard | env->hflags & MIPS_HFLAG_ERL ? 1 : 0); |
677 | 6af0bf9c | bellard | } |
678 | 6af0bf9c | bellard | } |
679 | 6af0bf9c | bellard | |
680 | 6af0bf9c | bellard | void do_pmon (int function) |
681 | 6af0bf9c | bellard | { |
682 | 6af0bf9c | bellard | function /= 2;
|
683 | 6af0bf9c | bellard | switch (function) {
|
684 | 6af0bf9c | bellard | case 2: /* TODO: char inbyte(int waitflag); */ |
685 | 6af0bf9c | bellard | if (env->gpr[4] == 0) |
686 | 6af0bf9c | bellard | env->gpr[2] = -1; |
687 | 6af0bf9c | bellard | /* Fall through */
|
688 | 6af0bf9c | bellard | case 11: /* TODO: char inbyte (void); */ |
689 | 6af0bf9c | bellard | env->gpr[2] = -1; |
690 | 6af0bf9c | bellard | break;
|
691 | 6af0bf9c | bellard | case 3: |
692 | 6af0bf9c | bellard | case 12: |
693 | 6af0bf9c | bellard | printf("%c", env->gpr[4] & 0xFF); |
694 | 6af0bf9c | bellard | break;
|
695 | 6af0bf9c | bellard | case 17: |
696 | 6af0bf9c | bellard | break;
|
697 | 6af0bf9c | bellard | case 158: |
698 | 6af0bf9c | bellard | { |
699 | 6af0bf9c | bellard | unsigned char *fmt = (void *)env->gpr[4]; |
700 | 6af0bf9c | bellard | printf("%s", fmt);
|
701 | 6af0bf9c | bellard | } |
702 | 6af0bf9c | bellard | break;
|
703 | 6af0bf9c | bellard | } |
704 | 6af0bf9c | bellard | } |
705 | e37e863f | bellard | |
706 | e37e863f | bellard | #if !defined(CONFIG_USER_ONLY)
|
707 | e37e863f | bellard | |
708 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
709 | 4ad40f36 | bellard | |
710 | e37e863f | bellard | #define MMUSUFFIX _mmu
|
711 | 4ad40f36 | bellard | #define ALIGNED_ONLY
|
712 | e37e863f | bellard | |
713 | e37e863f | bellard | #define SHIFT 0 |
714 | e37e863f | bellard | #include "softmmu_template.h" |
715 | e37e863f | bellard | |
716 | e37e863f | bellard | #define SHIFT 1 |
717 | e37e863f | bellard | #include "softmmu_template.h" |
718 | e37e863f | bellard | |
719 | e37e863f | bellard | #define SHIFT 2 |
720 | e37e863f | bellard | #include "softmmu_template.h" |
721 | e37e863f | bellard | |
722 | e37e863f | bellard | #define SHIFT 3 |
723 | e37e863f | bellard | #include "softmmu_template.h" |
724 | e37e863f | bellard | |
725 | 4ad40f36 | bellard | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
726 | 4ad40f36 | bellard | { |
727 | 4ad40f36 | bellard | env->CP0_BadVAddr = addr; |
728 | 4ad40f36 | bellard | do_restore_state (retaddr); |
729 | 4ad40f36 | bellard | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
|
730 | 4ad40f36 | bellard | } |
731 | 4ad40f36 | bellard | |
732 | e37e863f | bellard | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
733 | e37e863f | bellard | { |
734 | e37e863f | bellard | TranslationBlock *tb; |
735 | e37e863f | bellard | CPUState *saved_env; |
736 | e37e863f | bellard | unsigned long pc; |
737 | e37e863f | bellard | int ret;
|
738 | e37e863f | bellard | |
739 | e37e863f | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
740 | e37e863f | bellard | generated code */
|
741 | e37e863f | bellard | saved_env = env; |
742 | e37e863f | bellard | env = cpu_single_env; |
743 | e37e863f | bellard | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
|
744 | e37e863f | bellard | if (ret) {
|
745 | e37e863f | bellard | if (retaddr) {
|
746 | e37e863f | bellard | /* now we have a real cpu fault */
|
747 | e37e863f | bellard | pc = (unsigned long)retaddr; |
748 | e37e863f | bellard | tb = tb_find_pc(pc); |
749 | e37e863f | bellard | if (tb) {
|
750 | e37e863f | bellard | /* the PC is inside the translated code. It means that we have
|
751 | e37e863f | bellard | a virtual CPU fault */
|
752 | e37e863f | bellard | cpu_restore_state(tb, env, pc, NULL);
|
753 | e37e863f | bellard | } |
754 | e37e863f | bellard | } |
755 | e37e863f | bellard | do_raise_exception_err(env->exception_index, env->error_code); |
756 | e37e863f | bellard | } |
757 | e37e863f | bellard | env = saved_env; |
758 | e37e863f | bellard | } |
759 | e37e863f | bellard | |
760 | e37e863f | bellard | #endif |