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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 7a3f1944 | bellard | */
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20 | 7a3f1944 | bellard | |
21 | 7a3f1944 | bellard | #include <stdarg.h> |
22 | 7a3f1944 | bellard | #include <stdlib.h> |
23 | 7a3f1944 | bellard | #include <stdio.h> |
24 | 7a3f1944 | bellard | #include <string.h> |
25 | 7a3f1944 | bellard | #include <inttypes.h> |
26 | 7a3f1944 | bellard | |
27 | 7a3f1944 | bellard | #include "cpu.h" |
28 | 7a3f1944 | bellard | #include "exec-all.h" |
29 | 7a3f1944 | bellard | #include "disas.h" |
30 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
31 | 57fec1fe | bellard | #include "tcg-op.h" |
32 | 7a3f1944 | bellard | |
33 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
34 | a7812ae4 | pbrook | #include "helper.h" |
35 | a7812ae4 | pbrook | |
36 | 7a3f1944 | bellard | #define DEBUG_DISAS
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37 | 7a3f1944 | bellard | |
38 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
39 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
40 | 72cbca10 | bellard | according to jump_pc[T2] */
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41 | 72cbca10 | bellard | |
42 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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43 | a7812ae4 | pbrook | static TCGv_ptr cpu_env, cpu_regwptr;
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44 | 25517f99 | Paul Brook | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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45 | 25517f99 | Paul Brook | static TCGv_i32 cpu_cc_op;
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46 | a7812ae4 | pbrook | static TCGv_i32 cpu_psr;
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47 | a7812ae4 | pbrook | static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
48 | 255e1fcb | blueswir1 | static TCGv cpu_y;
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49 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
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50 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
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51 | 255e1fcb | blueswir1 | #endif
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52 | 42a8aa83 | Richard Henderson | static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;
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53 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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54 | a7812ae4 | pbrook | static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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55 | a7812ae4 | pbrook | static TCGv cpu_gsr;
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56 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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57 | a7812ae4 | pbrook | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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58 | a7812ae4 | pbrook | static TCGv_i32 cpu_softint;
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59 | 255e1fcb | blueswir1 | #else
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60 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
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61 | dc99a3f2 | blueswir1 | #endif
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62 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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63 | a7812ae4 | pbrook | static TCGv cpu_tmp0;
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64 | a7812ae4 | pbrook | static TCGv_i32 cpu_tmp32;
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65 | a7812ae4 | pbrook | static TCGv_i64 cpu_tmp64;
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66 | 714547bb | blueswir1 | /* Floating point registers */
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67 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpr[TARGET_FPREGS];
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68 | 1a2fb1c0 | blueswir1 | |
69 | 1a7ff922 | Paolo Bonzini | static target_ulong gen_opc_npc[OPC_BUF_SIZE];
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70 | 1a7ff922 | Paolo Bonzini | static target_ulong gen_opc_jump_pc[2]; |
71 | 1a7ff922 | Paolo Bonzini | |
72 | 2e70f6ef | pbrook | #include "gen-icount.h" |
73 | 2e70f6ef | pbrook | |
74 | 7a3f1944 | bellard | typedef struct DisasContext { |
75 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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76 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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77 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
78 | cf495bcf | bellard | int is_br;
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79 | e8af50a3 | bellard | int mem_idx;
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80 | a80dde08 | bellard | int fpu_enabled;
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81 | 2cade6a3 | blueswir1 | int address_mask_32bit;
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82 | 060718c1 | Richard Henderson | int singlestep;
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83 | 8393617c | Blue Swirl | uint32_t cc_op; /* current CC operation */
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84 | cf495bcf | bellard | struct TranslationBlock *tb;
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85 | 5578ceab | blueswir1 | sparc_def_t *def; |
86 | 7a3f1944 | bellard | } DisasContext; |
87 | 7a3f1944 | bellard | |
88 | 3475187d | bellard | // This function uses non-native bit order
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89 | dc1a6971 | Blue Swirl | #define GET_FIELD(X, FROM, TO) \
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90 | dc1a6971 | Blue Swirl | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
91 | 7a3f1944 | bellard | |
92 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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93 | dc1a6971 | Blue Swirl | #define GET_FIELD_SP(X, FROM, TO) \
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94 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
95 | 3475187d | bellard | |
96 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
97 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
98 | 3475187d | bellard | |
99 | 3475187d | bellard | #ifdef TARGET_SPARC64
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100 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
101 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
102 | 3475187d | bellard | #else
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103 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
104 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
105 | 3475187d | bellard | #endif
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106 | 3475187d | bellard | |
107 | b158a785 | blueswir1 | #define UA2005_HTRAP_MASK 0xff |
108 | b158a785 | blueswir1 | #define V8_TRAP_MASK 0x7f |
109 | b158a785 | blueswir1 | |
110 | 3475187d | bellard | static int sign_extend(int x, int len) |
111 | 3475187d | bellard | { |
112 | 3475187d | bellard | len = 32 - len;
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113 | 3475187d | bellard | return (x << len) >> len;
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114 | 3475187d | bellard | } |
115 | 3475187d | bellard | |
116 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
117 | 7a3f1944 | bellard | |
118 | ff07ec83 | blueswir1 | /* floating point registers moves */
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119 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
120 | ff07ec83 | blueswir1 | { |
121 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + |
122 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
123 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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124 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
125 | ff07ec83 | blueswir1 | } |
126 | ff07ec83 | blueswir1 | |
127 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
128 | ff07ec83 | blueswir1 | { |
129 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + |
130 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
131 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
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132 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
133 | ff07ec83 | blueswir1 | } |
134 | ff07ec83 | blueswir1 | |
135 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
136 | ff07ec83 | blueswir1 | { |
137 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + |
138 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
139 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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140 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
141 | ff07ec83 | blueswir1 | } |
142 | ff07ec83 | blueswir1 | |
143 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
144 | ff07ec83 | blueswir1 | { |
145 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
146 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
147 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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148 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
149 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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150 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
151 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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152 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
153 | ff07ec83 | blueswir1 | } |
154 | ff07ec83 | blueswir1 | |
155 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
156 | ff07ec83 | blueswir1 | { |
157 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
158 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
159 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
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160 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
161 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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162 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
163 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
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164 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
165 | ff07ec83 | blueswir1 | } |
166 | ff07ec83 | blueswir1 | |
167 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
168 | ff07ec83 | blueswir1 | { |
169 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
170 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
171 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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172 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
173 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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174 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
175 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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176 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
177 | ff07ec83 | blueswir1 | } |
178 | 1f587329 | blueswir1 | |
179 | 81ad8ba2 | blueswir1 | /* moves */
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180 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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181 | 3475187d | bellard | #define supervisor(dc) 0 |
182 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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183 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
184 | 81ad8ba2 | blueswir1 | #endif
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185 | 3475187d | bellard | #else
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186 | 2aae2b8e | Igor V. Kovalenko | #define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
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187 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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188 | 2aae2b8e | Igor V. Kovalenko | #define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
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189 | 6f27aba6 | blueswir1 | #else
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190 | 3475187d | bellard | #endif
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191 | 81ad8ba2 | blueswir1 | #endif
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192 | 81ad8ba2 | blueswir1 | |
193 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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194 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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195 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
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196 | 1a2fb1c0 | blueswir1 | #else
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197 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
198 | 2cade6a3 | blueswir1 | #endif
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199 | 1a2fb1c0 | blueswir1 | #endif
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200 | 3391c818 | blueswir1 | |
201 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
202 | 2cade6a3 | blueswir1 | { |
203 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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204 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
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205 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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206 | 2cade6a3 | blueswir1 | #endif
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207 | 2cade6a3 | blueswir1 | } |
208 | 2cade6a3 | blueswir1 | |
209 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
210 | 81ad8ba2 | blueswir1 | { |
211 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
212 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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213 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
214 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
215 | 1a2fb1c0 | blueswir1 | else {
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216 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
217 | 81ad8ba2 | blueswir1 | } |
218 | 81ad8ba2 | blueswir1 | } |
219 | 81ad8ba2 | blueswir1 | |
220 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
221 | 81ad8ba2 | blueswir1 | { |
222 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
223 | 1a2fb1c0 | blueswir1 | return;
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224 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
225 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
226 | 1a2fb1c0 | blueswir1 | else {
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227 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
228 | 81ad8ba2 | blueswir1 | } |
229 | 81ad8ba2 | blueswir1 | } |
230 | 81ad8ba2 | blueswir1 | |
231 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
232 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
233 | 6e256c93 | bellard | { |
234 | 6e256c93 | bellard | TranslationBlock *tb; |
235 | 6e256c93 | bellard | |
236 | 6e256c93 | bellard | tb = s->tb; |
237 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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238 | 060718c1 | Richard Henderson | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) && |
239 | 060718c1 | Richard Henderson | !s->singlestep) { |
240 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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241 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
242 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
243 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
244 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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245 | 6e256c93 | bellard | } else {
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246 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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247 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
248 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
249 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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250 | 6e256c93 | bellard | } |
251 | 6e256c93 | bellard | } |
252 | 6e256c93 | bellard | |
253 | 19f329ad | blueswir1 | // XXX suboptimal
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254 | a7812ae4 | pbrook | static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) |
255 | 19f329ad | blueswir1 | { |
256 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
257 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
258 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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259 | 19f329ad | blueswir1 | } |
260 | 19f329ad | blueswir1 | |
261 | a7812ae4 | pbrook | static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) |
262 | 19f329ad | blueswir1 | { |
263 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
264 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
265 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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266 | 19f329ad | blueswir1 | } |
267 | 19f329ad | blueswir1 | |
268 | a7812ae4 | pbrook | static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) |
269 | 19f329ad | blueswir1 | { |
270 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
271 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
272 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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273 | 19f329ad | blueswir1 | } |
274 | 19f329ad | blueswir1 | |
275 | a7812ae4 | pbrook | static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) |
276 | 19f329ad | blueswir1 | { |
277 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
278 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
279 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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280 | 19f329ad | blueswir1 | } |
281 | 19f329ad | blueswir1 | |
282 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
283 | dc99a3f2 | blueswir1 | { |
284 | a7812ae4 | pbrook | TCGv r_temp; |
285 | a7812ae4 | pbrook | TCGv_i32 r_const; |
286 | dc99a3f2 | blueswir1 | int l1;
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287 | dc99a3f2 | blueswir1 | |
288 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
289 | dc99a3f2 | blueswir1 | |
290 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
291 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
292 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
293 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
294 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
295 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
296 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
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297 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
298 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
299 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
300 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
301 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
302 | dc99a3f2 | blueswir1 | } |
303 | dc99a3f2 | blueswir1 | |
304 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
305 | dc99a3f2 | blueswir1 | { |
306 | dc99a3f2 | blueswir1 | int l1;
|
307 | a7812ae4 | pbrook | TCGv_i32 r_const; |
308 | dc99a3f2 | blueswir1 | |
309 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
310 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
311 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
312 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
313 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
314 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
315 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
316 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
317 | dc99a3f2 | blueswir1 | } |
318 | dc99a3f2 | blueswir1 | |
319 | 41d72852 | Blue Swirl | static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2) |
320 | 41d72852 | Blue Swirl | { |
321 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
322 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
323 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2); |
324 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
325 | 41d72852 | Blue Swirl | } |
326 | 41d72852 | Blue Swirl | |
327 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
328 | dc99a3f2 | blueswir1 | { |
329 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
330 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
331 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
332 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
333 | 41d72852 | Blue Swirl | } |
334 | 41d72852 | Blue Swirl | |
335 | 70c48285 | Richard Henderson | static TCGv_i32 gen_add32_carry32(void) |
336 | dc99a3f2 | blueswir1 | { |
337 | 70c48285 | Richard Henderson | TCGv_i32 carry_32, cc_src1_32, cc_src2_32; |
338 | 70c48285 | Richard Henderson | |
339 | 70c48285 | Richard Henderson | /* Carry is computed from a previous add: (dst < src) */
|
340 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
341 | 70c48285 | Richard Henderson | cc_src1_32 = tcg_temp_new_i32(); |
342 | 70c48285 | Richard Henderson | cc_src2_32 = tcg_temp_new_i32(); |
343 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_dst); |
344 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src); |
345 | 70c48285 | Richard Henderson | #else
|
346 | 70c48285 | Richard Henderson | cc_src1_32 = cpu_cc_dst; |
347 | 70c48285 | Richard Henderson | cc_src2_32 = cpu_cc_src; |
348 | 70c48285 | Richard Henderson | #endif
|
349 | 70c48285 | Richard Henderson | |
350 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
351 | 70c48285 | Richard Henderson | tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); |
352 | 70c48285 | Richard Henderson | |
353 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
354 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src1_32); |
355 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src2_32); |
356 | 70c48285 | Richard Henderson | #endif
|
357 | 70c48285 | Richard Henderson | |
358 | 70c48285 | Richard Henderson | return carry_32;
|
359 | 41d72852 | Blue Swirl | } |
360 | 41d72852 | Blue Swirl | |
361 | 70c48285 | Richard Henderson | static TCGv_i32 gen_sub32_carry32(void) |
362 | 41d72852 | Blue Swirl | { |
363 | 70c48285 | Richard Henderson | TCGv_i32 carry_32, cc_src1_32, cc_src2_32; |
364 | 70c48285 | Richard Henderson | |
365 | 70c48285 | Richard Henderson | /* Carry is computed from a previous borrow: (src1 < src2) */
|
366 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
367 | 70c48285 | Richard Henderson | cc_src1_32 = tcg_temp_new_i32(); |
368 | 70c48285 | Richard Henderson | cc_src2_32 = tcg_temp_new_i32(); |
369 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src1_32, cpu_cc_src); |
370 | 70c48285 | Richard Henderson | tcg_gen_trunc_i64_i32(cc_src2_32, cpu_cc_src2); |
371 | 70c48285 | Richard Henderson | #else
|
372 | 70c48285 | Richard Henderson | cc_src1_32 = cpu_cc_src; |
373 | 70c48285 | Richard Henderson | cc_src2_32 = cpu_cc_src2; |
374 | 70c48285 | Richard Henderson | #endif
|
375 | 70c48285 | Richard Henderson | |
376 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
377 | 70c48285 | Richard Henderson | tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); |
378 | 70c48285 | Richard Henderson | |
379 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
380 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src1_32); |
381 | 70c48285 | Richard Henderson | tcg_temp_free_i32(cc_src2_32); |
382 | 70c48285 | Richard Henderson | #endif
|
383 | 70c48285 | Richard Henderson | |
384 | 70c48285 | Richard Henderson | return carry_32;
|
385 | 70c48285 | Richard Henderson | } |
386 | 70c48285 | Richard Henderson | |
387 | 70c48285 | Richard Henderson | static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1, |
388 | 70c48285 | Richard Henderson | TCGv src2, int update_cc)
|
389 | 70c48285 | Richard Henderson | { |
390 | 70c48285 | Richard Henderson | TCGv_i32 carry_32; |
391 | 70c48285 | Richard Henderson | TCGv carry; |
392 | 70c48285 | Richard Henderson | |
393 | 70c48285 | Richard Henderson | switch (dc->cc_op) {
|
394 | 70c48285 | Richard Henderson | case CC_OP_DIV:
|
395 | 70c48285 | Richard Henderson | case CC_OP_LOGIC:
|
396 | 70c48285 | Richard Henderson | /* Carry is known to be zero. Fall back to plain ADD. */
|
397 | 70c48285 | Richard Henderson | if (update_cc) {
|
398 | 70c48285 | Richard Henderson | gen_op_add_cc(dst, src1, src2); |
399 | 70c48285 | Richard Henderson | } else {
|
400 | 70c48285 | Richard Henderson | tcg_gen_add_tl(dst, src1, src2); |
401 | 70c48285 | Richard Henderson | } |
402 | 70c48285 | Richard Henderson | return;
|
403 | 70c48285 | Richard Henderson | |
404 | 70c48285 | Richard Henderson | case CC_OP_ADD:
|
405 | 70c48285 | Richard Henderson | case CC_OP_TADD:
|
406 | 70c48285 | Richard Henderson | case CC_OP_TADDTV:
|
407 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
408 | 70c48285 | Richard Henderson | { |
409 | 70c48285 | Richard Henderson | /* For 32-bit hosts, we can re-use the host's hardware carry
|
410 | 70c48285 | Richard Henderson | generation by using an ADD2 opcode. We discard the low
|
411 | 70c48285 | Richard Henderson | part of the output. Ideally we'd combine this operation
|
412 | 70c48285 | Richard Henderson | with the add that generated the carry in the first place. */
|
413 | 70c48285 | Richard Henderson | TCGv dst_low = tcg_temp_new(); |
414 | 70c48285 | Richard Henderson | tcg_gen_op6_i32(INDEX_op_add2_i32, dst_low, dst, |
415 | 70c48285 | Richard Henderson | cpu_cc_src, src1, cpu_cc_src2, src2); |
416 | 70c48285 | Richard Henderson | tcg_temp_free(dst_low); |
417 | 70c48285 | Richard Henderson | goto add_done;
|
418 | 70c48285 | Richard Henderson | } |
419 | 70c48285 | Richard Henderson | #endif
|
420 | 70c48285 | Richard Henderson | carry_32 = gen_add32_carry32(); |
421 | 70c48285 | Richard Henderson | break;
|
422 | 70c48285 | Richard Henderson | |
423 | 70c48285 | Richard Henderson | case CC_OP_SUB:
|
424 | 70c48285 | Richard Henderson | case CC_OP_TSUB:
|
425 | 70c48285 | Richard Henderson | case CC_OP_TSUBTV:
|
426 | 70c48285 | Richard Henderson | carry_32 = gen_sub32_carry32(); |
427 | 70c48285 | Richard Henderson | break;
|
428 | 70c48285 | Richard Henderson | |
429 | 70c48285 | Richard Henderson | default:
|
430 | 70c48285 | Richard Henderson | /* We need external help to produce the carry. */
|
431 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
432 | 70c48285 | Richard Henderson | gen_helper_compute_C_icc(carry_32); |
433 | 70c48285 | Richard Henderson | break;
|
434 | 70c48285 | Richard Henderson | } |
435 | 70c48285 | Richard Henderson | |
436 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
437 | 70c48285 | Richard Henderson | carry = tcg_temp_new(); |
438 | 70c48285 | Richard Henderson | tcg_gen_extu_i32_i64(carry, carry_32); |
439 | 70c48285 | Richard Henderson | #else
|
440 | 70c48285 | Richard Henderson | carry = carry_32; |
441 | 70c48285 | Richard Henderson | #endif
|
442 | 70c48285 | Richard Henderson | |
443 | 70c48285 | Richard Henderson | tcg_gen_add_tl(dst, src1, src2); |
444 | 70c48285 | Richard Henderson | tcg_gen_add_tl(dst, dst, carry); |
445 | 70c48285 | Richard Henderson | |
446 | 70c48285 | Richard Henderson | tcg_temp_free_i32(carry_32); |
447 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
448 | 70c48285 | Richard Henderson | tcg_temp_free(carry); |
449 | 70c48285 | Richard Henderson | #endif
|
450 | 70c48285 | Richard Henderson | |
451 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
452 | 70c48285 | Richard Henderson | add_done:
|
453 | 70c48285 | Richard Henderson | #endif
|
454 | 70c48285 | Richard Henderson | if (update_cc) {
|
455 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src, src1); |
456 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src2, src2); |
457 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_dst, dst); |
458 | 70c48285 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
459 | 70c48285 | Richard Henderson | dc->cc_op = CC_OP_ADDX; |
460 | 70c48285 | Richard Henderson | } |
461 | dc99a3f2 | blueswir1 | } |
462 | dc99a3f2 | blueswir1 | |
463 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
464 | dc99a3f2 | blueswir1 | { |
465 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
466 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
467 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
468 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
469 | dc99a3f2 | blueswir1 | } |
470 | dc99a3f2 | blueswir1 | |
471 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
472 | dc99a3f2 | blueswir1 | { |
473 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
474 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
475 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
476 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
477 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
478 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
479 | dc99a3f2 | blueswir1 | } |
480 | dc99a3f2 | blueswir1 | |
481 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
482 | dc99a3f2 | blueswir1 | { |
483 | a7812ae4 | pbrook | TCGv r_temp; |
484 | a7812ae4 | pbrook | TCGv_i32 r_const; |
485 | dc99a3f2 | blueswir1 | int l1;
|
486 | dc99a3f2 | blueswir1 | |
487 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
488 | dc99a3f2 | blueswir1 | |
489 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
490 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
491 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
492 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
493 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
494 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
495 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
496 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
497 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
498 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
499 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
500 | dc99a3f2 | blueswir1 | } |
501 | dc99a3f2 | blueswir1 | |
502 | d4b0d468 | Blue Swirl | static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc) |
503 | 41d72852 | Blue Swirl | { |
504 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
505 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
506 | 719f66a7 | Blue Swirl | if (src2 == 0) { |
507 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, src1); |
508 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
509 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
510 | 719f66a7 | Blue Swirl | } else {
|
511 | 719f66a7 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2); |
512 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
513 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
514 | 719f66a7 | Blue Swirl | } |
515 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
516 | 41d72852 | Blue Swirl | } |
517 | 41d72852 | Blue Swirl | |
518 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
519 | dc99a3f2 | blueswir1 | { |
520 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
521 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
522 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
523 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
524 | 41d72852 | Blue Swirl | } |
525 | 41d72852 | Blue Swirl | |
526 | 70c48285 | Richard Henderson | static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1, |
527 | 70c48285 | Richard Henderson | TCGv src2, int update_cc)
|
528 | 41d72852 | Blue Swirl | { |
529 | 70c48285 | Richard Henderson | TCGv_i32 carry_32; |
530 | 70c48285 | Richard Henderson | TCGv carry; |
531 | 41d72852 | Blue Swirl | |
532 | 70c48285 | Richard Henderson | switch (dc->cc_op) {
|
533 | 70c48285 | Richard Henderson | case CC_OP_DIV:
|
534 | 70c48285 | Richard Henderson | case CC_OP_LOGIC:
|
535 | 70c48285 | Richard Henderson | /* Carry is known to be zero. Fall back to plain SUB. */
|
536 | 70c48285 | Richard Henderson | if (update_cc) {
|
537 | 70c48285 | Richard Henderson | gen_op_sub_cc(dst, src1, src2); |
538 | 70c48285 | Richard Henderson | } else {
|
539 | 70c48285 | Richard Henderson | tcg_gen_sub_tl(dst, src1, src2); |
540 | 70c48285 | Richard Henderson | } |
541 | 70c48285 | Richard Henderson | return;
|
542 | 70c48285 | Richard Henderson | |
543 | 70c48285 | Richard Henderson | case CC_OP_ADD:
|
544 | 70c48285 | Richard Henderson | case CC_OP_TADD:
|
545 | 70c48285 | Richard Henderson | case CC_OP_TADDTV:
|
546 | 70c48285 | Richard Henderson | carry_32 = gen_add32_carry32(); |
547 | 70c48285 | Richard Henderson | break;
|
548 | 70c48285 | Richard Henderson | |
549 | 70c48285 | Richard Henderson | case CC_OP_SUB:
|
550 | 70c48285 | Richard Henderson | case CC_OP_TSUB:
|
551 | 70c48285 | Richard Henderson | case CC_OP_TSUBTV:
|
552 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
553 | 70c48285 | Richard Henderson | { |
554 | 70c48285 | Richard Henderson | /* For 32-bit hosts, we can re-use the host's hardware carry
|
555 | 70c48285 | Richard Henderson | generation by using a SUB2 opcode. We discard the low
|
556 | 70c48285 | Richard Henderson | part of the output. Ideally we'd combine this operation
|
557 | 70c48285 | Richard Henderson | with the add that generated the carry in the first place. */
|
558 | 70c48285 | Richard Henderson | TCGv dst_low = tcg_temp_new(); |
559 | 70c48285 | Richard Henderson | tcg_gen_op6_i32(INDEX_op_sub2_i32, dst_low, dst, |
560 | 70c48285 | Richard Henderson | cpu_cc_src, src1, cpu_cc_src2, src2); |
561 | 70c48285 | Richard Henderson | tcg_temp_free(dst_low); |
562 | 70c48285 | Richard Henderson | goto sub_done;
|
563 | 70c48285 | Richard Henderson | } |
564 | 70c48285 | Richard Henderson | #endif
|
565 | 70c48285 | Richard Henderson | carry_32 = gen_sub32_carry32(); |
566 | 70c48285 | Richard Henderson | break;
|
567 | 70c48285 | Richard Henderson | |
568 | 70c48285 | Richard Henderson | default:
|
569 | 70c48285 | Richard Henderson | /* We need external help to produce the carry. */
|
570 | 70c48285 | Richard Henderson | carry_32 = tcg_temp_new_i32(); |
571 | 70c48285 | Richard Henderson | gen_helper_compute_C_icc(carry_32); |
572 | 70c48285 | Richard Henderson | break;
|
573 | 70c48285 | Richard Henderson | } |
574 | 70c48285 | Richard Henderson | |
575 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
576 | 70c48285 | Richard Henderson | carry = tcg_temp_new(); |
577 | 70c48285 | Richard Henderson | tcg_gen_extu_i32_i64(carry, carry_32); |
578 | 70c48285 | Richard Henderson | #else
|
579 | 70c48285 | Richard Henderson | carry = carry_32; |
580 | 70c48285 | Richard Henderson | #endif
|
581 | 70c48285 | Richard Henderson | |
582 | 70c48285 | Richard Henderson | tcg_gen_sub_tl(dst, src1, src2); |
583 | 70c48285 | Richard Henderson | tcg_gen_sub_tl(dst, dst, carry); |
584 | 70c48285 | Richard Henderson | |
585 | 70c48285 | Richard Henderson | tcg_temp_free_i32(carry_32); |
586 | 70c48285 | Richard Henderson | #if TARGET_LONG_BITS == 64 |
587 | 70c48285 | Richard Henderson | tcg_temp_free(carry); |
588 | 70c48285 | Richard Henderson | #endif
|
589 | 70c48285 | Richard Henderson | |
590 | 70c48285 | Richard Henderson | #if TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32 |
591 | 70c48285 | Richard Henderson | sub_done:
|
592 | 70c48285 | Richard Henderson | #endif
|
593 | 70c48285 | Richard Henderson | if (update_cc) {
|
594 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src, src1); |
595 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_src2, src2); |
596 | 70c48285 | Richard Henderson | tcg_gen_mov_tl(cpu_cc_dst, dst); |
597 | 70c48285 | Richard Henderson | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
598 | 70c48285 | Richard Henderson | dc->cc_op = CC_OP_SUBX; |
599 | 70c48285 | Richard Henderson | } |
600 | dc99a3f2 | blueswir1 | } |
601 | dc99a3f2 | blueswir1 | |
602 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
603 | dc99a3f2 | blueswir1 | { |
604 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
605 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
606 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
607 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
608 | dc99a3f2 | blueswir1 | } |
609 | dc99a3f2 | blueswir1 | |
610 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
611 | dc99a3f2 | blueswir1 | { |
612 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
613 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
614 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
615 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
616 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
617 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
618 | dc99a3f2 | blueswir1 | } |
619 | dc99a3f2 | blueswir1 | |
620 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
621 | d9bdab86 | blueswir1 | { |
622 | 105a1f04 | blueswir1 | TCGv r_temp; |
623 | 6f551262 | blueswir1 | int l1;
|
624 | d9bdab86 | blueswir1 | |
625 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
626 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
627 | d9bdab86 | blueswir1 | |
628 | d9bdab86 | blueswir1 | /* old op:
|
629 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
630 | d9bdab86 | blueswir1 | T1 = 0;
|
631 | d9bdab86 | blueswir1 | */
|
632 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
633 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
634 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
635 | 105a1f04 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
636 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
637 | 6f551262 | blueswir1 | gen_set_label(l1); |
638 | d9bdab86 | blueswir1 | |
639 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
640 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
641 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
642 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
643 | 255e1fcb | blueswir1 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
|
644 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
|
645 | 5068cbd9 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
646 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
647 | d9bdab86 | blueswir1 | |
648 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
649 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
650 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
651 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
652 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
653 | d9bdab86 | blueswir1 | |
654 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
655 | d9bdab86 | blueswir1 | // src1 = T0;
|
656 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
657 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
658 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
659 | d9bdab86 | blueswir1 | |
660 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
661 | d9bdab86 | blueswir1 | |
662 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
663 | d9bdab86 | blueswir1 | } |
664 | d9bdab86 | blueswir1 | |
665 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
666 | 8879d139 | blueswir1 | { |
667 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
668 | 8879d139 | blueswir1 | |
669 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
670 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
671 | 8879d139 | blueswir1 | |
672 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, src2); |
673 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, src1); |
674 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
675 | 8879d139 | blueswir1 | |
676 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
677 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
678 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
679 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
680 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
681 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
682 | 8879d139 | blueswir1 | #else
|
683 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
684 | 8879d139 | blueswir1 | #endif
|
685 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
686 | 8879d139 | blueswir1 | } |
687 | 8879d139 | blueswir1 | |
688 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
689 | 8879d139 | blueswir1 | { |
690 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
691 | 8879d139 | blueswir1 | |
692 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
693 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
694 | 8879d139 | blueswir1 | |
695 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, src2); |
696 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, src1); |
697 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
698 | 8879d139 | blueswir1 | |
699 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
700 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
701 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
702 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
703 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
704 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
705 | 8879d139 | blueswir1 | #else
|
706 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
707 | 8879d139 | blueswir1 | #endif
|
708 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
709 | 8879d139 | blueswir1 | } |
710 | 8879d139 | blueswir1 | |
711 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
712 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
713 | 1a7b60e7 | blueswir1 | { |
714 | a7812ae4 | pbrook | TCGv_i32 r_const; |
715 | 1a7b60e7 | blueswir1 | int l1;
|
716 | 1a7b60e7 | blueswir1 | |
717 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
718 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
719 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
720 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
721 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
722 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
723 | 1a7b60e7 | blueswir1 | } |
724 | 1a7b60e7 | blueswir1 | |
725 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
726 | 1a7b60e7 | blueswir1 | { |
727 | 1a7b60e7 | blueswir1 | int l1, l2;
|
728 | 1a7b60e7 | blueswir1 | |
729 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
730 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
731 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
732 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
733 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
734 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
735 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
736 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
737 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
738 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
739 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
740 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
741 | 1a7b60e7 | blueswir1 | } |
742 | 1a7b60e7 | blueswir1 | #endif
|
743 | 1a7b60e7 | blueswir1 | |
744 | 19f329ad | blueswir1 | // 1
|
745 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
746 | 19f329ad | blueswir1 | { |
747 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
748 | 19f329ad | blueswir1 | } |
749 | 19f329ad | blueswir1 | |
750 | 19f329ad | blueswir1 | // Z
|
751 | a7812ae4 | pbrook | static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) |
752 | 19f329ad | blueswir1 | { |
753 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
754 | 19f329ad | blueswir1 | } |
755 | 19f329ad | blueswir1 | |
756 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
757 | a7812ae4 | pbrook | static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) |
758 | 19f329ad | blueswir1 | { |
759 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
760 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
761 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
762 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
763 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
764 | 19f329ad | blueswir1 | } |
765 | 19f329ad | blueswir1 | |
766 | 19f329ad | blueswir1 | // N ^ V
|
767 | a7812ae4 | pbrook | static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) |
768 | 19f329ad | blueswir1 | { |
769 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
770 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
771 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
772 | 19f329ad | blueswir1 | } |
773 | 19f329ad | blueswir1 | |
774 | 19f329ad | blueswir1 | // C | Z
|
775 | a7812ae4 | pbrook | static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) |
776 | 19f329ad | blueswir1 | { |
777 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
778 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
779 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
780 | 19f329ad | blueswir1 | } |
781 | 19f329ad | blueswir1 | |
782 | 19f329ad | blueswir1 | // C
|
783 | a7812ae4 | pbrook | static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) |
784 | 19f329ad | blueswir1 | { |
785 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
786 | 19f329ad | blueswir1 | } |
787 | 19f329ad | blueswir1 | |
788 | 19f329ad | blueswir1 | // V
|
789 | a7812ae4 | pbrook | static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) |
790 | 19f329ad | blueswir1 | { |
791 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
792 | 19f329ad | blueswir1 | } |
793 | 19f329ad | blueswir1 | |
794 | 19f329ad | blueswir1 | // 0
|
795 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
796 | 19f329ad | blueswir1 | { |
797 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
798 | 19f329ad | blueswir1 | } |
799 | 19f329ad | blueswir1 | |
800 | 19f329ad | blueswir1 | // N
|
801 | a7812ae4 | pbrook | static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) |
802 | 19f329ad | blueswir1 | { |
803 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
804 | 19f329ad | blueswir1 | } |
805 | 19f329ad | blueswir1 | |
806 | 19f329ad | blueswir1 | // !Z
|
807 | a7812ae4 | pbrook | static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) |
808 | 19f329ad | blueswir1 | { |
809 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
810 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
811 | 19f329ad | blueswir1 | } |
812 | 19f329ad | blueswir1 | |
813 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
814 | a7812ae4 | pbrook | static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) |
815 | 19f329ad | blueswir1 | { |
816 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
817 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
818 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
819 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
820 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
821 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
822 | 19f329ad | blueswir1 | } |
823 | 19f329ad | blueswir1 | |
824 | 19f329ad | blueswir1 | // !(N ^ V)
|
825 | a7812ae4 | pbrook | static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) |
826 | 19f329ad | blueswir1 | { |
827 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
828 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
829 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
830 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
831 | 19f329ad | blueswir1 | } |
832 | 19f329ad | blueswir1 | |
833 | 19f329ad | blueswir1 | // !(C | Z)
|
834 | a7812ae4 | pbrook | static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) |
835 | 19f329ad | blueswir1 | { |
836 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
837 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
838 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
839 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
840 | 19f329ad | blueswir1 | } |
841 | 19f329ad | blueswir1 | |
842 | 19f329ad | blueswir1 | // !C
|
843 | a7812ae4 | pbrook | static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) |
844 | 19f329ad | blueswir1 | { |
845 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
846 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
847 | 19f329ad | blueswir1 | } |
848 | 19f329ad | blueswir1 | |
849 | 19f329ad | blueswir1 | // !N
|
850 | a7812ae4 | pbrook | static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) |
851 | 19f329ad | blueswir1 | { |
852 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
853 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
854 | 19f329ad | blueswir1 | } |
855 | 19f329ad | blueswir1 | |
856 | 19f329ad | blueswir1 | // !V
|
857 | a7812ae4 | pbrook | static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) |
858 | 19f329ad | blueswir1 | { |
859 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
860 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
861 | 19f329ad | blueswir1 | } |
862 | 19f329ad | blueswir1 | |
863 | 19f329ad | blueswir1 | /*
|
864 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
865 | 19f329ad | blueswir1 | 0 =
|
866 | 19f329ad | blueswir1 | 1 <
|
867 | 19f329ad | blueswir1 | 2 >
|
868 | 19f329ad | blueswir1 | 3 unordered
|
869 | 19f329ad | blueswir1 | */
|
870 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
871 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
872 | 19f329ad | blueswir1 | { |
873 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
874 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
875 | 19f329ad | blueswir1 | } |
876 | 19f329ad | blueswir1 | |
877 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
878 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
879 | 19f329ad | blueswir1 | { |
880 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
881 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
882 | 19f329ad | blueswir1 | } |
883 | 19f329ad | blueswir1 | |
884 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
885 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
886 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
887 | 19f329ad | blueswir1 | { |
888 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
889 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
890 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
891 | 19f329ad | blueswir1 | } |
892 | 19f329ad | blueswir1 | |
893 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
894 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
895 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
896 | 19f329ad | blueswir1 | { |
897 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
898 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
899 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
900 | 19f329ad | blueswir1 | } |
901 | 19f329ad | blueswir1 | |
902 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
903 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
904 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
905 | 19f329ad | blueswir1 | { |
906 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
907 | 19f329ad | blueswir1 | } |
908 | 19f329ad | blueswir1 | |
909 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
910 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
911 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
912 | 19f329ad | blueswir1 | { |
913 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
914 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
915 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
916 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
917 | 19f329ad | blueswir1 | } |
918 | 19f329ad | blueswir1 | |
919 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
920 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
921 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
922 | 19f329ad | blueswir1 | { |
923 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
924 | 19f329ad | blueswir1 | } |
925 | 19f329ad | blueswir1 | |
926 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
927 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
928 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
929 | 19f329ad | blueswir1 | { |
930 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
931 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
932 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
933 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
934 | 19f329ad | blueswir1 | } |
935 | 19f329ad | blueswir1 | |
936 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
937 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
938 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
939 | 19f329ad | blueswir1 | { |
940 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
941 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
942 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
943 | 19f329ad | blueswir1 | } |
944 | 19f329ad | blueswir1 | |
945 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
946 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
947 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
948 | 19f329ad | blueswir1 | { |
949 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
950 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
951 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
952 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
953 | 19f329ad | blueswir1 | } |
954 | 19f329ad | blueswir1 | |
955 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
956 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
957 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
958 | 19f329ad | blueswir1 | { |
959 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
960 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
961 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
962 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
963 | 19f329ad | blueswir1 | } |
964 | 19f329ad | blueswir1 | |
965 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
966 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
967 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
968 | 19f329ad | blueswir1 | { |
969 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
970 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
971 | 19f329ad | blueswir1 | } |
972 | 19f329ad | blueswir1 | |
973 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
974 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
975 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
976 | 19f329ad | blueswir1 | { |
977 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
978 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
979 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
980 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
981 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
982 | 19f329ad | blueswir1 | } |
983 | 19f329ad | blueswir1 | |
984 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
985 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
986 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
987 | 19f329ad | blueswir1 | { |
988 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
989 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
990 | 19f329ad | blueswir1 | } |
991 | 19f329ad | blueswir1 | |
992 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
993 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
994 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
995 | 19f329ad | blueswir1 | { |
996 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
997 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
998 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
999 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1000 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1001 | 19f329ad | blueswir1 | } |
1002 | 19f329ad | blueswir1 | |
1003 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
1004 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
1005 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
1006 | 19f329ad | blueswir1 | { |
1007 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
1008 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
1009 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
1010 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
1011 | 19f329ad | blueswir1 | } |
1012 | 19f329ad | blueswir1 | |
1013 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
1014 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1015 | 83469015 | bellard | { |
1016 | 83469015 | bellard | int l1;
|
1017 | 83469015 | bellard | |
1018 | 83469015 | bellard | l1 = gen_new_label(); |
1019 | 83469015 | bellard | |
1020 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1021 | 83469015 | bellard | |
1022 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
1023 | 83469015 | bellard | |
1024 | 83469015 | bellard | gen_set_label(l1); |
1025 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
1026 | 83469015 | bellard | } |
1027 | 83469015 | bellard | |
1028 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
1029 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
1030 | 83469015 | bellard | { |
1031 | 83469015 | bellard | int l1;
|
1032 | 83469015 | bellard | |
1033 | 83469015 | bellard | l1 = gen_new_label(); |
1034 | 83469015 | bellard | |
1035 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1036 | 83469015 | bellard | |
1037 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
1038 | 83469015 | bellard | |
1039 | 83469015 | bellard | gen_set_label(l1); |
1040 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
1041 | 83469015 | bellard | } |
1042 | 83469015 | bellard | |
1043 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
1044 | 19f329ad | blueswir1 | TCGv r_cond) |
1045 | 83469015 | bellard | { |
1046 | 83469015 | bellard | int l1, l2;
|
1047 | 83469015 | bellard | |
1048 | 83469015 | bellard | l1 = gen_new_label(); |
1049 | 83469015 | bellard | l2 = gen_new_label(); |
1050 | 19f329ad | blueswir1 | |
1051 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1052 | 83469015 | bellard | |
1053 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
1054 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
1055 | 83469015 | bellard | |
1056 | 83469015 | bellard | gen_set_label(l1); |
1057 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
1058 | 83469015 | bellard | gen_set_label(l2); |
1059 | 83469015 | bellard | } |
1060 | 83469015 | bellard | |
1061 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
1062 | 4af984a7 | blueswir1 | have been set for a jump */
|
1063 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
1064 | 83469015 | bellard | { |
1065 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
1066 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1067 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
1068 | 83469015 | bellard | } |
1069 | 83469015 | bellard | } |
1070 | 83469015 | bellard | |
1071 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
1072 | 72cbca10 | bellard | { |
1073 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
1074 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1075 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
1076 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
1077 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
1078 | 72cbca10 | bellard | } |
1079 | 72cbca10 | bellard | } |
1080 | 72cbca10 | bellard | |
1081 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
1082 | 72cbca10 | bellard | { |
1083 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
1084 | cfa90513 | Blue Swirl | /* flush pending conditional evaluations before exposing cpu state */
|
1085 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
1086 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1087 | cfa90513 | Blue Swirl | gen_helper_compute_psr(); |
1088 | cfa90513 | Blue Swirl | } |
1089 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
1090 | 72cbca10 | bellard | } |
1091 | 72cbca10 | bellard | |
1092 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
1093 | 0bee699e | bellard | { |
1094 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
1095 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
1096 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1097 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1098 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
1099 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1100 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
1101 | 0bee699e | bellard | } else {
|
1102 | 0bee699e | bellard | dc->pc = dc->npc; |
1103 | 0bee699e | bellard | } |
1104 | 0bee699e | bellard | } |
1105 | 0bee699e | bellard | |
1106 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
1107 | 38bc628b | blueswir1 | { |
1108 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1109 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
1110 | 38bc628b | blueswir1 | } |
1111 | 38bc628b | blueswir1 | |
1112 | 8393617c | Blue Swirl | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, |
1113 | 8393617c | Blue Swirl | DisasContext *dc) |
1114 | 19f329ad | blueswir1 | { |
1115 | a7812ae4 | pbrook | TCGv_i32 r_src; |
1116 | 3475187d | bellard | |
1117 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1118 | 19f329ad | blueswir1 | if (cc)
|
1119 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
1120 | 19f329ad | blueswir1 | else
|
1121 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1122 | 3475187d | bellard | #else
|
1123 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
1124 | 3475187d | bellard | #endif
|
1125 | 8393617c | Blue Swirl | switch (dc->cc_op) {
|
1126 | 8393617c | Blue Swirl | case CC_OP_FLAGS:
|
1127 | 8393617c | Blue Swirl | break;
|
1128 | 8393617c | Blue Swirl | default:
|
1129 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1130 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1131 | 8393617c | Blue Swirl | break;
|
1132 | 8393617c | Blue Swirl | } |
1133 | 19f329ad | blueswir1 | switch (cond) {
|
1134 | 19f329ad | blueswir1 | case 0x0: |
1135 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1136 | 19f329ad | blueswir1 | break;
|
1137 | 19f329ad | blueswir1 | case 0x1: |
1138 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
1139 | 19f329ad | blueswir1 | break;
|
1140 | 19f329ad | blueswir1 | case 0x2: |
1141 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
1142 | 19f329ad | blueswir1 | break;
|
1143 | 19f329ad | blueswir1 | case 0x3: |
1144 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
1145 | 19f329ad | blueswir1 | break;
|
1146 | 19f329ad | blueswir1 | case 0x4: |
1147 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
1148 | 19f329ad | blueswir1 | break;
|
1149 | 19f329ad | blueswir1 | case 0x5: |
1150 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
1151 | 19f329ad | blueswir1 | break;
|
1152 | 19f329ad | blueswir1 | case 0x6: |
1153 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
1154 | 19f329ad | blueswir1 | break;
|
1155 | 19f329ad | blueswir1 | case 0x7: |
1156 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
1157 | 19f329ad | blueswir1 | break;
|
1158 | 19f329ad | blueswir1 | case 0x8: |
1159 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1160 | 19f329ad | blueswir1 | break;
|
1161 | 19f329ad | blueswir1 | case 0x9: |
1162 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
1163 | 19f329ad | blueswir1 | break;
|
1164 | 19f329ad | blueswir1 | case 0xa: |
1165 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1166 | 19f329ad | blueswir1 | break;
|
1167 | 19f329ad | blueswir1 | case 0xb: |
1168 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1169 | 19f329ad | blueswir1 | break;
|
1170 | 19f329ad | blueswir1 | case 0xc: |
1171 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1172 | 19f329ad | blueswir1 | break;
|
1173 | 19f329ad | blueswir1 | case 0xd: |
1174 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1175 | 19f329ad | blueswir1 | break;
|
1176 | 19f329ad | blueswir1 | case 0xe: |
1177 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1178 | 19f329ad | blueswir1 | break;
|
1179 | 19f329ad | blueswir1 | case 0xf: |
1180 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1181 | 19f329ad | blueswir1 | break;
|
1182 | 19f329ad | blueswir1 | } |
1183 | 19f329ad | blueswir1 | } |
1184 | 7a3f1944 | bellard | |
1185 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1186 | e8af50a3 | bellard | { |
1187 | 19f329ad | blueswir1 | unsigned int offset; |
1188 | 19f329ad | blueswir1 | |
1189 | 19f329ad | blueswir1 | switch (cc) {
|
1190 | 19f329ad | blueswir1 | default:
|
1191 | 19f329ad | blueswir1 | case 0x0: |
1192 | 19f329ad | blueswir1 | offset = 0;
|
1193 | 19f329ad | blueswir1 | break;
|
1194 | 19f329ad | blueswir1 | case 0x1: |
1195 | 19f329ad | blueswir1 | offset = 32 - 10; |
1196 | 19f329ad | blueswir1 | break;
|
1197 | 19f329ad | blueswir1 | case 0x2: |
1198 | 19f329ad | blueswir1 | offset = 34 - 10; |
1199 | 19f329ad | blueswir1 | break;
|
1200 | 19f329ad | blueswir1 | case 0x3: |
1201 | 19f329ad | blueswir1 | offset = 36 - 10; |
1202 | 19f329ad | blueswir1 | break;
|
1203 | 19f329ad | blueswir1 | } |
1204 | 19f329ad | blueswir1 | |
1205 | 19f329ad | blueswir1 | switch (cond) {
|
1206 | 19f329ad | blueswir1 | case 0x0: |
1207 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1208 | 19f329ad | blueswir1 | break;
|
1209 | 19f329ad | blueswir1 | case 0x1: |
1210 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1211 | 19f329ad | blueswir1 | break;
|
1212 | 19f329ad | blueswir1 | case 0x2: |
1213 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1214 | 19f329ad | blueswir1 | break;
|
1215 | 19f329ad | blueswir1 | case 0x3: |
1216 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1217 | 19f329ad | blueswir1 | break;
|
1218 | 19f329ad | blueswir1 | case 0x4: |
1219 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1220 | 19f329ad | blueswir1 | break;
|
1221 | 19f329ad | blueswir1 | case 0x5: |
1222 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1223 | 19f329ad | blueswir1 | break;
|
1224 | 19f329ad | blueswir1 | case 0x6: |
1225 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1226 | 19f329ad | blueswir1 | break;
|
1227 | 19f329ad | blueswir1 | case 0x7: |
1228 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1229 | 19f329ad | blueswir1 | break;
|
1230 | 19f329ad | blueswir1 | case 0x8: |
1231 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1232 | 19f329ad | blueswir1 | break;
|
1233 | 19f329ad | blueswir1 | case 0x9: |
1234 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1235 | 19f329ad | blueswir1 | break;
|
1236 | 19f329ad | blueswir1 | case 0xa: |
1237 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1238 | 19f329ad | blueswir1 | break;
|
1239 | 19f329ad | blueswir1 | case 0xb: |
1240 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1241 | 19f329ad | blueswir1 | break;
|
1242 | 19f329ad | blueswir1 | case 0xc: |
1243 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1244 | 19f329ad | blueswir1 | break;
|
1245 | 19f329ad | blueswir1 | case 0xd: |
1246 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1247 | 19f329ad | blueswir1 | break;
|
1248 | 19f329ad | blueswir1 | case 0xe: |
1249 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1250 | 19f329ad | blueswir1 | break;
|
1251 | 19f329ad | blueswir1 | case 0xf: |
1252 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1253 | 19f329ad | blueswir1 | break;
|
1254 | 19f329ad | blueswir1 | } |
1255 | e8af50a3 | bellard | } |
1256 | 00f219bf | blueswir1 | |
1257 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1258 | 00f219bf | blueswir1 | // Inverted logic
|
1259 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1260 | 00f219bf | blueswir1 | -1,
|
1261 | 00f219bf | blueswir1 | TCG_COND_NE, |
1262 | 00f219bf | blueswir1 | TCG_COND_GT, |
1263 | 00f219bf | blueswir1 | TCG_COND_GE, |
1264 | 00f219bf | blueswir1 | -1,
|
1265 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1266 | 00f219bf | blueswir1 | TCG_COND_LE, |
1267 | 00f219bf | blueswir1 | TCG_COND_LT, |
1268 | 00f219bf | blueswir1 | }; |
1269 | 19f329ad | blueswir1 | |
1270 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1271 | 19f329ad | blueswir1 | { |
1272 | 19f329ad | blueswir1 | int l1;
|
1273 | 19f329ad | blueswir1 | |
1274 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1275 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1276 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1277 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1278 | 19f329ad | blueswir1 | gen_set_label(l1); |
1279 | 19f329ad | blueswir1 | } |
1280 | 3475187d | bellard | #endif
|
1281 | cf495bcf | bellard | |
1282 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1283 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1284 | 4af984a7 | blueswir1 | TCGv r_cond) |
1285 | 7a3f1944 | bellard | { |
1286 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1287 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1288 | 5fafdf24 | ths | |
1289 | cf495bcf | bellard | if (cond == 0x0) { |
1290 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1291 | 0f8a249a | blueswir1 | if (a) {
|
1292 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1293 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1294 | 0f8a249a | blueswir1 | } else {
|
1295 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1296 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1297 | 0f8a249a | blueswir1 | } |
1298 | cf495bcf | bellard | } else if (cond == 0x8) { |
1299 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1300 | 0f8a249a | blueswir1 | if (a) {
|
1301 | 0f8a249a | blueswir1 | dc->pc = target; |
1302 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1303 | 0f8a249a | blueswir1 | } else {
|
1304 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1305 | 0f8a249a | blueswir1 | dc->npc = target; |
1306 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1307 | 0f8a249a | blueswir1 | } |
1308 | cf495bcf | bellard | } else {
|
1309 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1310 | 8393617c | Blue Swirl | gen_cond(r_cond, cc, cond, dc); |
1311 | 0f8a249a | blueswir1 | if (a) {
|
1312 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1313 | cf495bcf | bellard | dc->is_br = 1;
|
1314 | 0f8a249a | blueswir1 | } else {
|
1315 | cf495bcf | bellard | dc->pc = dc->npc; |
1316 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1317 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1318 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1319 | 0f8a249a | blueswir1 | } |
1320 | cf495bcf | bellard | } |
1321 | 7a3f1944 | bellard | } |
1322 | 7a3f1944 | bellard | |
1323 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1324 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1325 | 4af984a7 | blueswir1 | TCGv r_cond) |
1326 | e8af50a3 | bellard | { |
1327 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1328 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1329 | af7bf89b | bellard | |
1330 | e8af50a3 | bellard | if (cond == 0x0) { |
1331 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1332 | 0f8a249a | blueswir1 | if (a) {
|
1333 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1334 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1335 | 0f8a249a | blueswir1 | } else {
|
1336 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1337 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1338 | 0f8a249a | blueswir1 | } |
1339 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1340 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1341 | 0f8a249a | blueswir1 | if (a) {
|
1342 | 0f8a249a | blueswir1 | dc->pc = target; |
1343 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1344 | 0f8a249a | blueswir1 | } else {
|
1345 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1346 | 0f8a249a | blueswir1 | dc->npc = target; |
1347 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1348 | 0f8a249a | blueswir1 | } |
1349 | e8af50a3 | bellard | } else {
|
1350 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1351 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1352 | 0f8a249a | blueswir1 | if (a) {
|
1353 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1354 | e8af50a3 | bellard | dc->is_br = 1;
|
1355 | 0f8a249a | blueswir1 | } else {
|
1356 | e8af50a3 | bellard | dc->pc = dc->npc; |
1357 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1358 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1359 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1360 | 0f8a249a | blueswir1 | } |
1361 | e8af50a3 | bellard | } |
1362 | e8af50a3 | bellard | } |
1363 | e8af50a3 | bellard | |
1364 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1365 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1366 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1367 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1368 | 7a3f1944 | bellard | { |
1369 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1370 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1371 | 3475187d | bellard | |
1372 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1373 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1374 | 3475187d | bellard | if (a) {
|
1375 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1376 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1377 | 3475187d | bellard | } else {
|
1378 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1379 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1380 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1381 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1382 | 3475187d | bellard | } |
1383 | 7a3f1944 | bellard | } |
1384 | 7a3f1944 | bellard | |
1385 | a7812ae4 | pbrook | static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1386 | 7e8c2b6c | blueswir1 | { |
1387 | 714547bb | blueswir1 | switch (fccno) {
|
1388 | 714547bb | blueswir1 | case 0: |
1389 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1390 | 714547bb | blueswir1 | break;
|
1391 | 714547bb | blueswir1 | case 1: |
1392 | a7812ae4 | pbrook | gen_helper_fcmps_fcc1(r_rs1, r_rs2); |
1393 | 714547bb | blueswir1 | break;
|
1394 | 714547bb | blueswir1 | case 2: |
1395 | a7812ae4 | pbrook | gen_helper_fcmps_fcc2(r_rs1, r_rs2); |
1396 | 714547bb | blueswir1 | break;
|
1397 | 714547bb | blueswir1 | case 3: |
1398 | a7812ae4 | pbrook | gen_helper_fcmps_fcc3(r_rs1, r_rs2); |
1399 | 714547bb | blueswir1 | break;
|
1400 | 714547bb | blueswir1 | } |
1401 | 7e8c2b6c | blueswir1 | } |
1402 | 7e8c2b6c | blueswir1 | |
1403 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1404 | 7e8c2b6c | blueswir1 | { |
1405 | a7812ae4 | pbrook | switch (fccno) {
|
1406 | a7812ae4 | pbrook | case 0: |
1407 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1408 | a7812ae4 | pbrook | break;
|
1409 | a7812ae4 | pbrook | case 1: |
1410 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc1(); |
1411 | a7812ae4 | pbrook | break;
|
1412 | a7812ae4 | pbrook | case 2: |
1413 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc2(); |
1414 | a7812ae4 | pbrook | break;
|
1415 | a7812ae4 | pbrook | case 3: |
1416 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc3(); |
1417 | a7812ae4 | pbrook | break;
|
1418 | a7812ae4 | pbrook | } |
1419 | 7e8c2b6c | blueswir1 | } |
1420 | 7e8c2b6c | blueswir1 | |
1421 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1422 | 7e8c2b6c | blueswir1 | { |
1423 | a7812ae4 | pbrook | switch (fccno) {
|
1424 | a7812ae4 | pbrook | case 0: |
1425 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1426 | a7812ae4 | pbrook | break;
|
1427 | a7812ae4 | pbrook | case 1: |
1428 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc1(); |
1429 | a7812ae4 | pbrook | break;
|
1430 | a7812ae4 | pbrook | case 2: |
1431 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc2(); |
1432 | a7812ae4 | pbrook | break;
|
1433 | a7812ae4 | pbrook | case 3: |
1434 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc3(); |
1435 | a7812ae4 | pbrook | break;
|
1436 | a7812ae4 | pbrook | } |
1437 | 7e8c2b6c | blueswir1 | } |
1438 | 7e8c2b6c | blueswir1 | |
1439 | a7812ae4 | pbrook | static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1440 | 7e8c2b6c | blueswir1 | { |
1441 | 714547bb | blueswir1 | switch (fccno) {
|
1442 | 714547bb | blueswir1 | case 0: |
1443 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1444 | 714547bb | blueswir1 | break;
|
1445 | 714547bb | blueswir1 | case 1: |
1446 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc1(r_rs1, r_rs2); |
1447 | 714547bb | blueswir1 | break;
|
1448 | 714547bb | blueswir1 | case 2: |
1449 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc2(r_rs1, r_rs2); |
1450 | 714547bb | blueswir1 | break;
|
1451 | 714547bb | blueswir1 | case 3: |
1452 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc3(r_rs1, r_rs2); |
1453 | 714547bb | blueswir1 | break;
|
1454 | 714547bb | blueswir1 | } |
1455 | 7e8c2b6c | blueswir1 | } |
1456 | 7e8c2b6c | blueswir1 | |
1457 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1458 | 7e8c2b6c | blueswir1 | { |
1459 | a7812ae4 | pbrook | switch (fccno) {
|
1460 | a7812ae4 | pbrook | case 0: |
1461 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1462 | a7812ae4 | pbrook | break;
|
1463 | a7812ae4 | pbrook | case 1: |
1464 | a7812ae4 | pbrook | gen_helper_fcmped_fcc1(); |
1465 | a7812ae4 | pbrook | break;
|
1466 | a7812ae4 | pbrook | case 2: |
1467 | a7812ae4 | pbrook | gen_helper_fcmped_fcc2(); |
1468 | a7812ae4 | pbrook | break;
|
1469 | a7812ae4 | pbrook | case 3: |
1470 | a7812ae4 | pbrook | gen_helper_fcmped_fcc3(); |
1471 | a7812ae4 | pbrook | break;
|
1472 | a7812ae4 | pbrook | } |
1473 | 7e8c2b6c | blueswir1 | } |
1474 | 7e8c2b6c | blueswir1 | |
1475 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1476 | 7e8c2b6c | blueswir1 | { |
1477 | a7812ae4 | pbrook | switch (fccno) {
|
1478 | a7812ae4 | pbrook | case 0: |
1479 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1480 | a7812ae4 | pbrook | break;
|
1481 | a7812ae4 | pbrook | case 1: |
1482 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc1(); |
1483 | a7812ae4 | pbrook | break;
|
1484 | a7812ae4 | pbrook | case 2: |
1485 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc2(); |
1486 | a7812ae4 | pbrook | break;
|
1487 | a7812ae4 | pbrook | case 3: |
1488 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc3(); |
1489 | a7812ae4 | pbrook | break;
|
1490 | a7812ae4 | pbrook | } |
1491 | 7e8c2b6c | blueswir1 | } |
1492 | 7e8c2b6c | blueswir1 | |
1493 | 7e8c2b6c | blueswir1 | #else
|
1494 | 7e8c2b6c | blueswir1 | |
1495 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1496 | 7e8c2b6c | blueswir1 | { |
1497 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1498 | 7e8c2b6c | blueswir1 | } |
1499 | 7e8c2b6c | blueswir1 | |
1500 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1501 | 7e8c2b6c | blueswir1 | { |
1502 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1503 | 7e8c2b6c | blueswir1 | } |
1504 | 7e8c2b6c | blueswir1 | |
1505 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1506 | 7e8c2b6c | blueswir1 | { |
1507 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1508 | 7e8c2b6c | blueswir1 | } |
1509 | 7e8c2b6c | blueswir1 | |
1510 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1511 | 7e8c2b6c | blueswir1 | { |
1512 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1513 | 7e8c2b6c | blueswir1 | } |
1514 | 7e8c2b6c | blueswir1 | |
1515 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1516 | 7e8c2b6c | blueswir1 | { |
1517 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1518 | 7e8c2b6c | blueswir1 | } |
1519 | 7e8c2b6c | blueswir1 | |
1520 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1521 | 7e8c2b6c | blueswir1 | { |
1522 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1523 | 7e8c2b6c | blueswir1 | } |
1524 | 7e8c2b6c | blueswir1 | #endif
|
1525 | 7e8c2b6c | blueswir1 | |
1526 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1527 | 134d77a1 | blueswir1 | { |
1528 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1529 | 2ea815ca | blueswir1 | |
1530 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1531 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1532 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1533 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1534 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1535 | 134d77a1 | blueswir1 | } |
1536 | 134d77a1 | blueswir1 | |
1537 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1538 | a80dde08 | bellard | { |
1539 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1540 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1541 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1542 | 2ea815ca | blueswir1 | |
1543 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1544 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1545 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1546 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1547 | a80dde08 | bellard | dc->is_br = 1;
|
1548 | a80dde08 | bellard | return 1; |
1549 | a80dde08 | bellard | } |
1550 | a80dde08 | bellard | #endif
|
1551 | a80dde08 | bellard | return 0; |
1552 | a80dde08 | bellard | } |
1553 | a80dde08 | bellard | |
1554 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1555 | 7e8c2b6c | blueswir1 | { |
1556 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1557 | 7e8c2b6c | blueswir1 | } |
1558 | 7e8c2b6c | blueswir1 | |
1559 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1560 | 7e8c2b6c | blueswir1 | { |
1561 | a7812ae4 | pbrook | gen_helper_clear_float_exceptions(); |
1562 | 7e8c2b6c | blueswir1 | } |
1563 | 7e8c2b6c | blueswir1 | |
1564 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1565 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1566 | a7812ae4 | pbrook | static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) |
1567 | 1a2fb1c0 | blueswir1 | { |
1568 | 95f9397c | blueswir1 | int asi;
|
1569 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1570 | 1a2fb1c0 | blueswir1 | |
1571 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1572 | a7812ae4 | pbrook | r_asi = tcg_temp_new_i32(); |
1573 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1574 | 1a2fb1c0 | blueswir1 | } else {
|
1575 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1576 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1577 | 1a2fb1c0 | blueswir1 | } |
1578 | 0425bee5 | blueswir1 | return r_asi;
|
1579 | 0425bee5 | blueswir1 | } |
1580 | 0425bee5 | blueswir1 | |
1581 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1582 | 77f193da | blueswir1 | int sign)
|
1583 | 0425bee5 | blueswir1 | { |
1584 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1585 | 0425bee5 | blueswir1 | |
1586 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1587 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1588 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1589 | a7812ae4 | pbrook | gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign); |
1590 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1591 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1592 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1593 | 1a2fb1c0 | blueswir1 | } |
1594 | 1a2fb1c0 | blueswir1 | |
1595 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1596 | 1a2fb1c0 | blueswir1 | { |
1597 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1598 | 1a2fb1c0 | blueswir1 | |
1599 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1600 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1601 | a7812ae4 | pbrook | gen_helper_st_asi(addr, src, r_asi, r_size); |
1602 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1603 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1604 | 1a2fb1c0 | blueswir1 | } |
1605 | 1a2fb1c0 | blueswir1 | |
1606 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1607 | 1a2fb1c0 | blueswir1 | { |
1608 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1609 | 1a2fb1c0 | blueswir1 | |
1610 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1611 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1612 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1613 | a7812ae4 | pbrook | gen_helper_ldf_asi(addr, r_asi, r_size, r_rd); |
1614 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1615 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1616 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1617 | 1a2fb1c0 | blueswir1 | } |
1618 | 1a2fb1c0 | blueswir1 | |
1619 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1620 | 1a2fb1c0 | blueswir1 | { |
1621 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1622 | 1a2fb1c0 | blueswir1 | |
1623 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1624 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1625 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1626 | a7812ae4 | pbrook | gen_helper_stf_asi(addr, r_asi, r_size, r_rd); |
1627 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1628 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1629 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1630 | 1a2fb1c0 | blueswir1 | } |
1631 | 1a2fb1c0 | blueswir1 | |
1632 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1633 | 1a2fb1c0 | blueswir1 | { |
1634 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1635 | 1a2fb1c0 | blueswir1 | |
1636 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1637 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1638 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1639 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1640 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1641 | a7812ae4 | pbrook | gen_helper_st_asi(addr, dst, r_asi, r_size); |
1642 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1643 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1644 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1645 | 1a2fb1c0 | blueswir1 | } |
1646 | 1a2fb1c0 | blueswir1 | |
1647 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1648 | 1a2fb1c0 | blueswir1 | { |
1649 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_rd; |
1650 | 1a2fb1c0 | blueswir1 | |
1651 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1652 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1653 | a7812ae4 | pbrook | gen_helper_ldda_asi(addr, r_asi, r_rd); |
1654 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1655 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1656 | 0425bee5 | blueswir1 | } |
1657 | 0425bee5 | blueswir1 | |
1658 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1659 | 0425bee5 | blueswir1 | { |
1660 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1661 | a7ec4229 | blueswir1 | |
1662 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1663 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1664 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1665 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1666 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1667 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1668 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1669 | 1a2fb1c0 | blueswir1 | } |
1670 | 1a2fb1c0 | blueswir1 | |
1671 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1672 | 77f193da | blueswir1 | int rd)
|
1673 | 1a2fb1c0 | blueswir1 | { |
1674 | a7812ae4 | pbrook | TCGv r_val1; |
1675 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1676 | 1a2fb1c0 | blueswir1 | |
1677 | a7812ae4 | pbrook | r_val1 = tcg_temp_new(); |
1678 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1679 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1680 | a7812ae4 | pbrook | gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi); |
1681 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1682 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1683 | 1a2fb1c0 | blueswir1 | } |
1684 | 1a2fb1c0 | blueswir1 | |
1685 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1686 | 77f193da | blueswir1 | int rd)
|
1687 | 1a2fb1c0 | blueswir1 | { |
1688 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1689 | 1a2fb1c0 | blueswir1 | |
1690 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1691 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1692 | a7812ae4 | pbrook | gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi); |
1693 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1694 | 1a2fb1c0 | blueswir1 | } |
1695 | 1a2fb1c0 | blueswir1 | |
1696 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1697 | 1a2fb1c0 | blueswir1 | |
1698 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1699 | 77f193da | blueswir1 | int sign)
|
1700 | 1a2fb1c0 | blueswir1 | { |
1701 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1702 | 1a2fb1c0 | blueswir1 | |
1703 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1704 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1705 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1706 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1707 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1708 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1709 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1710 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1711 | 1a2fb1c0 | blueswir1 | } |
1712 | 1a2fb1c0 | blueswir1 | |
1713 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1714 | 1a2fb1c0 | blueswir1 | { |
1715 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1716 | 1a2fb1c0 | blueswir1 | |
1717 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1718 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1719 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1720 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1721 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1722 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1723 | 1a2fb1c0 | blueswir1 | } |
1724 | 1a2fb1c0 | blueswir1 | |
1725 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1726 | 1a2fb1c0 | blueswir1 | { |
1727 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1728 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1729 | 1a2fb1c0 | blueswir1 | |
1730 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1731 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1732 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1733 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1734 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1735 | a7812ae4 | pbrook | r_val = tcg_temp_new_i64(); |
1736 | a7812ae4 | pbrook | tcg_gen_extu_tl_i64(r_val, dst); |
1737 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1738 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1739 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1740 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1741 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1742 | 1a2fb1c0 | blueswir1 | } |
1743 | 1a2fb1c0 | blueswir1 | |
1744 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1745 | 1a2fb1c0 | blueswir1 | { |
1746 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1747 | 1a2fb1c0 | blueswir1 | |
1748 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1749 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1750 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1751 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1752 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1753 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1754 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1755 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1756 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1757 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1758 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1759 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1760 | 0425bee5 | blueswir1 | } |
1761 | 0425bee5 | blueswir1 | |
1762 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1763 | 0425bee5 | blueswir1 | { |
1764 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1765 | a7ec4229 | blueswir1 | |
1766 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1767 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1768 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1769 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1770 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1771 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1772 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1773 | 1a2fb1c0 | blueswir1 | } |
1774 | 1a2fb1c0 | blueswir1 | #endif
|
1775 | 1a2fb1c0 | blueswir1 | |
1776 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1777 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1778 | 1a2fb1c0 | blueswir1 | { |
1779 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1780 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1781 | 1a2fb1c0 | blueswir1 | |
1782 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1783 | 1a2fb1c0 | blueswir1 | |
1784 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1785 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1786 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1787 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1788 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1789 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1790 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1791 | 1a2fb1c0 | blueswir1 | } |
1792 | 1a2fb1c0 | blueswir1 | #endif
|
1793 | 1a2fb1c0 | blueswir1 | |
1794 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1795 | 9322a4bf | blueswir1 | { |
1796 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1797 | 9322a4bf | blueswir1 | unsigned int rs1; |
1798 | 9322a4bf | blueswir1 | |
1799 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1800 | 42a8aa83 | Richard Henderson | if (rs1 == 0) { |
1801 | 42a8aa83 | Richard Henderson | tcg_gen_movi_tl(def, 0);
|
1802 | 42a8aa83 | Richard Henderson | } else if (rs1 < 8) { |
1803 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1804 | 42a8aa83 | Richard Henderson | } else {
|
1805 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1806 | 42a8aa83 | Richard Henderson | } |
1807 | 9322a4bf | blueswir1 | return r_rs1;
|
1808 | 9322a4bf | blueswir1 | } |
1809 | 9322a4bf | blueswir1 | |
1810 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1811 | a49d9390 | blueswir1 | { |
1812 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1813 | a49d9390 | blueswir1 | |
1814 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1815 | 42a8aa83 | Richard Henderson | target_long simm = GET_FIELDs(insn, 19, 31); |
1816 | 42a8aa83 | Richard Henderson | tcg_gen_movi_tl(def, simm); |
1817 | a49d9390 | blueswir1 | } else { /* register */ |
1818 | 42a8aa83 | Richard Henderson | unsigned int rs2 = GET_FIELD(insn, 27, 31); |
1819 | 42a8aa83 | Richard Henderson | if (rs2 == 0) { |
1820 | 42a8aa83 | Richard Henderson | tcg_gen_movi_tl(def, 0);
|
1821 | 42a8aa83 | Richard Henderson | } else if (rs2 < 8) { |
1822 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1823 | 42a8aa83 | Richard Henderson | } else {
|
1824 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1825 | 42a8aa83 | Richard Henderson | } |
1826 | a49d9390 | blueswir1 | } |
1827 | a49d9390 | blueswir1 | return r_rs2;
|
1828 | a49d9390 | blueswir1 | } |
1829 | a49d9390 | blueswir1 | |
1830 | 8194f35a | Igor Kovalenko | #ifdef TARGET_SPARC64
|
1831 | 8194f35a | Igor Kovalenko | static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env) |
1832 | 8194f35a | Igor Kovalenko | { |
1833 | b551ec04 | Jay Foad | TCGv_i32 r_tl = tcg_temp_new_i32(); |
1834 | 8194f35a | Igor Kovalenko | |
1835 | 8194f35a | Igor Kovalenko | /* load env->tl into r_tl */
|
1836 | b551ec04 | Jay Foad | tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); |
1837 | 8194f35a | Igor Kovalenko | |
1838 | 8194f35a | Igor Kovalenko | /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
|
1839 | b551ec04 | Jay Foad | tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); |
1840 | 8194f35a | Igor Kovalenko | |
1841 | 8194f35a | Igor Kovalenko | /* calculate offset to current trap state from env->ts, reuse r_tl */
|
1842 | b551ec04 | Jay Foad | tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
|
1843 | 8194f35a | Igor Kovalenko | tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts)); |
1844 | 8194f35a | Igor Kovalenko | |
1845 | 8194f35a | Igor Kovalenko | /* tsptr = env->ts[env->tl & MAXTL_MASK] */
|
1846 | b551ec04 | Jay Foad | { |
1847 | b551ec04 | Jay Foad | TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); |
1848 | b551ec04 | Jay Foad | tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); |
1849 | b551ec04 | Jay Foad | tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); |
1850 | bc57c114 | Stefan Weil | tcg_temp_free_ptr(r_tl_tmp); |
1851 | b551ec04 | Jay Foad | } |
1852 | 8194f35a | Igor Kovalenko | |
1853 | b551ec04 | Jay Foad | tcg_temp_free_i32(r_tl); |
1854 | 8194f35a | Igor Kovalenko | } |
1855 | 8194f35a | Igor Kovalenko | #endif
|
1856 | 8194f35a | Igor Kovalenko | |
1857 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1858 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1859 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1860 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1861 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1862 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1863 | 64a88d5d | blueswir1 | |
1864 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1865 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1866 | cf495bcf | bellard | { |
1867 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1868 | 42a8aa83 | Richard Henderson | TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2; |
1869 | 67526b20 | Blue Swirl | target_long simm; |
1870 | 7a3f1944 | bellard | |
1871 | 8fec2b8c | aliguori | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1872 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1873 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1874 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1875 | 7a3f1944 | bellard | |
1876 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1877 | 6ae20372 | blueswir1 | |
1878 | 42a8aa83 | Richard Henderson | cpu_tmp1 = cpu_src1 = tcg_temp_new(); |
1879 | 42a8aa83 | Richard Henderson | cpu_tmp2 = cpu_src2 = tcg_temp_new(); |
1880 | 6ae20372 | blueswir1 | |
1881 | cf495bcf | bellard | switch (opc) {
|
1882 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1883 | 0f8a249a | blueswir1 | { |
1884 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1885 | 0f8a249a | blueswir1 | int32_t target; |
1886 | 0f8a249a | blueswir1 | switch (xop) {
|
1887 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1888 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1889 | 0f8a249a | blueswir1 | { |
1890 | 0f8a249a | blueswir1 | int cc;
|
1891 | 0f8a249a | blueswir1 | |
1892 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1893 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1894 | 0f8a249a | blueswir1 | target <<= 2;
|
1895 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1896 | 0f8a249a | blueswir1 | if (cc == 0) |
1897 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1898 | 0f8a249a | blueswir1 | else if (cc == 2) |
1899 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
1900 | 0f8a249a | blueswir1 | else
|
1901 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1902 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1903 | 0f8a249a | blueswir1 | } |
1904 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1905 | 0f8a249a | blueswir1 | { |
1906 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1907 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1908 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1909 | 0f8a249a | blueswir1 | target <<= 2;
|
1910 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1911 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
1912 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1913 | 0f8a249a | blueswir1 | } |
1914 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1915 | 0f8a249a | blueswir1 | { |
1916 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1917 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1918 | a80dde08 | bellard | goto jmp_insn;
|
1919 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1920 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1921 | 0f8a249a | blueswir1 | target <<= 2;
|
1922 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
1923 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1924 | 0f8a249a | blueswir1 | } |
1925 | a4d17f19 | blueswir1 | #else
|
1926 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1927 | 0f8a249a | blueswir1 | { |
1928 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1929 | 0f8a249a | blueswir1 | } |
1930 | 0f8a249a | blueswir1 | #endif
|
1931 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1932 | 0f8a249a | blueswir1 | { |
1933 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1934 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1935 | 0f8a249a | blueswir1 | target <<= 2;
|
1936 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1937 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1938 | 0f8a249a | blueswir1 | } |
1939 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1940 | 0f8a249a | blueswir1 | { |
1941 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1942 | a80dde08 | bellard | goto jmp_insn;
|
1943 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1944 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1945 | 0f8a249a | blueswir1 | target <<= 2;
|
1946 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
1947 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1948 | 0f8a249a | blueswir1 | } |
1949 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1950 | 0f8a249a | blueswir1 | if (rd) { // nop |
1951 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1952 | 2ea815ca | blueswir1 | TCGv r_const; |
1953 | 2ea815ca | blueswir1 | |
1954 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
1955 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1956 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1957 | 0f8a249a | blueswir1 | } |
1958 | 0f8a249a | blueswir1 | break;
|
1959 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1960 | 0f8a249a | blueswir1 | default:
|
1961 | 3475187d | bellard | goto illegal_insn;
|
1962 | 0f8a249a | blueswir1 | } |
1963 | 0f8a249a | blueswir1 | break;
|
1964 | 0f8a249a | blueswir1 | } |
1965 | 0f8a249a | blueswir1 | break;
|
1966 | dc1a6971 | Blue Swirl | case 1: /*CALL*/ |
1967 | dc1a6971 | Blue Swirl | { |
1968 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1969 | 2ea815ca | blueswir1 | TCGv r_const; |
1970 | cf495bcf | bellard | |
1971 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1972 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
1973 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1974 | 0f8a249a | blueswir1 | target += dc->pc; |
1975 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
1976 | 0f8a249a | blueswir1 | dc->npc = target; |
1977 | 0f8a249a | blueswir1 | } |
1978 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1979 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
1980 | 0f8a249a | blueswir1 | { |
1981 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
1982 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
1983 | cf495bcf | bellard | int cond;
|
1984 | 3475187d | bellard | |
1985 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1986 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
1987 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
1988 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
1989 | cf495bcf | bellard | } else {
|
1990 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
1991 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
1992 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
1993 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
1994 | 6f551262 | blueswir1 | } else
|
1995 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
1996 | cf495bcf | bellard | } |
1997 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
1998 | cf495bcf | bellard | if (cond == 0x8) { |
1999 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2000 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
2001 | b158a785 | blueswir1 | supervisor(dc)) |
2002 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
2003 | b158a785 | blueswir1 | else
|
2004 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
2005 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
2006 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
2007 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
2008 | af7bf89b | bellard | } else if (cond != 0) { |
2009 | a7812ae4 | pbrook | TCGv r_cond = tcg_temp_new(); |
2010 | b158a785 | blueswir1 | int l1;
|
2011 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2012 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
2013 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
2014 | 748b9d8e | blueswir1 | |
2015 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2016 | 0f8a249a | blueswir1 | if (cc == 0) |
2017 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
2018 | 0f8a249a | blueswir1 | else if (cc == 2) |
2019 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
2020 | 0f8a249a | blueswir1 | else
|
2021 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2022 | 3475187d | bellard | #else
|
2023 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
2024 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
2025 | 3475187d | bellard | #endif
|
2026 | b158a785 | blueswir1 | l1 = gen_new_label(); |
2027 | b158a785 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
2028 | b158a785 | blueswir1 | |
2029 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
2030 | b158a785 | blueswir1 | supervisor(dc)) |
2031 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
2032 | b158a785 | blueswir1 | else
|
2033 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
2034 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
2035 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
2036 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
2037 | b158a785 | blueswir1 | |
2038 | b158a785 | blueswir1 | gen_set_label(l1); |
2039 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
2040 | cf495bcf | bellard | } |
2041 | a80dde08 | bellard | gen_op_next_insn(); |
2042 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2043 | a80dde08 | bellard | dc->is_br = 1;
|
2044 | a80dde08 | bellard | goto jmp_insn;
|
2045 | cf495bcf | bellard | } else if (xop == 0x28) { |
2046 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2047 | cf495bcf | bellard | switch(rs1) {
|
2048 | cf495bcf | bellard | case 0: /* rdy */ |
2049 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
2050 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
2051 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
2052 | 65fe7b09 | blueswir1 | II */
|
2053 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
2054 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
2055 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
2056 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
2057 | 65fe7b09 | blueswir1 | microSPARC II */
|
2058 | 65fe7b09 | blueswir1 | #endif
|
2059 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_y); |
2060 | cf495bcf | bellard | break;
|
2061 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2062 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
2063 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2064 | a7812ae4 | pbrook | gen_helper_rdccr(cpu_dst); |
2065 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2066 | 3475187d | bellard | break;
|
2067 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
2068 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
2069 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2070 | 3475187d | bellard | break;
|
2071 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
2072 | ccd4a219 | blueswir1 | { |
2073 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2074 | ccd4a219 | blueswir1 | |
2075 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2076 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2077 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2078 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
2079 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2080 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2081 | ccd4a219 | blueswir1 | } |
2082 | 3475187d | bellard | break;
|
2083 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
2084 | 2ea815ca | blueswir1 | { |
2085 | 2ea815ca | blueswir1 | TCGv r_const; |
2086 | 2ea815ca | blueswir1 | |
2087 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
2088 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2089 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2090 | 2ea815ca | blueswir1 | } |
2091 | 0f8a249a | blueswir1 | break;
|
2092 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
2093 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
2094 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2095 | 3475187d | bellard | break;
|
2096 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
2097 | 65fe7b09 | blueswir1 | break; /* no effect */ |
2098 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
2099 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2100 | 725cb90b | bellard | goto jmp_insn;
|
2101 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_gsr); |
2102 | 725cb90b | bellard | break;
|
2103 | 9d926598 | blueswir1 | case 0x16: /* Softint */ |
2104 | 9d926598 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); |
2105 | 9d926598 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2106 | 9d926598 | blueswir1 | break;
|
2107 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
2108 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
2109 | 83469015 | bellard | break;
|
2110 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
2111 | ccd4a219 | blueswir1 | { |
2112 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2113 | ccd4a219 | blueswir1 | |
2114 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2115 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2116 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
2117 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
2118 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2119 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2120 | ccd4a219 | blueswir1 | } |
2121 | 83469015 | bellard | break;
|
2122 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
2123 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
2124 | 83469015 | bellard | break;
|
2125 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
2126 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
2127 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
2128 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
2129 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
2130 | 3475187d | bellard | #endif
|
2131 | 3475187d | bellard | default:
|
2132 | cf495bcf | bellard | goto illegal_insn;
|
2133 | cf495bcf | bellard | } |
2134 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
2135 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
2136 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
2137 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2138 | 0f8a249a | blueswir1 | goto priv_insn;
|
2139 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2140 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
2141 | a7812ae4 | pbrook | gen_helper_rdpsr(cpu_dst); |
2142 | e9ebed4d | blueswir1 | #else
|
2143 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2144 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2145 | e9ebed4d | blueswir1 | goto priv_insn;
|
2146 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
2147 | e9ebed4d | blueswir1 | switch (rs1) {
|
2148 | e9ebed4d | blueswir1 | case 0: // hpstate |
2149 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
2150 | e9ebed4d | blueswir1 | break;
|
2151 | e9ebed4d | blueswir1 | case 1: // htstate |
2152 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
2153 | e9ebed4d | blueswir1 | break;
|
2154 | e9ebed4d | blueswir1 | case 3: // hintp |
2155 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
2156 | e9ebed4d | blueswir1 | break;
|
2157 | e9ebed4d | blueswir1 | case 5: // htba |
2158 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
2159 | e9ebed4d | blueswir1 | break;
|
2160 | e9ebed4d | blueswir1 | case 6: // hver |
2161 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
2162 | e9ebed4d | blueswir1 | break;
|
2163 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
2164 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
2165 | e9ebed4d | blueswir1 | break;
|
2166 | e9ebed4d | blueswir1 | default:
|
2167 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2168 | e9ebed4d | blueswir1 | } |
2169 | e9ebed4d | blueswir1 | #endif
|
2170 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2171 | e8af50a3 | bellard | break;
|
2172 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2173 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2174 | 0f8a249a | blueswir1 | goto priv_insn;
|
2175 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2176 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2177 | 0f8a249a | blueswir1 | switch (rs1) {
|
2178 | 0f8a249a | blueswir1 | case 0: // tpc |
2179 | 375ee38b | blueswir1 | { |
2180 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2181 | 375ee38b | blueswir1 | |
2182 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2183 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2184 | a7812ae4 | pbrook | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2185 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2186 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2187 | 375ee38b | blueswir1 | } |
2188 | 0f8a249a | blueswir1 | break;
|
2189 | 0f8a249a | blueswir1 | case 1: // tnpc |
2190 | 375ee38b | blueswir1 | { |
2191 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2192 | 375ee38b | blueswir1 | |
2193 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2194 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2195 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2196 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2197 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2198 | 375ee38b | blueswir1 | } |
2199 | 0f8a249a | blueswir1 | break;
|
2200 | 0f8a249a | blueswir1 | case 2: // tstate |
2201 | 375ee38b | blueswir1 | { |
2202 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2203 | 375ee38b | blueswir1 | |
2204 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2205 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2206 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2207 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2208 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2209 | 375ee38b | blueswir1 | } |
2210 | 0f8a249a | blueswir1 | break;
|
2211 | 0f8a249a | blueswir1 | case 3: // tt |
2212 | 375ee38b | blueswir1 | { |
2213 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2214 | 375ee38b | blueswir1 | |
2215 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2216 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2217 | a7812ae4 | pbrook | tcg_gen_ld_i32(cpu_tmp32, r_tsptr, |
2218 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2219 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2220 | a7812ae4 | pbrook | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2221 | 375ee38b | blueswir1 | } |
2222 | 0f8a249a | blueswir1 | break;
|
2223 | 0f8a249a | blueswir1 | case 4: // tick |
2224 | ccd4a219 | blueswir1 | { |
2225 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2226 | ccd4a219 | blueswir1 | |
2227 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2228 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2229 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2230 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
2231 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2232 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2233 | ccd4a219 | blueswir1 | } |
2234 | 0f8a249a | blueswir1 | break;
|
2235 | 0f8a249a | blueswir1 | case 5: // tba |
2236 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2237 | 0f8a249a | blueswir1 | break;
|
2238 | 0f8a249a | blueswir1 | case 6: // pstate |
2239 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2240 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2241 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2242 | 0f8a249a | blueswir1 | break;
|
2243 | 0f8a249a | blueswir1 | case 7: // tl |
2244 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2245 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2246 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2247 | 0f8a249a | blueswir1 | break;
|
2248 | 0f8a249a | blueswir1 | case 8: // pil |
2249 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2250 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2251 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2252 | 0f8a249a | blueswir1 | break;
|
2253 | 0f8a249a | blueswir1 | case 9: // cwp |
2254 | a7812ae4 | pbrook | gen_helper_rdcwp(cpu_tmp0); |
2255 | 0f8a249a | blueswir1 | break;
|
2256 | 0f8a249a | blueswir1 | case 10: // cansave |
2257 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2258 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2259 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2260 | 0f8a249a | blueswir1 | break;
|
2261 | 0f8a249a | blueswir1 | case 11: // canrestore |
2262 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2263 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2264 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2265 | 0f8a249a | blueswir1 | break;
|
2266 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2267 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2268 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2269 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2270 | 0f8a249a | blueswir1 | break;
|
2271 | 0f8a249a | blueswir1 | case 13: // otherwin |
2272 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2273 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2274 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2275 | 0f8a249a | blueswir1 | break;
|
2276 | 0f8a249a | blueswir1 | case 14: // wstate |
2277 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2278 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2279 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2280 | 0f8a249a | blueswir1 | break;
|
2281 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2282 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2283 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2284 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2285 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2286 | e9ebed4d | blueswir1 | break;
|
2287 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2288 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2289 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2290 | e9ebed4d | blueswir1 | goto priv_insn;
|
2291 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); |
2292 | e9ebed4d | blueswir1 | break;
|
2293 | 0f8a249a | blueswir1 | case 31: // ver |
2294 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2295 | 0f8a249a | blueswir1 | break;
|
2296 | 0f8a249a | blueswir1 | case 15: // fq |
2297 | 0f8a249a | blueswir1 | default:
|
2298 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2299 | 0f8a249a | blueswir1 | } |
2300 | 3475187d | bellard | #else
|
2301 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2302 | 3475187d | bellard | #endif
|
2303 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2304 | e8af50a3 | bellard | break;
|
2305 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2306 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2307 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2308 | a7812ae4 | pbrook | gen_helper_flushw(); |
2309 | 3475187d | bellard | #else
|
2310 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2311 | 0f8a249a | blueswir1 | goto priv_insn;
|
2312 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tbr); |
2313 | 3475187d | bellard | #endif
|
2314 | e8af50a3 | bellard | break;
|
2315 | e8af50a3 | bellard | #endif
|
2316 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2317 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2318 | a80dde08 | bellard | goto jmp_insn;
|
2319 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2320 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2321 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2322 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2323 | cca1d527 | Blue Swirl | save_state(dc, cpu_cond); |
2324 | 0f8a249a | blueswir1 | switch (xop) {
|
2325 | dc1a6971 | Blue Swirl | case 0x1: /* fmovs */ |
2326 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2327 | dc1a6971 | Blue Swirl | break;
|
2328 | dc1a6971 | Blue Swirl | case 0x5: /* fnegs */ |
2329 | dc1a6971 | Blue Swirl | gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
2330 | dc1a6971 | Blue Swirl | break;
|
2331 | dc1a6971 | Blue Swirl | case 0x9: /* fabss */ |
2332 | dc1a6971 | Blue Swirl | gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
2333 | dc1a6971 | Blue Swirl | break;
|
2334 | dc1a6971 | Blue Swirl | case 0x29: /* fsqrts */ |
2335 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2336 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2337 | dc1a6971 | Blue Swirl | gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
2338 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2339 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2340 | dc1a6971 | Blue Swirl | break;
|
2341 | dc1a6971 | Blue Swirl | case 0x2a: /* fsqrtd */ |
2342 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2343 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2344 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2345 | dc1a6971 | Blue Swirl | gen_helper_fsqrtd(); |
2346 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2347 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2348 | dc1a6971 | Blue Swirl | break;
|
2349 | dc1a6971 | Blue Swirl | case 0x2b: /* fsqrtq */ |
2350 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2351 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2352 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2353 | dc1a6971 | Blue Swirl | gen_helper_fsqrtq(); |
2354 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2355 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2356 | dc1a6971 | Blue Swirl | break;
|
2357 | dc1a6971 | Blue Swirl | case 0x41: /* fadds */ |
2358 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2359 | dc1a6971 | Blue Swirl | gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2360 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2361 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2362 | dc1a6971 | Blue Swirl | break;
|
2363 | dc1a6971 | Blue Swirl | case 0x42: /* faddd */ |
2364 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2365 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2366 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2367 | dc1a6971 | Blue Swirl | gen_helper_faddd(); |
2368 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2369 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2370 | dc1a6971 | Blue Swirl | break;
|
2371 | dc1a6971 | Blue Swirl | case 0x43: /* faddq */ |
2372 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2373 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2374 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2375 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2376 | dc1a6971 | Blue Swirl | gen_helper_faddq(); |
2377 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2378 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2379 | dc1a6971 | Blue Swirl | break;
|
2380 | dc1a6971 | Blue Swirl | case 0x45: /* fsubs */ |
2381 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2382 | dc1a6971 | Blue Swirl | gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2383 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2384 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2385 | dc1a6971 | Blue Swirl | break;
|
2386 | dc1a6971 | Blue Swirl | case 0x46: /* fsubd */ |
2387 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2388 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2389 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2390 | dc1a6971 | Blue Swirl | gen_helper_fsubd(); |
2391 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2392 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2393 | dc1a6971 | Blue Swirl | break;
|
2394 | dc1a6971 | Blue Swirl | case 0x47: /* fsubq */ |
2395 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2396 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2397 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2398 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2399 | dc1a6971 | Blue Swirl | gen_helper_fsubq(); |
2400 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2401 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2402 | dc1a6971 | Blue Swirl | break;
|
2403 | dc1a6971 | Blue Swirl | case 0x49: /* fmuls */ |
2404 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2405 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2406 | dc1a6971 | Blue Swirl | gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2407 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2408 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2409 | dc1a6971 | Blue Swirl | break;
|
2410 | dc1a6971 | Blue Swirl | case 0x4a: /* fmuld */ |
2411 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2412 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2413 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2414 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2415 | dc1a6971 | Blue Swirl | gen_helper_fmuld(); |
2416 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2417 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2418 | dc1a6971 | Blue Swirl | break;
|
2419 | dc1a6971 | Blue Swirl | case 0x4b: /* fmulq */ |
2420 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2421 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2422 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2423 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2424 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2425 | dc1a6971 | Blue Swirl | gen_helper_fmulq(); |
2426 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2427 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2428 | dc1a6971 | Blue Swirl | break;
|
2429 | dc1a6971 | Blue Swirl | case 0x4d: /* fdivs */ |
2430 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2431 | dc1a6971 | Blue Swirl | gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2432 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2433 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2434 | dc1a6971 | Blue Swirl | break;
|
2435 | dc1a6971 | Blue Swirl | case 0x4e: /* fdivd */ |
2436 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2437 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2438 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2439 | dc1a6971 | Blue Swirl | gen_helper_fdivd(); |
2440 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2441 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2442 | dc1a6971 | Blue Swirl | break;
|
2443 | dc1a6971 | Blue Swirl | case 0x4f: /* fdivq */ |
2444 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2445 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2446 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2447 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2448 | dc1a6971 | Blue Swirl | gen_helper_fdivq(); |
2449 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2450 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2451 | dc1a6971 | Blue Swirl | break;
|
2452 | dc1a6971 | Blue Swirl | case 0x69: /* fsmuld */ |
2453 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSMULD); |
2454 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2455 | dc1a6971 | Blue Swirl | gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
2456 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2457 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2458 | dc1a6971 | Blue Swirl | break;
|
2459 | dc1a6971 | Blue Swirl | case 0x6e: /* fdmulq */ |
2460 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2461 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2462 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2463 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2464 | dc1a6971 | Blue Swirl | gen_helper_fdmulq(); |
2465 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2466 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2467 | dc1a6971 | Blue Swirl | break;
|
2468 | dc1a6971 | Blue Swirl | case 0xc4: /* fitos */ |
2469 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2470 | dc1a6971 | Blue Swirl | gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
2471 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2472 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2473 | dc1a6971 | Blue Swirl | break;
|
2474 | dc1a6971 | Blue Swirl | case 0xc6: /* fdtos */ |
2475 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2476 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2477 | dc1a6971 | Blue Swirl | gen_helper_fdtos(cpu_tmp32); |
2478 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2479 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2480 | dc1a6971 | Blue Swirl | break;
|
2481 | dc1a6971 | Blue Swirl | case 0xc7: /* fqtos */ |
2482 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2483 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2484 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2485 | dc1a6971 | Blue Swirl | gen_helper_fqtos(cpu_tmp32); |
2486 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2487 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2488 | dc1a6971 | Blue Swirl | break;
|
2489 | dc1a6971 | Blue Swirl | case 0xc8: /* fitod */ |
2490 | dc1a6971 | Blue Swirl | gen_helper_fitod(cpu_fpr[rs2]); |
2491 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2492 | dc1a6971 | Blue Swirl | break;
|
2493 | dc1a6971 | Blue Swirl | case 0xc9: /* fstod */ |
2494 | dc1a6971 | Blue Swirl | gen_helper_fstod(cpu_fpr[rs2]); |
2495 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2496 | dc1a6971 | Blue Swirl | break;
|
2497 | dc1a6971 | Blue Swirl | case 0xcb: /* fqtod */ |
2498 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2499 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2500 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2501 | dc1a6971 | Blue Swirl | gen_helper_fqtod(); |
2502 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2503 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2504 | dc1a6971 | Blue Swirl | break;
|
2505 | dc1a6971 | Blue Swirl | case 0xcc: /* fitoq */ |
2506 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2507 | dc1a6971 | Blue Swirl | gen_helper_fitoq(cpu_fpr[rs2]); |
2508 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2509 | dc1a6971 | Blue Swirl | break;
|
2510 | dc1a6971 | Blue Swirl | case 0xcd: /* fstoq */ |
2511 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2512 | dc1a6971 | Blue Swirl | gen_helper_fstoq(cpu_fpr[rs2]); |
2513 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2514 | dc1a6971 | Blue Swirl | break;
|
2515 | dc1a6971 | Blue Swirl | case 0xce: /* fdtoq */ |
2516 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2517 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2518 | dc1a6971 | Blue Swirl | gen_helper_fdtoq(); |
2519 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2520 | dc1a6971 | Blue Swirl | break;
|
2521 | dc1a6971 | Blue Swirl | case 0xd1: /* fstoi */ |
2522 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2523 | dc1a6971 | Blue Swirl | gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
2524 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2525 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2526 | dc1a6971 | Blue Swirl | break;
|
2527 | dc1a6971 | Blue Swirl | case 0xd2: /* fdtoi */ |
2528 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2529 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2530 | dc1a6971 | Blue Swirl | gen_helper_fdtoi(cpu_tmp32); |
2531 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2532 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2533 | dc1a6971 | Blue Swirl | break;
|
2534 | dc1a6971 | Blue Swirl | case 0xd3: /* fqtoi */ |
2535 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2536 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2537 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2538 | dc1a6971 | Blue Swirl | gen_helper_fqtoi(cpu_tmp32); |
2539 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2540 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2541 | dc1a6971 | Blue Swirl | break;
|
2542 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2543 | dc1a6971 | Blue Swirl | case 0x2: /* V9 fmovd */ |
2544 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2545 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
2546 | dc1a6971 | Blue Swirl | cpu_fpr[DFPREG(rs2) + 1]);
|
2547 | dc1a6971 | Blue Swirl | break;
|
2548 | dc1a6971 | Blue Swirl | case 0x3: /* V9 fmovq */ |
2549 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2550 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2551 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
|
2552 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 1]);
|
2553 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
|
2554 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 2]);
|
2555 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
|
2556 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 3]);
|
2557 | dc1a6971 | Blue Swirl | break;
|
2558 | dc1a6971 | Blue Swirl | case 0x6: /* V9 fnegd */ |
2559 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2560 | dc1a6971 | Blue Swirl | gen_helper_fnegd(); |
2561 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2562 | dc1a6971 | Blue Swirl | break;
|
2563 | dc1a6971 | Blue Swirl | case 0x7: /* V9 fnegq */ |
2564 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2565 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2566 | dc1a6971 | Blue Swirl | gen_helper_fnegq(); |
2567 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2568 | dc1a6971 | Blue Swirl | break;
|
2569 | dc1a6971 | Blue Swirl | case 0xa: /* V9 fabsd */ |
2570 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2571 | dc1a6971 | Blue Swirl | gen_helper_fabsd(); |
2572 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2573 | dc1a6971 | Blue Swirl | break;
|
2574 | dc1a6971 | Blue Swirl | case 0xb: /* V9 fabsq */ |
2575 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2576 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2577 | dc1a6971 | Blue Swirl | gen_helper_fabsq(); |
2578 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2579 | dc1a6971 | Blue Swirl | break;
|
2580 | dc1a6971 | Blue Swirl | case 0x81: /* V9 fstox */ |
2581 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2582 | dc1a6971 | Blue Swirl | gen_helper_fstox(cpu_fpr[rs2]); |
2583 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2584 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2585 | dc1a6971 | Blue Swirl | break;
|
2586 | dc1a6971 | Blue Swirl | case 0x82: /* V9 fdtox */ |
2587 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2588 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2589 | dc1a6971 | Blue Swirl | gen_helper_fdtox(); |
2590 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2591 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2592 | dc1a6971 | Blue Swirl | break;
|
2593 | dc1a6971 | Blue Swirl | case 0x83: /* V9 fqtox */ |
2594 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2595 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2596 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2597 | dc1a6971 | Blue Swirl | gen_helper_fqtox(); |
2598 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2599 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2600 | dc1a6971 | Blue Swirl | break;
|
2601 | dc1a6971 | Blue Swirl | case 0x84: /* V9 fxtos */ |
2602 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2603 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2604 | dc1a6971 | Blue Swirl | gen_helper_fxtos(cpu_tmp32); |
2605 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2606 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2607 | dc1a6971 | Blue Swirl | break;
|
2608 | dc1a6971 | Blue Swirl | case 0x88: /* V9 fxtod */ |
2609 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2610 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2611 | dc1a6971 | Blue Swirl | gen_helper_fxtod(); |
2612 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2613 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2614 | dc1a6971 | Blue Swirl | break;
|
2615 | dc1a6971 | Blue Swirl | case 0x8c: /* V9 fxtoq */ |
2616 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2617 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2618 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2619 | dc1a6971 | Blue Swirl | gen_helper_fxtoq(); |
2620 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2621 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2622 | dc1a6971 | Blue Swirl | break;
|
2623 | 1f587329 | blueswir1 | #endif
|
2624 | dc1a6971 | Blue Swirl | default:
|
2625 | dc1a6971 | Blue Swirl | goto illegal_insn;
|
2626 | 0f8a249a | blueswir1 | } |
2627 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2628 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2629 | 0f8a249a | blueswir1 | int cond;
|
2630 | 3475187d | bellard | #endif
|
2631 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2632 | a80dde08 | bellard | goto jmp_insn;
|
2633 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2634 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2635 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2636 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2637 | cca1d527 | Blue Swirl | save_state(dc, cpu_cond); |
2638 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2639 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2640 | dcf24905 | blueswir1 | int l1;
|
2641 | dcf24905 | blueswir1 | |
2642 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2643 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2644 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2645 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2646 | cb63669a | pbrook | 0, l1);
|
2647 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2648 | dcf24905 | blueswir1 | gen_set_label(l1); |
2649 | 0f8a249a | blueswir1 | break;
|
2650 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2651 | dcf24905 | blueswir1 | int l1;
|
2652 | dcf24905 | blueswir1 | |
2653 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2654 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2655 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2656 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2657 | cb63669a | pbrook | 0, l1);
|
2658 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2659 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
2660 | dcf24905 | blueswir1 | gen_set_label(l1); |
2661 | 0f8a249a | blueswir1 | break;
|
2662 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2663 | dcf24905 | blueswir1 | int l1;
|
2664 | dcf24905 | blueswir1 | |
2665 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2666 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2667 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2668 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2669 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2670 | cb63669a | pbrook | 0, l1);
|
2671 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2672 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
2673 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
2674 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
2675 | dcf24905 | blueswir1 | gen_set_label(l1); |
2676 | 1f587329 | blueswir1 | break;
|
2677 | 0f8a249a | blueswir1 | } |
2678 | 0f8a249a | blueswir1 | #endif
|
2679 | 0f8a249a | blueswir1 | switch (xop) {
|
2680 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2681 | 714547bb | blueswir1 | #define FMOVSCC(fcc) \
|
2682 | 19f329ad | blueswir1 | { \ |
2683 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2684 | 19f329ad | blueswir1 | int l1; \
|
2685 | 19f329ad | blueswir1 | \ |
2686 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2687 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2688 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2689 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2690 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2691 | cb63669a | pbrook | 0, l1); \
|
2692 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2693 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2694 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2695 | 714547bb | blueswir1 | } |
2696 | 714547bb | blueswir1 | #define FMOVDCC(fcc) \
|
2697 | 714547bb | blueswir1 | { \ |
2698 | 714547bb | blueswir1 | TCGv r_cond; \ |
2699 | 714547bb | blueswir1 | int l1; \
|
2700 | 714547bb | blueswir1 | \ |
2701 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2702 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2703 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2704 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2705 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2706 | 714547bb | blueswir1 | 0, l1); \
|
2707 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2708 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2709 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2710 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2711 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2712 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2713 | 714547bb | blueswir1 | } |
2714 | 714547bb | blueswir1 | #define FMOVQCC(fcc) \
|
2715 | 714547bb | blueswir1 | { \ |
2716 | 714547bb | blueswir1 | TCGv r_cond; \ |
2717 | 714547bb | blueswir1 | int l1; \
|
2718 | 714547bb | blueswir1 | \ |
2719 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2720 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2721 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2722 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2723 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2724 | 714547bb | blueswir1 | 0, l1); \
|
2725 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2726 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2727 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2728 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2729 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2730 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2731 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2732 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2733 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2734 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2735 | 19f329ad | blueswir1 | } |
2736 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2737 | 714547bb | blueswir1 | FMOVSCC(0);
|
2738 | 0f8a249a | blueswir1 | break;
|
2739 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2740 | 714547bb | blueswir1 | FMOVDCC(0);
|
2741 | 0f8a249a | blueswir1 | break;
|
2742 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2743 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2744 | 714547bb | blueswir1 | FMOVQCC(0);
|
2745 | 1f587329 | blueswir1 | break;
|
2746 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2747 | 714547bb | blueswir1 | FMOVSCC(1);
|
2748 | 0f8a249a | blueswir1 | break;
|
2749 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2750 | 714547bb | blueswir1 | FMOVDCC(1);
|
2751 | 0f8a249a | blueswir1 | break;
|
2752 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2753 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2754 | 714547bb | blueswir1 | FMOVQCC(1);
|
2755 | 1f587329 | blueswir1 | break;
|
2756 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2757 | 714547bb | blueswir1 | FMOVSCC(2);
|
2758 | 0f8a249a | blueswir1 | break;
|
2759 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2760 | 714547bb | blueswir1 | FMOVDCC(2);
|
2761 | 0f8a249a | blueswir1 | break;
|
2762 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2763 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2764 | 714547bb | blueswir1 | FMOVQCC(2);
|
2765 | 1f587329 | blueswir1 | break;
|
2766 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2767 | 714547bb | blueswir1 | FMOVSCC(3);
|
2768 | 0f8a249a | blueswir1 | break;
|
2769 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2770 | 714547bb | blueswir1 | FMOVDCC(3);
|
2771 | 0f8a249a | blueswir1 | break;
|
2772 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2773 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2774 | 714547bb | blueswir1 | FMOVQCC(3);
|
2775 | 1f587329 | blueswir1 | break;
|
2776 | 714547bb | blueswir1 | #undef FMOVSCC
|
2777 | 714547bb | blueswir1 | #undef FMOVDCC
|
2778 | 714547bb | blueswir1 | #undef FMOVQCC
|
2779 | 714547bb | blueswir1 | #define FMOVSCC(icc) \
|
2780 | 714547bb | blueswir1 | { \ |
2781 | 714547bb | blueswir1 | TCGv r_cond; \ |
2782 | 714547bb | blueswir1 | int l1; \
|
2783 | 714547bb | blueswir1 | \ |
2784 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2785 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2786 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2787 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2788 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2789 | 714547bb | blueswir1 | 0, l1); \
|
2790 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2791 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2792 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2793 | 714547bb | blueswir1 | } |
2794 | 714547bb | blueswir1 | #define FMOVDCC(icc) \
|
2795 | 714547bb | blueswir1 | { \ |
2796 | 714547bb | blueswir1 | TCGv r_cond; \ |
2797 | 714547bb | blueswir1 | int l1; \
|
2798 | 714547bb | blueswir1 | \ |
2799 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2800 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2801 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2802 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2803 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2804 | 714547bb | blueswir1 | 0, l1); \
|
2805 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2806 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2807 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2808 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2809 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2810 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2811 | 714547bb | blueswir1 | } |
2812 | 714547bb | blueswir1 | #define FMOVQCC(icc) \
|
2813 | 714547bb | blueswir1 | { \ |
2814 | 714547bb | blueswir1 | TCGv r_cond; \ |
2815 | 714547bb | blueswir1 | int l1; \
|
2816 | 714547bb | blueswir1 | \ |
2817 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2818 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2819 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2820 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2821 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2822 | 714547bb | blueswir1 | 0, l1); \
|
2823 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2824 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2825 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2826 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2827 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2828 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2829 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2830 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2831 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2832 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2833 | 714547bb | blueswir1 | } |
2834 | 19f329ad | blueswir1 | |
2835 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2836 | 714547bb | blueswir1 | FMOVSCC(0);
|
2837 | 0f8a249a | blueswir1 | break;
|
2838 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2839 | 714547bb | blueswir1 | FMOVDCC(0);
|
2840 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2841 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2842 | 714547bb | blueswir1 | FMOVQCC(0);
|
2843 | 1f587329 | blueswir1 | break;
|
2844 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2845 | 714547bb | blueswir1 | FMOVSCC(1);
|
2846 | 0f8a249a | blueswir1 | break;
|
2847 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2848 | 714547bb | blueswir1 | FMOVDCC(1);
|
2849 | 0f8a249a | blueswir1 | break;
|
2850 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2851 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2852 | 714547bb | blueswir1 | FMOVQCC(1);
|
2853 | 1f587329 | blueswir1 | break;
|
2854 | 714547bb | blueswir1 | #undef FMOVSCC
|
2855 | 714547bb | blueswir1 | #undef FMOVDCC
|
2856 | 714547bb | blueswir1 | #undef FMOVQCC
|
2857 | 1f587329 | blueswir1 | #endif
|
2858 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2859 | 714547bb | blueswir1 | gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2860 | 0f8a249a | blueswir1 | break;
|
2861 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2862 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2863 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2864 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2865 | 0f8a249a | blueswir1 | break;
|
2866 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2867 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2868 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2869 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2870 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2871 | 1f587329 | blueswir1 | break;
|
2872 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2873 | 714547bb | blueswir1 | gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2874 | 0f8a249a | blueswir1 | break;
|
2875 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2876 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2877 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2878 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2879 | 0f8a249a | blueswir1 | break;
|
2880 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2881 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2882 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2883 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2884 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2885 | 1f587329 | blueswir1 | break;
|
2886 | 0f8a249a | blueswir1 | default:
|
2887 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2888 | 0f8a249a | blueswir1 | } |
2889 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2890 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2891 | e80cfcfc | bellard | |
2892 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2893 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2894 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2895 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2896 | 2ea815ca | blueswir1 | TCGv r_const; |
2897 | 2ea815ca | blueswir1 | |
2898 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2899 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
2900 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2901 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2902 | 0f8a249a | blueswir1 | } else { /* register */ |
2903 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2904 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
2905 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2906 | 0f8a249a | blueswir1 | } |
2907 | 0f8a249a | blueswir1 | } else {
|
2908 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2909 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2910 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2911 | 67526b20 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2912 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2913 | 0f8a249a | blueswir1 | } else { /* register */ |
2914 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2915 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2916 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2917 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2918 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2919 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2920 | 6f551262 | blueswir1 | } else
|
2921 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
2922 | 0f8a249a | blueswir1 | } |
2923 | 0f8a249a | blueswir1 | } |
2924 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2925 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2926 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2927 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2928 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2929 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2930 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2931 | 1a2fb1c0 | blueswir1 | } else {
|
2932 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
|
2933 | 1a2fb1c0 | blueswir1 | } |
2934 | 0f8a249a | blueswir1 | } else { /* register */ |
2935 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2936 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2937 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2938 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2939 | 1a2fb1c0 | blueswir1 | } else {
|
2940 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2941 | 1a2fb1c0 | blueswir1 | } |
2942 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2943 | 83469015 | bellard | } |
2944 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2945 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2946 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2947 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2948 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2949 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2950 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2951 | 1a2fb1c0 | blueswir1 | } else {
|
2952 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2953 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2954 | 1a2fb1c0 | blueswir1 | } |
2955 | 0f8a249a | blueswir1 | } else { /* register */ |
2956 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2957 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2958 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2959 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2960 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2961 | 1a2fb1c0 | blueswir1 | } else {
|
2962 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2963 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2964 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2965 | 1a2fb1c0 | blueswir1 | } |
2966 | 83469015 | bellard | } |
2967 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2968 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2969 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2970 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2971 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2972 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2973 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2974 | 1a2fb1c0 | blueswir1 | } else {
|
2975 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2976 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2977 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2978 | 1a2fb1c0 | blueswir1 | } |
2979 | 0f8a249a | blueswir1 | } else { /* register */ |
2980 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2981 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2982 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2983 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2984 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2985 | 1a2fb1c0 | blueswir1 | } else {
|
2986 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2987 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2988 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2989 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2990 | 1a2fb1c0 | blueswir1 | } |
2991 | 83469015 | bellard | } |
2992 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2993 | 83469015 | bellard | #endif
|
2994 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
2995 | cf495bcf | bellard | if (xop < 0x20) { |
2996 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
2997 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
2998 | cf495bcf | bellard | switch (xop & ~0x10) { |
2999 | b89e94af | Blue Swirl | case 0x0: /* add */ |
3000 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3001 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3002 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3003 | 41d72852 | Blue Swirl | gen_op_addi_cc(cpu_dst, cpu_src1, simm); |
3004 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3005 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3006 | 41d72852 | Blue Swirl | } else {
|
3007 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
3008 | 41d72852 | Blue Swirl | } |
3009 | 41d72852 | Blue Swirl | } else {
|
3010 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3011 | 41d72852 | Blue Swirl | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
3012 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3013 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3014 | 41d72852 | Blue Swirl | } else {
|
3015 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
3016 | 41d72852 | Blue Swirl | } |
3017 | 41d72852 | Blue Swirl | } |
3018 | cf495bcf | bellard | break;
|
3019 | b89e94af | Blue Swirl | case 0x1: /* and */ |
3020 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3021 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3022 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); |
3023 | 41d72852 | Blue Swirl | } else {
|
3024 | 41d72852 | Blue Swirl | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
3025 | 41d72852 | Blue Swirl | } |
3026 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3027 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3028 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3029 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3030 | 41d72852 | Blue Swirl | } |
3031 | cf495bcf | bellard | break;
|
3032 | b89e94af | Blue Swirl | case 0x2: /* or */ |
3033 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3034 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3035 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
3036 | 41d72852 | Blue Swirl | } else {
|
3037 | 41d72852 | Blue Swirl | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
3038 | 41d72852 | Blue Swirl | } |
3039 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3040 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3041 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3042 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3043 | 8393617c | Blue Swirl | } |
3044 | 0f8a249a | blueswir1 | break;
|
3045 | b89e94af | Blue Swirl | case 0x3: /* xor */ |
3046 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3047 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3048 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); |
3049 | 41d72852 | Blue Swirl | } else {
|
3050 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3051 | 41d72852 | Blue Swirl | } |
3052 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3053 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3054 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3055 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3056 | 8393617c | Blue Swirl | } |
3057 | cf495bcf | bellard | break;
|
3058 | b89e94af | Blue Swirl | case 0x4: /* sub */ |
3059 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3060 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3061 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3062 | d4b0d468 | Blue Swirl | gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc); |
3063 | 41d72852 | Blue Swirl | } else {
|
3064 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_dst, cpu_src1, simm); |
3065 | 41d72852 | Blue Swirl | } |
3066 | 41d72852 | Blue Swirl | } else {
|
3067 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3068 | 41d72852 | Blue Swirl | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
3069 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
3070 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
3071 | 41d72852 | Blue Swirl | } else {
|
3072 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
3073 | 41d72852 | Blue Swirl | } |
3074 | 41d72852 | Blue Swirl | } |
3075 | cf495bcf | bellard | break;
|
3076 | b89e94af | Blue Swirl | case 0x5: /* andn */ |
3077 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3078 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3079 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); |
3080 | 41d72852 | Blue Swirl | } else {
|
3081 | 41d72852 | Blue Swirl | tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
3082 | 41d72852 | Blue Swirl | } |
3083 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3084 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3085 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3086 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3087 | 8393617c | Blue Swirl | } |
3088 | cf495bcf | bellard | break;
|
3089 | b89e94af | Blue Swirl | case 0x6: /* orn */ |
3090 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3091 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3092 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); |
3093 | 41d72852 | Blue Swirl | } else {
|
3094 | 41d72852 | Blue Swirl | tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
3095 | 41d72852 | Blue Swirl | } |
3096 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3097 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3098 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3099 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3100 | 8393617c | Blue Swirl | } |
3101 | cf495bcf | bellard | break;
|
3102 | b89e94af | Blue Swirl | case 0x7: /* xorn */ |
3103 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3104 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3105 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); |
3106 | 41d72852 | Blue Swirl | } else {
|
3107 | 41d72852 | Blue Swirl | tcg_gen_not_tl(cpu_tmp0, cpu_src2); |
3108 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3109 | 41d72852 | Blue Swirl | } |
3110 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3111 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3112 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3113 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3114 | 8393617c | Blue Swirl | } |
3115 | cf495bcf | bellard | break;
|
3116 | b89e94af | Blue Swirl | case 0x8: /* addx, V9 addc */ |
3117 | 70c48285 | Richard Henderson | gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, |
3118 | 70c48285 | Richard Henderson | (xop & 0x10));
|
3119 | cf495bcf | bellard | break;
|
3120 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3121 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
3122 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3123 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3124 | 41d72852 | Blue Swirl | tcg_gen_muli_i64(cpu_dst, cpu_src1, simm); |
3125 | 41d72852 | Blue Swirl | } else {
|
3126 | 41d72852 | Blue Swirl | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
3127 | 41d72852 | Blue Swirl | } |
3128 | ded3ab80 | pbrook | break;
|
3129 | ded3ab80 | pbrook | #endif
|
3130 | b89e94af | Blue Swirl | case 0xa: /* umul */ |
3131 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3132 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
3133 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3134 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3135 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3136 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3137 | 8393617c | Blue Swirl | } |
3138 | cf495bcf | bellard | break;
|
3139 | b89e94af | Blue Swirl | case 0xb: /* smul */ |
3140 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
3141 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
3142 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3143 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3144 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3145 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3146 | 8393617c | Blue Swirl | } |
3147 | cf495bcf | bellard | break;
|
3148 | b89e94af | Blue Swirl | case 0xc: /* subx, V9 subc */ |
3149 | 70c48285 | Richard Henderson | gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, |
3150 | 70c48285 | Richard Henderson | (xop & 0x10));
|
3151 | cf495bcf | bellard | break;
|
3152 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3153 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3154 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3155 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3156 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3157 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3158 | ded3ab80 | pbrook | break;
|
3159 | ded3ab80 | pbrook | #endif
|
3160 | b89e94af | Blue Swirl | case 0xe: /* udiv */ |
3161 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3162 | a7812ae4 | pbrook | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
3163 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3164 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3165 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3166 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3167 | 8393617c | Blue Swirl | } |
3168 | cf495bcf | bellard | break;
|
3169 | b89e94af | Blue Swirl | case 0xf: /* sdiv */ |
3170 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3171 | a7812ae4 | pbrook | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
3172 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3173 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3174 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3175 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3176 | 8393617c | Blue Swirl | } |
3177 | cf495bcf | bellard | break;
|
3178 | cf495bcf | bellard | default:
|
3179 | cf495bcf | bellard | goto illegal_insn;
|
3180 | cf495bcf | bellard | } |
3181 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3182 | cf495bcf | bellard | } else {
|
3183 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
3184 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
3185 | cf495bcf | bellard | switch (xop) {
|
3186 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3187 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3188 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3189 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); |
3190 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADD; |
3191 | 0f8a249a | blueswir1 | break;
|
3192 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3193 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3194 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3195 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); |
3196 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUB; |
3197 | 0f8a249a | blueswir1 | break;
|
3198 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3199 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3200 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3201 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3202 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV); |
3203 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADDTV; |
3204 | 0f8a249a | blueswir1 | break;
|
3205 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3206 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3207 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3208 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3209 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV); |
3210 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUBTV; |
3211 | 0f8a249a | blueswir1 | break;
|
3212 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3213 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3214 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3215 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3216 | d084469c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3217 | d084469c | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3218 | cf495bcf | bellard | break;
|
3219 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3220 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3221 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3222 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3223 | 67526b20 | Blue Swirl | tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3224 | e35298cd | blueswir1 | } else { /* register */ |
3225 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3226 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3227 | e35298cd | blueswir1 | } |
3228 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3229 | cf495bcf | bellard | break;
|
3230 | 83469015 | bellard | case 0x26: /* srl */ |
3231 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3232 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3233 | 67526b20 | Blue Swirl | tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3234 | e35298cd | blueswir1 | } else { /* register */ |
3235 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3236 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3237 | e35298cd | blueswir1 | } |
3238 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3239 | cf495bcf | bellard | break;
|
3240 | 83469015 | bellard | case 0x27: /* sra */ |
3241 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3242 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3243 | 67526b20 | Blue Swirl | tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3244 | e35298cd | blueswir1 | } else { /* register */ |
3245 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3246 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3247 | e35298cd | blueswir1 | } |
3248 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3249 | cf495bcf | bellard | break;
|
3250 | 83469015 | bellard | #endif
|
3251 | cf495bcf | bellard | case 0x30: |
3252 | cf495bcf | bellard | { |
3253 | cf495bcf | bellard | switch(rd) {
|
3254 | 3475187d | bellard | case 0: /* wry */ |
3255 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3256 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3257 | cf495bcf | bellard | break;
|
3258 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3259 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3260 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3261 | 65fe7b09 | blueswir1 | on the microSPARC
|
3262 | 65fe7b09 | blueswir1 | II */
|
3263 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3264 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3265 | 65fe7b09 | blueswir1 | manual, nop on the
|
3266 | 65fe7b09 | blueswir1 | microSPARC II */
|
3267 | 65fe7b09 | blueswir1 | break;
|
3268 | 65fe7b09 | blueswir1 | #else
|
3269 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3270 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3271 | a7812ae4 | pbrook | gen_helper_wrccr(cpu_dst); |
3272 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3273 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3274 | 0f8a249a | blueswir1 | break;
|
3275 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3276 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3277 | 01b5d4e5 | Igor V. Kovalenko | tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
|
3278 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
3279 | 0f8a249a | blueswir1 | break;
|
3280 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3281 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3282 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
3283 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3284 | 3299908c | blueswir1 | gen_op_next_insn(); |
3285 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3286 | 3299908c | blueswir1 | dc->is_br = 1;
|
3287 | 0f8a249a | blueswir1 | break;
|
3288 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3289 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3290 | 6ad6135d | Blue Swirl | if (supervisor(dc)) {
|
3291 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3292 | 6ad6135d | Blue Swirl | } |
3293 | 3475187d | bellard | #endif
|
3294 | 0f8a249a | blueswir1 | break;
|
3295 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3296 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3297 | 725cb90b | bellard | goto jmp_insn;
|
3298 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3299 | 0f8a249a | blueswir1 | break;
|
3300 | 9d926598 | blueswir1 | case 0x14: /* Softint set */ |
3301 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3302 | 9d926598 | blueswir1 | goto illegal_insn;
|
3303 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3304 | a7812ae4 | pbrook | gen_helper_set_softint(cpu_tmp64); |
3305 | 9d926598 | blueswir1 | break;
|
3306 | 9d926598 | blueswir1 | case 0x15: /* Softint clear */ |
3307 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3308 | 9d926598 | blueswir1 | goto illegal_insn;
|
3309 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3310 | a7812ae4 | pbrook | gen_helper_clear_softint(cpu_tmp64); |
3311 | 9d926598 | blueswir1 | break;
|
3312 | 9d926598 | blueswir1 | case 0x16: /* Softint write */ |
3313 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3314 | 9d926598 | blueswir1 | goto illegal_insn;
|
3315 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3316 | a7812ae4 | pbrook | gen_helper_write_softint(cpu_tmp64); |
3317 | 9d926598 | blueswir1 | break;
|
3318 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3319 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3320 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3321 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3322 | 83469015 | bellard | #endif
|
3323 | ccd4a219 | blueswir1 | { |
3324 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3325 | ccd4a219 | blueswir1 | |
3326 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3327 | 6ae20372 | blueswir1 | cpu_src2); |
3328 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3329 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3330 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3331 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3332 | a7812ae4 | pbrook | cpu_tick_cmpr); |
3333 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3334 | ccd4a219 | blueswir1 | } |
3335 | 0f8a249a | blueswir1 | break;
|
3336 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3337 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3338 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3339 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3340 | 83469015 | bellard | #endif
|
3341 | ccd4a219 | blueswir1 | { |
3342 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3343 | ccd4a219 | blueswir1 | |
3344 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3345 | 6ae20372 | blueswir1 | cpu_src2); |
3346 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3347 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3348 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3349 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3350 | a7812ae4 | pbrook | cpu_dst); |
3351 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3352 | ccd4a219 | blueswir1 | } |
3353 | 0f8a249a | blueswir1 | break;
|
3354 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3355 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3356 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3357 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3358 | 3475187d | bellard | #endif
|
3359 | ccd4a219 | blueswir1 | { |
3360 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3361 | ccd4a219 | blueswir1 | |
3362 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3363 | 6ae20372 | blueswir1 | cpu_src2); |
3364 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3365 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3366 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3367 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3368 | a7812ae4 | pbrook | cpu_stick_cmpr); |
3369 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3370 | ccd4a219 | blueswir1 | } |
3371 | 0f8a249a | blueswir1 | break;
|
3372 | 83469015 | bellard | |
3373 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3374 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3375 | 77f193da | blueswir1 | Counter */
|
3376 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3377 | 83469015 | bellard | #endif
|
3378 | 3475187d | bellard | default:
|
3379 | cf495bcf | bellard | goto illegal_insn;
|
3380 | cf495bcf | bellard | } |
3381 | cf495bcf | bellard | } |
3382 | cf495bcf | bellard | break;
|
3383 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3384 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3385 | e8af50a3 | bellard | { |
3386 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3387 | 0f8a249a | blueswir1 | goto priv_insn;
|
3388 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3389 | 0f8a249a | blueswir1 | switch (rd) {
|
3390 | 0f8a249a | blueswir1 | case 0: |
3391 | a7812ae4 | pbrook | gen_helper_saved(); |
3392 | 0f8a249a | blueswir1 | break;
|
3393 | 0f8a249a | blueswir1 | case 1: |
3394 | a7812ae4 | pbrook | gen_helper_restored(); |
3395 | 0f8a249a | blueswir1 | break;
|
3396 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3397 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3398 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3399 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3400 | e9ebed4d | blueswir1 | // XXX
|
3401 | 0f8a249a | blueswir1 | default:
|
3402 | 3475187d | bellard | goto illegal_insn;
|
3403 | 3475187d | bellard | } |
3404 | 3475187d | bellard | #else
|
3405 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3406 | a7812ae4 | pbrook | gen_helper_wrpsr(cpu_dst); |
3407 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3408 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3409 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3410 | 9e61bde5 | bellard | gen_op_next_insn(); |
3411 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3412 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3413 | 3475187d | bellard | #endif
|
3414 | e8af50a3 | bellard | } |
3415 | e8af50a3 | bellard | break;
|
3416 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3417 | e8af50a3 | bellard | { |
3418 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3419 | 0f8a249a | blueswir1 | goto priv_insn;
|
3420 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3421 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3422 | 0f8a249a | blueswir1 | switch (rd) {
|
3423 | 0f8a249a | blueswir1 | case 0: // tpc |
3424 | 375ee38b | blueswir1 | { |
3425 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3426 | 375ee38b | blueswir1 | |
3427 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3428 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3429 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3430 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3431 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3432 | 375ee38b | blueswir1 | } |
3433 | 0f8a249a | blueswir1 | break;
|
3434 | 0f8a249a | blueswir1 | case 1: // tnpc |
3435 | 375ee38b | blueswir1 | { |
3436 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3437 | 375ee38b | blueswir1 | |
3438 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3439 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3440 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3441 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3442 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3443 | 375ee38b | blueswir1 | } |
3444 | 0f8a249a | blueswir1 | break;
|
3445 | 0f8a249a | blueswir1 | case 2: // tstate |
3446 | 375ee38b | blueswir1 | { |
3447 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3448 | 375ee38b | blueswir1 | |
3449 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3450 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3451 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3452 | 77f193da | blueswir1 | offsetof(trap_state, |
3453 | 77f193da | blueswir1 | tstate)); |
3454 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3455 | 375ee38b | blueswir1 | } |
3456 | 0f8a249a | blueswir1 | break;
|
3457 | 0f8a249a | blueswir1 | case 3: // tt |
3458 | 375ee38b | blueswir1 | { |
3459 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3460 | 375ee38b | blueswir1 | |
3461 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3462 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3463 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3464 | 527067d8 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, r_tsptr, |
3465 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3466 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3467 | 375ee38b | blueswir1 | } |
3468 | 0f8a249a | blueswir1 | break;
|
3469 | 0f8a249a | blueswir1 | case 4: // tick |
3470 | ccd4a219 | blueswir1 | { |
3471 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3472 | ccd4a219 | blueswir1 | |
3473 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3474 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3475 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3476 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3477 | a7812ae4 | pbrook | cpu_tmp0); |
3478 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3479 | ccd4a219 | blueswir1 | } |
3480 | 0f8a249a | blueswir1 | break;
|
3481 | 0f8a249a | blueswir1 | case 5: // tba |
3482 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3483 | 0f8a249a | blueswir1 | break;
|
3484 | 0f8a249a | blueswir1 | case 6: // pstate |
3485 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3486 | a7812ae4 | pbrook | gen_helper_wrpstate(cpu_tmp0); |
3487 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
3488 | 0f8a249a | blueswir1 | break;
|
3489 | 0f8a249a | blueswir1 | case 7: // tl |
3490 | 9fd1ae3a | Igor V. Kovalenko | save_state(dc, cpu_cond); |
3491 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3492 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3493 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3494 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
3495 | 0f8a249a | blueswir1 | break;
|
3496 | 0f8a249a | blueswir1 | case 8: // pil |
3497 | 1fae7b70 | Igor V. Kovalenko | gen_helper_wrpil(cpu_tmp0); |
3498 | 0f8a249a | blueswir1 | break;
|
3499 | 0f8a249a | blueswir1 | case 9: // cwp |
3500 | a7812ae4 | pbrook | gen_helper_wrcwp(cpu_tmp0); |
3501 | 0f8a249a | blueswir1 | break;
|
3502 | 0f8a249a | blueswir1 | case 10: // cansave |
3503 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3504 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3505 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3506 | 77f193da | blueswir1 | cansave)); |
3507 | 0f8a249a | blueswir1 | break;
|
3508 | 0f8a249a | blueswir1 | case 11: // canrestore |
3509 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3510 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3511 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3512 | 77f193da | blueswir1 | canrestore)); |
3513 | 0f8a249a | blueswir1 | break;
|
3514 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3515 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3516 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3517 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3518 | 77f193da | blueswir1 | cleanwin)); |
3519 | 0f8a249a | blueswir1 | break;
|
3520 | 0f8a249a | blueswir1 | case 13: // otherwin |
3521 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3522 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3523 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3524 | 77f193da | blueswir1 | otherwin)); |
3525 | 0f8a249a | blueswir1 | break;
|
3526 | 0f8a249a | blueswir1 | case 14: // wstate |
3527 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3528 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3529 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3530 | 77f193da | blueswir1 | wstate)); |
3531 | 0f8a249a | blueswir1 | break;
|
3532 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3533 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3534 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3535 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3536 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3537 | e9ebed4d | blueswir1 | break;
|
3538 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3539 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3540 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3541 | e9ebed4d | blueswir1 | goto priv_insn;
|
3542 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); |
3543 | e9ebed4d | blueswir1 | break;
|
3544 | 0f8a249a | blueswir1 | default:
|
3545 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3546 | 0f8a249a | blueswir1 | } |
3547 | 3475187d | bellard | #else
|
3548 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3549 | c93e7817 | blueswir1 | if (dc->def->nwindows != 32) |
3550 | c93e7817 | blueswir1 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
3551 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3552 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3553 | 3475187d | bellard | #endif
|
3554 | e8af50a3 | bellard | } |
3555 | e8af50a3 | bellard | break;
|
3556 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3557 | e8af50a3 | bellard | { |
3558 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3559 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3560 | 0f8a249a | blueswir1 | goto priv_insn;
|
3561 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3562 | e9ebed4d | blueswir1 | #else
|
3563 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3564 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3565 | e9ebed4d | blueswir1 | goto priv_insn;
|
3566 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3567 | e9ebed4d | blueswir1 | switch (rd) {
|
3568 | e9ebed4d | blueswir1 | case 0: // hpstate |
3569 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3570 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3571 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3572 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3573 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3574 | e9ebed4d | blueswir1 | break;
|
3575 | e9ebed4d | blueswir1 | case 1: // htstate |
3576 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3577 | e9ebed4d | blueswir1 | break;
|
3578 | e9ebed4d | blueswir1 | case 3: // hintp |
3579 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3580 | e9ebed4d | blueswir1 | break;
|
3581 | e9ebed4d | blueswir1 | case 5: // htba |
3582 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3583 | e9ebed4d | blueswir1 | break;
|
3584 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3585 | ccd4a219 | blueswir1 | { |
3586 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3587 | ccd4a219 | blueswir1 | |
3588 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3589 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3590 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3591 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3592 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3593 | a7812ae4 | pbrook | cpu_hstick_cmpr); |
3594 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3595 | ccd4a219 | blueswir1 | } |
3596 | e9ebed4d | blueswir1 | break;
|
3597 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3598 | e9ebed4d | blueswir1 | default:
|
3599 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3600 | e9ebed4d | blueswir1 | } |
3601 | e9ebed4d | blueswir1 | #endif
|
3602 | e8af50a3 | bellard | } |
3603 | e8af50a3 | bellard | break;
|
3604 | e8af50a3 | bellard | #endif
|
3605 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3606 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3607 | 0f8a249a | blueswir1 | { |
3608 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3609 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3610 | 748b9d8e | blueswir1 | TCGv r_cond; |
3611 | 00f219bf | blueswir1 | int l1;
|
3612 | 00f219bf | blueswir1 | |
3613 | a7812ae4 | pbrook | r_cond = tcg_temp_new(); |
3614 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3615 | 0f8a249a | blueswir1 | if (cc == 0) |
3616 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
3617 | 0f8a249a | blueswir1 | else if (cc == 2) |
3618 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
3619 | 0f8a249a | blueswir1 | else
|
3620 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3621 | 0f8a249a | blueswir1 | } else {
|
3622 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3623 | 0f8a249a | blueswir1 | } |
3624 | 00f219bf | blueswir1 | |
3625 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3626 | 00f219bf | blueswir1 | |
3627 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3628 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3629 | 2ea815ca | blueswir1 | TCGv r_const; |
3630 | 2ea815ca | blueswir1 | |
3631 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 10); |
3632 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3633 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3634 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3635 | 00f219bf | blueswir1 | } else {
|
3636 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3637 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3638 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3639 | 00f219bf | blueswir1 | } |
3640 | 00f219bf | blueswir1 | gen_set_label(l1); |
3641 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3642 | 0f8a249a | blueswir1 | break;
|
3643 | 0f8a249a | blueswir1 | } |
3644 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3645 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3646 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3647 | 0f8a249a | blueswir1 | break;
|
3648 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3649 | 0f8a249a | blueswir1 | { |
3650 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3651 | a7812ae4 | pbrook | gen_helper_popc(cpu_dst, cpu_src2); |
3652 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3653 | 0f8a249a | blueswir1 | } |
3654 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3655 | 0f8a249a | blueswir1 | { |
3656 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3657 | 00f219bf | blueswir1 | int l1;
|
3658 | 00f219bf | blueswir1 | |
3659 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3660 | 00f219bf | blueswir1 | |
3661 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3662 | 00f219bf | blueswir1 | |
3663 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3664 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3665 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3666 | 2ea815ca | blueswir1 | TCGv r_const; |
3667 | 2ea815ca | blueswir1 | |
3668 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 9); |
3669 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3670 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3671 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3672 | 00f219bf | blueswir1 | } else {
|
3673 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3674 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3675 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3676 | 0f8a249a | blueswir1 | } |
3677 | 00f219bf | blueswir1 | gen_set_label(l1); |
3678 | 0f8a249a | blueswir1 | break;
|
3679 | 0f8a249a | blueswir1 | } |
3680 | 0f8a249a | blueswir1 | #endif
|
3681 | 0f8a249a | blueswir1 | default:
|
3682 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3683 | 0f8a249a | blueswir1 | } |
3684 | 0f8a249a | blueswir1 | } |
3685 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3686 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3687 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3688 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3689 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3690 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3691 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3692 | 3299908c | blueswir1 | |
3693 | 3299908c | blueswir1 | switch (opf) {
|
3694 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3695 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3696 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3697 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3698 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3699 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3700 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3701 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3702 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3703 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3704 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3705 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3706 | e9ebed4d | blueswir1 | // XXX
|
3707 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3708 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3709 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3710 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3711 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3712 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3713 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3714 | e9ebed4d | blueswir1 | break;
|
3715 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3716 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3717 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3718 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3719 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3720 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3721 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3722 | e9ebed4d | blueswir1 | break;
|
3723 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3724 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3725 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3726 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3727 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3728 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3729 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3730 | e9ebed4d | blueswir1 | break;
|
3731 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3732 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3733 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3734 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3735 | a7812ae4 | pbrook | gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); |
3736 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3737 | 3299908c | blueswir1 | break;
|
3738 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3739 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3740 | 3299908c | blueswir1 | // XXX
|
3741 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3742 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3743 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3744 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3745 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3746 | a7812ae4 | pbrook | gen_helper_fcmple16(); |
3747 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3748 | e9ebed4d | blueswir1 | break;
|
3749 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3750 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3751 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3752 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3753 | a7812ae4 | pbrook | gen_helper_fcmpne16(); |
3754 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3755 | 3299908c | blueswir1 | break;
|
3756 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3757 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3758 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3759 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3760 | a7812ae4 | pbrook | gen_helper_fcmple32(); |
3761 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3762 | e9ebed4d | blueswir1 | break;
|
3763 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3764 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3765 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3766 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3767 | a7812ae4 | pbrook | gen_helper_fcmpne32(); |
3768 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3769 | e9ebed4d | blueswir1 | break;
|
3770 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3771 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3772 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3773 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3774 | a7812ae4 | pbrook | gen_helper_fcmpgt16(); |
3775 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3776 | e9ebed4d | blueswir1 | break;
|
3777 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3778 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3779 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3780 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3781 | a7812ae4 | pbrook | gen_helper_fcmpeq16(); |
3782 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3783 | e9ebed4d | blueswir1 | break;
|
3784 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3785 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3786 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3787 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3788 | a7812ae4 | pbrook | gen_helper_fcmpgt32(); |
3789 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3790 | e9ebed4d | blueswir1 | break;
|
3791 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3792 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3793 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3794 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3795 | a7812ae4 | pbrook | gen_helper_fcmpeq32(); |
3796 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3797 | e9ebed4d | blueswir1 | break;
|
3798 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3799 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3800 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3801 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3802 | a7812ae4 | pbrook | gen_helper_fmul8x16(); |
3803 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3804 | e9ebed4d | blueswir1 | break;
|
3805 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3806 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3807 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3808 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3809 | a7812ae4 | pbrook | gen_helper_fmul8x16au(); |
3810 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3811 | e9ebed4d | blueswir1 | break;
|
3812 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3813 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3814 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3815 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3816 | a7812ae4 | pbrook | gen_helper_fmul8x16al(); |
3817 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3818 | e9ebed4d | blueswir1 | break;
|
3819 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3820 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3821 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3822 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3823 | a7812ae4 | pbrook | gen_helper_fmul8sux16(); |
3824 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3825 | e9ebed4d | blueswir1 | break;
|
3826 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3827 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3828 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3829 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3830 | a7812ae4 | pbrook | gen_helper_fmul8ulx16(); |
3831 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3832 | e9ebed4d | blueswir1 | break;
|
3833 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3834 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3835 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3836 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3837 | a7812ae4 | pbrook | gen_helper_fmuld8sux16(); |
3838 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3839 | e9ebed4d | blueswir1 | break;
|
3840 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3841 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3842 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3843 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3844 | a7812ae4 | pbrook | gen_helper_fmuld8ulx16(); |
3845 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3846 | e9ebed4d | blueswir1 | break;
|
3847 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3848 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3849 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3850 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3851 | e9ebed4d | blueswir1 | // XXX
|
3852 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3853 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3854 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3855 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3856 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3857 | a7812ae4 | pbrook | gen_helper_faligndata(); |
3858 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3859 | 3299908c | blueswir1 | break;
|
3860 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3861 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3862 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3863 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3864 | a7812ae4 | pbrook | gen_helper_fpmerge(); |
3865 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3866 | e9ebed4d | blueswir1 | break;
|
3867 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3868 | e9ebed4d | blueswir1 | // XXX
|
3869 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3870 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3871 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3872 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3873 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3874 | a7812ae4 | pbrook | gen_helper_fexpand(); |
3875 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3876 | e9ebed4d | blueswir1 | break;
|
3877 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3878 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3879 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3880 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3881 | a7812ae4 | pbrook | gen_helper_fpadd16(); |
3882 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3883 | e9ebed4d | blueswir1 | break;
|
3884 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3885 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3886 | a7812ae4 | pbrook | gen_helper_fpadd16s(cpu_fpr[rd], |
3887 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3888 | e9ebed4d | blueswir1 | break;
|
3889 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3890 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3891 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3892 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3893 | a7812ae4 | pbrook | gen_helper_fpadd32(); |
3894 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3895 | e9ebed4d | blueswir1 | break;
|
3896 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3897 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3898 | a7812ae4 | pbrook | gen_helper_fpadd32s(cpu_fpr[rd], |
3899 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3900 | e9ebed4d | blueswir1 | break;
|
3901 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3902 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3903 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3904 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3905 | a7812ae4 | pbrook | gen_helper_fpsub16(); |
3906 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3907 | e9ebed4d | blueswir1 | break;
|
3908 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3909 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3910 | a7812ae4 | pbrook | gen_helper_fpsub16s(cpu_fpr[rd], |
3911 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3912 | e9ebed4d | blueswir1 | break;
|
3913 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3914 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3915 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3916 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3917 | a7812ae4 | pbrook | gen_helper_fpsub32(); |
3918 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3919 | e9ebed4d | blueswir1 | break;
|
3920 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3921 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3922 | a7812ae4 | pbrook | gen_helper_fpsub32s(cpu_fpr[rd], |
3923 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3924 | e9ebed4d | blueswir1 | break;
|
3925 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3926 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3927 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
3928 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
3929 | 3299908c | blueswir1 | break;
|
3930 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3931 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3932 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], 0);
|
3933 | 3299908c | blueswir1 | break;
|
3934 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3935 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3936 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3937 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3938 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3939 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3940 | e9ebed4d | blueswir1 | break;
|
3941 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3942 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3943 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3944 | e9ebed4d | blueswir1 | break;
|
3945 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3946 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3947 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3948 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3949 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3950 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3951 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3952 | e9ebed4d | blueswir1 | break;
|
3953 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3954 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3955 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3956 | e9ebed4d | blueswir1 | break;
|
3957 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3958 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3959 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
3960 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3961 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3962 | e9ebed4d | blueswir1 | break;
|
3963 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3964 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3965 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3966 | e9ebed4d | blueswir1 | break;
|
3967 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3968 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3969 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3970 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3971 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3972 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3973 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3974 | e9ebed4d | blueswir1 | break;
|
3975 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3976 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3977 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3978 | e9ebed4d | blueswir1 | break;
|
3979 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3980 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3981 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3982 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3983 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3984 | e9ebed4d | blueswir1 | break;
|
3985 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3986 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3987 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3988 | e9ebed4d | blueswir1 | break;
|
3989 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3990 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3991 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3992 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3993 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
|
3994 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3995 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3996 | e9ebed4d | blueswir1 | break;
|
3997 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3998 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3999 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4000 | e9ebed4d | blueswir1 | break;
|
4001 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
4002 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4003 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
4004 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4005 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
4006 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4007 | e9ebed4d | blueswir1 | break;
|
4008 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
4009 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4010 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
4011 | e9ebed4d | blueswir1 | break;
|
4012 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
4013 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4014 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4015 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4016 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
|
4017 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4018 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4019 | e9ebed4d | blueswir1 | break;
|
4020 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
4021 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4022 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4023 | e9ebed4d | blueswir1 | break;
|
4024 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
4025 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4026 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
4027 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
4028 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
4029 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
4030 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
4031 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4032 | e9ebed4d | blueswir1 | break;
|
4033 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
4034 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4035 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
4036 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
4037 | e9ebed4d | blueswir1 | break;
|
4038 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
4039 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4040 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
4041 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
4042 | 1d01299d | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4043 | 3299908c | blueswir1 | break;
|
4044 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
4045 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4046 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
4047 | 3299908c | blueswir1 | break;
|
4048 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
4049 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4050 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4051 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4052 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
4053 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4054 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4055 | e9ebed4d | blueswir1 | break;
|
4056 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
4057 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4058 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4059 | e9ebed4d | blueswir1 | break;
|
4060 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
4061 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4062 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
4063 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4064 | 3299908c | blueswir1 | break;
|
4065 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
4066 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4067 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
4068 | 3299908c | blueswir1 | break;
|
4069 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
4070 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4071 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
4072 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
4073 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
4074 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
4075 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
4076 | e9ebed4d | blueswir1 | break;
|
4077 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
4078 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4079 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
4080 | e9ebed4d | blueswir1 | break;
|
4081 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
4082 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4083 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
4084 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
4085 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
|
4086 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
4087 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
4088 | e9ebed4d | blueswir1 | break;
|
4089 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
4090 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4091 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
4092 | e9ebed4d | blueswir1 | break;
|
4093 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
4094 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4095 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
4096 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
4097 | 3299908c | blueswir1 | break;
|
4098 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
4099 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
4100 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], -1);
|
4101 | 3299908c | blueswir1 | break;
|
4102 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
4103 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
4104 | e9ebed4d | blueswir1 | // XXX
|
4105 | e9ebed4d | blueswir1 | goto illegal_insn;
|
4106 | 3299908c | blueswir1 | default:
|
4107 | 3299908c | blueswir1 | goto illegal_insn;
|
4108 | 3299908c | blueswir1 | } |
4109 | 3299908c | blueswir1 | #else
|
4110 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4111 | 3299908c | blueswir1 | #endif
|
4112 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
4113 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
4114 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4115 | fcc72045 | blueswir1 | #else
|
4116 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4117 | fcc72045 | blueswir1 | #endif
|
4118 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4119 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
4120 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4121 | 2ea815ca | blueswir1 | |
4122 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4123 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4124 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4125 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4126 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4127 | 0f8a249a | blueswir1 | } else { /* register */ |
4128 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4129 | 0f8a249a | blueswir1 | if (rs2) {
|
4130 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4131 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4132 | 6f551262 | blueswir1 | } else
|
4133 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4134 | 3475187d | bellard | } |
4135 | a7812ae4 | pbrook | gen_helper_restore(); |
4136 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4137 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4138 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4139 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4140 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4141 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4142 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4143 | 3475187d | bellard | #endif
|
4144 | 0f8a249a | blueswir1 | } else {
|
4145 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4146 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4147 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4148 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4149 | 0f8a249a | blueswir1 | } else { /* register */ |
4150 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4151 | 0f8a249a | blueswir1 | if (rs2) {
|
4152 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4153 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4154 | 6f551262 | blueswir1 | } else
|
4155 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4156 | cf495bcf | bellard | } |
4157 | 0f8a249a | blueswir1 | switch (xop) {
|
4158 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4159 | 0f8a249a | blueswir1 | { |
4160 | a7812ae4 | pbrook | TCGv r_pc; |
4161 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4162 | 2ea815ca | blueswir1 | |
4163 | a7812ae4 | pbrook | r_pc = tcg_const_tl(dc->pc); |
4164 | a7812ae4 | pbrook | gen_movl_TN_reg(rd, r_pc); |
4165 | a7812ae4 | pbrook | tcg_temp_free(r_pc); |
4166 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4167 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4168 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4169 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4170 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4171 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4172 | 0f8a249a | blueswir1 | } |
4173 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4174 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4175 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4176 | 0f8a249a | blueswir1 | { |
4177 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4178 | 2ea815ca | blueswir1 | |
4179 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4180 | 0f8a249a | blueswir1 | goto priv_insn;
|
4181 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4182 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4183 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4184 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4185 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4186 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4187 | a7812ae4 | pbrook | gen_helper_rett(); |
4188 | 0f8a249a | blueswir1 | } |
4189 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4190 | 0f8a249a | blueswir1 | #endif
|
4191 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4192 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4193 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4194 | a7812ae4 | pbrook | gen_helper_flush(cpu_dst); |
4195 | 0f8a249a | blueswir1 | break;
|
4196 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4197 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4198 | a7812ae4 | pbrook | gen_helper_save(); |
4199 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4200 | 0f8a249a | blueswir1 | break;
|
4201 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4202 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4203 | a7812ae4 | pbrook | gen_helper_restore(); |
4204 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4205 | 0f8a249a | blueswir1 | break;
|
4206 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4207 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4208 | 0f8a249a | blueswir1 | { |
4209 | 0f8a249a | blueswir1 | switch (rd) {
|
4210 | 0f8a249a | blueswir1 | case 0: |
4211 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4212 | 0f8a249a | blueswir1 | goto priv_insn;
|
4213 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4214 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4215 | a7812ae4 | pbrook | gen_helper_done(); |
4216 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4217 | 0f8a249a | blueswir1 | case 1: |
4218 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4219 | 0f8a249a | blueswir1 | goto priv_insn;
|
4220 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4221 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4222 | a7812ae4 | pbrook | gen_helper_retry(); |
4223 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4224 | 0f8a249a | blueswir1 | default:
|
4225 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4226 | 0f8a249a | blueswir1 | } |
4227 | 0f8a249a | blueswir1 | } |
4228 | 0f8a249a | blueswir1 | break;
|
4229 | 0f8a249a | blueswir1 | #endif
|
4230 | 0f8a249a | blueswir1 | default:
|
4231 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4232 | 0f8a249a | blueswir1 | } |
4233 | cf495bcf | bellard | } |
4234 | 0f8a249a | blueswir1 | break;
|
4235 | 0f8a249a | blueswir1 | } |
4236 | 0f8a249a | blueswir1 | break;
|
4237 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4238 | 0f8a249a | blueswir1 | { |
4239 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4240 | 9322a4bf | blueswir1 | |
4241 | cfa90513 | Blue Swirl | /* flush pending conditional evaluations before exposing
|
4242 | cfa90513 | Blue Swirl | cpu state */
|
4243 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
4244 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
4245 | cfa90513 | Blue Swirl | gen_helper_compute_psr(); |
4246 | cfa90513 | Blue Swirl | } |
4247 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4248 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4249 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4250 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4251 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4252 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4253 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4254 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_addr, cpu_src1, simm); |
4255 | 0f8a249a | blueswir1 | } else { /* register */ |
4256 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4257 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4258 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4259 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4260 | 6f551262 | blueswir1 | } else
|
4261 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4262 | 0f8a249a | blueswir1 | } |
4263 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4264 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4265 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4266 | 0f8a249a | blueswir1 | switch (xop) {
|
4267 | b89e94af | Blue Swirl | case 0x0: /* ld, V9 lduw, load unsigned word */ |
4268 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4269 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4270 | 0f8a249a | blueswir1 | break;
|
4271 | b89e94af | Blue Swirl | case 0x1: /* ldub, load unsigned byte */ |
4272 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4273 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4274 | 0f8a249a | blueswir1 | break;
|
4275 | b89e94af | Blue Swirl | case 0x2: /* lduh, load unsigned halfword */ |
4276 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4277 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4278 | 0f8a249a | blueswir1 | break;
|
4279 | b89e94af | Blue Swirl | case 0x3: /* ldd, load double word */ |
4280 | 0f8a249a | blueswir1 | if (rd & 1) |
4281 | d4218d99 | blueswir1 | goto illegal_insn;
|
4282 | 1a2fb1c0 | blueswir1 | else {
|
4283 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4284 | 2ea815ca | blueswir1 | |
4285 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4286 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4287 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4288 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4289 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4290 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4291 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4292 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4293 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4294 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4295 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4296 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4297 | 1a2fb1c0 | blueswir1 | } |
4298 | 0f8a249a | blueswir1 | break;
|
4299 | b89e94af | Blue Swirl | case 0x9: /* ldsb, load signed byte */ |
4300 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4301 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4302 | 0f8a249a | blueswir1 | break;
|
4303 | b89e94af | Blue Swirl | case 0xa: /* ldsh, load signed halfword */ |
4304 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4305 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4306 | 0f8a249a | blueswir1 | break;
|
4307 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4308 | 2ea815ca | blueswir1 | { |
4309 | 2ea815ca | blueswir1 | TCGv r_const; |
4310 | 2ea815ca | blueswir1 | |
4311 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4312 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4313 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4314 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4315 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4316 | 2ea815ca | blueswir1 | } |
4317 | 0f8a249a | blueswir1 | break;
|
4318 | b89e94af | Blue Swirl | case 0x0f: /* swap, swap register with memory. Also |
4319 | 77f193da | blueswir1 | atomically */
|
4320 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4321 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4322 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4323 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4324 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4325 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_val, cpu_tmp0); |
4326 | 0f8a249a | blueswir1 | break;
|
4327 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4328 | b89e94af | Blue Swirl | case 0x10: /* lda, V9 lduwa, load word alternate */ |
4329 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4330 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4331 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4332 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4333 | 0f8a249a | blueswir1 | goto priv_insn;
|
4334 | 6ea4a6c8 | blueswir1 | #endif
|
4335 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4336 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4337 | 0f8a249a | blueswir1 | break;
|
4338 | b89e94af | Blue Swirl | case 0x11: /* lduba, load unsigned byte alternate */ |
4339 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4340 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4341 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4342 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4343 | 0f8a249a | blueswir1 | goto priv_insn;
|
4344 | 0f8a249a | blueswir1 | #endif
|
4345 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4346 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4347 | 0f8a249a | blueswir1 | break;
|
4348 | b89e94af | Blue Swirl | case 0x12: /* lduha, load unsigned halfword alternate */ |
4349 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4350 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4351 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4352 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4353 | 0f8a249a | blueswir1 | goto priv_insn;
|
4354 | 6ea4a6c8 | blueswir1 | #endif
|
4355 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4356 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4357 | 0f8a249a | blueswir1 | break;
|
4358 | b89e94af | Blue Swirl | case 0x13: /* ldda, load double word alternate */ |
4359 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4360 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4361 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4362 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4363 | 0f8a249a | blueswir1 | goto priv_insn;
|
4364 | 3475187d | bellard | #endif
|
4365 | 0f8a249a | blueswir1 | if (rd & 1) |
4366 | d4218d99 | blueswir1 | goto illegal_insn;
|
4367 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4368 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4369 | db166940 | blueswir1 | goto skip_move;
|
4370 | b89e94af | Blue Swirl | case 0x19: /* ldsba, load signed byte alternate */ |
4371 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4372 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4373 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4374 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4375 | 0f8a249a | blueswir1 | goto priv_insn;
|
4376 | 0f8a249a | blueswir1 | #endif
|
4377 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4378 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4379 | 0f8a249a | blueswir1 | break;
|
4380 | b89e94af | Blue Swirl | case 0x1a: /* ldsha, load signed halfword alternate */ |
4381 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4382 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4383 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4384 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4385 | 0f8a249a | blueswir1 | goto priv_insn;
|
4386 | 6ea4a6c8 | blueswir1 | #endif
|
4387 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4388 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4389 | 0f8a249a | blueswir1 | break;
|
4390 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4391 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4392 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4393 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4394 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4395 | 0f8a249a | blueswir1 | goto priv_insn;
|
4396 | 0f8a249a | blueswir1 | #endif
|
4397 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4398 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4399 | 0f8a249a | blueswir1 | break;
|
4400 | b89e94af | Blue Swirl | case 0x1f: /* swapa, swap reg with alt. memory. Also |
4401 | 77f193da | blueswir1 | atomically */
|
4402 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4403 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4404 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4405 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4406 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4407 | 0f8a249a | blueswir1 | goto priv_insn;
|
4408 | 6ea4a6c8 | blueswir1 | #endif
|
4409 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4410 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4411 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4412 | 0f8a249a | blueswir1 | break;
|
4413 | 3475187d | bellard | |
4414 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4415 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4416 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4417 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4418 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4419 | 3475187d | bellard | #endif
|
4420 | 3475187d | bellard | #endif
|
4421 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4422 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4423 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4424 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4425 | 0f8a249a | blueswir1 | break;
|
4426 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4427 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4428 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4429 | 0f8a249a | blueswir1 | break;
|
4430 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4431 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4432 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4433 | 0f8a249a | blueswir1 | break;
|
4434 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4435 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4436 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4437 | 0f8a249a | blueswir1 | break;
|
4438 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4439 | 0f8a249a | blueswir1 | goto skip_move;
|
4440 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4441 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4442 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4443 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4444 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4445 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4446 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4447 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4448 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4449 | 0f8a249a | blueswir1 | goto skip_move;
|
4450 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4451 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4452 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4453 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4454 | 1f587329 | blueswir1 | goto skip_move;
|
4455 | 1f587329 | blueswir1 | #endif
|
4456 | 0f8a249a | blueswir1 | default:
|
4457 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4458 | 0f8a249a | blueswir1 | } |
4459 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4460 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4461 | 0f8a249a | blueswir1 | skip_move: ;
|
4462 | 3475187d | bellard | #endif
|
4463 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4464 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4465 | a80dde08 | bellard | goto jmp_insn;
|
4466 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4467 | 0f8a249a | blueswir1 | switch (xop) {
|
4468 | b89e94af | Blue Swirl | case 0x20: /* ldf, load fpreg */ |
4469 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4470 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4471 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
4472 | 0f8a249a | blueswir1 | break;
|
4473 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4474 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4475 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4476 | 3a3b925d | blueswir1 | if (rd == 1) { |
4477 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4478 | a7812ae4 | pbrook | gen_helper_ldxfsr(cpu_tmp64); |
4479 | 3a3b925d | blueswir1 | } else
|
4480 | 3a3b925d | blueswir1 | #else
|
4481 | 3a3b925d | blueswir1 | { |
4482 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4483 | a7812ae4 | pbrook | gen_helper_ldfsr(cpu_tmp32); |
4484 | 3a3b925d | blueswir1 | } |
4485 | 3a3b925d | blueswir1 | #endif
|
4486 | 0f8a249a | blueswir1 | break;
|
4487 | b89e94af | Blue Swirl | case 0x22: /* ldqf, load quad fpreg */ |
4488 | 2ea815ca | blueswir1 | { |
4489 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4490 | 2ea815ca | blueswir1 | |
4491 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4492 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4493 | 1295001c | Igor V. Kovalenko | gen_address_mask(dc, cpu_addr); |
4494 | a7812ae4 | pbrook | gen_helper_ldqf(cpu_addr, r_const); |
4495 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4496 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4497 | 2ea815ca | blueswir1 | } |
4498 | 1f587329 | blueswir1 | break;
|
4499 | b89e94af | Blue Swirl | case 0x23: /* lddf, load double fpreg */ |
4500 | 2ea815ca | blueswir1 | { |
4501 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4502 | 2ea815ca | blueswir1 | |
4503 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4504 | 1295001c | Igor V. Kovalenko | gen_address_mask(dc, cpu_addr); |
4505 | a7812ae4 | pbrook | gen_helper_lddf(cpu_addr, r_const); |
4506 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4507 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4508 | 2ea815ca | blueswir1 | } |
4509 | 0f8a249a | blueswir1 | break;
|
4510 | 0f8a249a | blueswir1 | default:
|
4511 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4512 | 0f8a249a | blueswir1 | } |
4513 | dc1a6971 | Blue Swirl | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || |
4514 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4515 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4516 | 0f8a249a | blueswir1 | switch (xop) {
|
4517 | b89e94af | Blue Swirl | case 0x4: /* st, store word */ |
4518 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4519 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4520 | 0f8a249a | blueswir1 | break;
|
4521 | b89e94af | Blue Swirl | case 0x5: /* stb, store byte */ |
4522 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4523 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4524 | 0f8a249a | blueswir1 | break;
|
4525 | b89e94af | Blue Swirl | case 0x6: /* sth, store halfword */ |
4526 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4527 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4528 | 0f8a249a | blueswir1 | break;
|
4529 | b89e94af | Blue Swirl | case 0x7: /* std, store double word */ |
4530 | 0f8a249a | blueswir1 | if (rd & 1) |
4531 | d4218d99 | blueswir1 | goto illegal_insn;
|
4532 | 1a2fb1c0 | blueswir1 | else {
|
4533 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4534 | 1a2fb1c0 | blueswir1 | |
4535 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4536 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4537 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4538 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4539 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4540 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
4541 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); |
4542 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4543 | 7fa76c0b | blueswir1 | } |
4544 | 0f8a249a | blueswir1 | break;
|
4545 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4546 | b89e94af | Blue Swirl | case 0x14: /* sta, V9 stwa, store word alternate */ |
4547 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4548 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4549 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4550 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4551 | 0f8a249a | blueswir1 | goto priv_insn;
|
4552 | 3475187d | bellard | #endif
|
4553 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4554 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4555 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4556 | d39c0b99 | bellard | break;
|
4557 | b89e94af | Blue Swirl | case 0x15: /* stba, store byte alternate */ |
4558 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4559 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4560 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4561 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4562 | 0f8a249a | blueswir1 | goto priv_insn;
|
4563 | 3475187d | bellard | #endif
|
4564 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4565 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4566 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4567 | d39c0b99 | bellard | break;
|
4568 | b89e94af | Blue Swirl | case 0x16: /* stha, store halfword alternate */ |
4569 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4570 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4571 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4572 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4573 | 0f8a249a | blueswir1 | goto priv_insn;
|
4574 | 3475187d | bellard | #endif
|
4575 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4576 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4577 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4578 | d39c0b99 | bellard | break;
|
4579 | b89e94af | Blue Swirl | case 0x17: /* stda, store double word alternate */ |
4580 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4581 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4582 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4583 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4584 | 0f8a249a | blueswir1 | goto priv_insn;
|
4585 | 3475187d | bellard | #endif
|
4586 | 0f8a249a | blueswir1 | if (rd & 1) |
4587 | d4218d99 | blueswir1 | goto illegal_insn;
|
4588 | 1a2fb1c0 | blueswir1 | else {
|
4589 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4590 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4591 | 1a2fb1c0 | blueswir1 | } |
4592 | d39c0b99 | bellard | break;
|
4593 | e80cfcfc | bellard | #endif
|
4594 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4595 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4596 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4597 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4598 | 0f8a249a | blueswir1 | break;
|
4599 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4600 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4601 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4602 | 9fd1ae3a | Igor V. Kovalenko | dc->npc = DYNAMIC_PC; |
4603 | 0f8a249a | blueswir1 | break;
|
4604 | 3475187d | bellard | #endif
|
4605 | 0f8a249a | blueswir1 | default:
|
4606 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4607 | 0f8a249a | blueswir1 | } |
4608 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4609 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4610 | a80dde08 | bellard | goto jmp_insn;
|
4611 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4612 | 0f8a249a | blueswir1 | switch (xop) {
|
4613 | b89e94af | Blue Swirl | case 0x24: /* stf, store fpreg */ |
4614 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4615 | 527067d8 | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); |
4616 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); |
4617 | 0f8a249a | blueswir1 | break;
|
4618 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4619 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4620 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4621 | 3a3b925d | blueswir1 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4622 | 3a3b925d | blueswir1 | if (rd == 1) |
4623 | 3a3b925d | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4624 | 527067d8 | blueswir1 | else
|
4625 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx); |
4626 | 3a3b925d | blueswir1 | #else
|
4627 | 3a3b925d | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); |
4628 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4629 | 3a3b925d | blueswir1 | #endif
|
4630 | 0f8a249a | blueswir1 | break;
|
4631 | 1f587329 | blueswir1 | case 0x26: |
4632 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4633 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4634 | 2ea815ca | blueswir1 | { |
4635 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4636 | 2ea815ca | blueswir1 | |
4637 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4638 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4639 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4640 | 1295001c | Igor V. Kovalenko | gen_address_mask(dc, cpu_addr); |
4641 | a7812ae4 | pbrook | gen_helper_stqf(cpu_addr, r_const); |
4642 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4643 | 2ea815ca | blueswir1 | } |
4644 | 1f587329 | blueswir1 | break;
|
4645 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4646 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4647 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4648 | 1f587329 | blueswir1 | goto illegal_insn;
|
4649 | 1f587329 | blueswir1 | #else
|
4650 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4651 | 0f8a249a | blueswir1 | goto priv_insn;
|
4652 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4653 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4654 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4655 | 0f8a249a | blueswir1 | #endif
|
4656 | 1f587329 | blueswir1 | #endif
|
4657 | b89e94af | Blue Swirl | case 0x27: /* stdf, store double fpreg */ |
4658 | 2ea815ca | blueswir1 | { |
4659 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4660 | 2ea815ca | blueswir1 | |
4661 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4662 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4663 | 1295001c | Igor V. Kovalenko | gen_address_mask(dc, cpu_addr); |
4664 | a7812ae4 | pbrook | gen_helper_stdf(cpu_addr, r_const); |
4665 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4666 | 2ea815ca | blueswir1 | } |
4667 | 0f8a249a | blueswir1 | break;
|
4668 | 0f8a249a | blueswir1 | default:
|
4669 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4670 | 0f8a249a | blueswir1 | } |
4671 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4672 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4673 | 0f8a249a | blueswir1 | switch (xop) {
|
4674 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4675 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4676 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4677 | 0f8a249a | blueswir1 | break;
|
4678 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4679 | 2ea815ca | blueswir1 | { |
4680 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4681 | 2ea815ca | blueswir1 | |
4682 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4683 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4684 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); |
4685 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4686 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4687 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4688 | 2ea815ca | blueswir1 | } |
4689 | 1f587329 | blueswir1 | break;
|
4690 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4691 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4692 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4693 | 0f8a249a | blueswir1 | break;
|
4694 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4695 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4696 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4697 | 0f8a249a | blueswir1 | break;
|
4698 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4699 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4700 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4701 | 0f8a249a | blueswir1 | break;
|
4702 | a4d17f19 | blueswir1 | #else
|
4703 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4704 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4705 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4706 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4707 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4708 | 0f8a249a | blueswir1 | #endif
|
4709 | 0f8a249a | blueswir1 | default:
|
4710 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4711 | 0f8a249a | blueswir1 | } |
4712 | dc1a6971 | Blue Swirl | } else
|
4713 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4714 | 0f8a249a | blueswir1 | } |
4715 | 0f8a249a | blueswir1 | break;
|
4716 | cf495bcf | bellard | } |
4717 | cf495bcf | bellard | /* default case for non jump instructions */
|
4718 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4719 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4720 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4721 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4722 | 72cbca10 | bellard | /* we can do a static jump */
|
4723 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4724 | 72cbca10 | bellard | dc->is_br = 1;
|
4725 | 72cbca10 | bellard | } else {
|
4726 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4727 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4728 | cf495bcf | bellard | } |
4729 | e80cfcfc | bellard | jmp_insn:
|
4730 | 42a8aa83 | Richard Henderson | goto egress;
|
4731 | cf495bcf | bellard | illegal_insn:
|
4732 | 2ea815ca | blueswir1 | { |
4733 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4734 | 2ea815ca | blueswir1 | |
4735 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4736 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4737 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4738 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4739 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4740 | 2ea815ca | blueswir1 | } |
4741 | 42a8aa83 | Richard Henderson | goto egress;
|
4742 | 64a88d5d | blueswir1 | unimp_flush:
|
4743 | 2ea815ca | blueswir1 | { |
4744 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4745 | 2ea815ca | blueswir1 | |
4746 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4747 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4748 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4749 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4750 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4751 | 2ea815ca | blueswir1 | } |
4752 | 42a8aa83 | Richard Henderson | goto egress;
|
4753 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4754 | e8af50a3 | bellard | priv_insn:
|
4755 | 2ea815ca | blueswir1 | { |
4756 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4757 | 2ea815ca | blueswir1 | |
4758 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4759 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4760 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4761 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4762 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4763 | 2ea815ca | blueswir1 | } |
4764 | 42a8aa83 | Richard Henderson | goto egress;
|
4765 | 64a88d5d | blueswir1 | #endif
|
4766 | e80cfcfc | bellard | nfpu_insn:
|
4767 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4768 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4769 | e80cfcfc | bellard | dc->is_br = 1;
|
4770 | 42a8aa83 | Richard Henderson | goto egress;
|
4771 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4772 | 9143e598 | blueswir1 | nfq_insn:
|
4773 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4774 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4775 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4776 | 42a8aa83 | Richard Henderson | goto egress;
|
4777 | 9143e598 | blueswir1 | #endif
|
4778 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4779 | fcc72045 | blueswir1 | ncp_insn:
|
4780 | 2ea815ca | blueswir1 | { |
4781 | 2ea815ca | blueswir1 | TCGv r_const; |
4782 | 2ea815ca | blueswir1 | |
4783 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4784 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4785 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4786 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4787 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4788 | 2ea815ca | blueswir1 | } |
4789 | 42a8aa83 | Richard Henderson | goto egress;
|
4790 | fcc72045 | blueswir1 | #endif
|
4791 | 42a8aa83 | Richard Henderson | egress:
|
4792 | 42a8aa83 | Richard Henderson | tcg_temp_free(cpu_tmp1); |
4793 | 42a8aa83 | Richard Henderson | tcg_temp_free(cpu_tmp2); |
4794 | 7a3f1944 | bellard | } |
4795 | 7a3f1944 | bellard | |
4796 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4797 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4798 | 7a3f1944 | bellard | { |
4799 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4800 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4801 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4802 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
4803 | e8af50a3 | bellard | int j, lj = -1; |
4804 | 2e70f6ef | pbrook | int num_insns;
|
4805 | 2e70f6ef | pbrook | int max_insns;
|
4806 | cf495bcf | bellard | |
4807 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4808 | cf495bcf | bellard | dc->tb = tb; |
4809 | 72cbca10 | bellard | pc_start = tb->pc; |
4810 | cf495bcf | bellard | dc->pc = pc_start; |
4811 | e80cfcfc | bellard | last_pc = dc->pc; |
4812 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4813 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_DYNAMIC; |
4814 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4815 | 5578ceab | blueswir1 | dc->def = env->def; |
4816 | 5578ceab | blueswir1 | if ((dc->def->features & CPU_FEATURE_FLOAT))
|
4817 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4818 | 5578ceab | blueswir1 | else
|
4819 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4820 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4821 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4822 | 2cade6a3 | blueswir1 | #endif
|
4823 | 060718c1 | Richard Henderson | dc->singlestep = (env->singlestep_enabled || singlestep); |
4824 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4825 | cf495bcf | bellard | |
4826 | a7812ae4 | pbrook | cpu_tmp0 = tcg_temp_new(); |
4827 | a7812ae4 | pbrook | cpu_tmp32 = tcg_temp_new_i32(); |
4828 | a7812ae4 | pbrook | cpu_tmp64 = tcg_temp_new_i64(); |
4829 | d987963a | blueswir1 | |
4830 | a7812ae4 | pbrook | cpu_dst = tcg_temp_local_new(); |
4831 | d987963a | blueswir1 | |
4832 | d987963a | blueswir1 | // loads and stores
|
4833 | a7812ae4 | pbrook | cpu_val = tcg_temp_local_new(); |
4834 | a7812ae4 | pbrook | cpu_addr = tcg_temp_local_new(); |
4835 | 1a2fb1c0 | blueswir1 | |
4836 | 2e70f6ef | pbrook | num_insns = 0;
|
4837 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4838 | 2e70f6ef | pbrook | if (max_insns == 0) |
4839 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4840 | 2e70f6ef | pbrook | gen_icount_start(); |
4841 | cf495bcf | bellard | do {
|
4842 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
4843 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
4844 | a1d1bb31 | aliguori | if (bp->pc == dc->pc) {
|
4845 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4846 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4847 | a7812ae4 | pbrook | gen_helper_debug(); |
4848 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4849 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4850 | e80cfcfc | bellard | goto exit_gen_loop;
|
4851 | e8af50a3 | bellard | } |
4852 | e8af50a3 | bellard | } |
4853 | e8af50a3 | bellard | } |
4854 | e8af50a3 | bellard | if (spc) {
|
4855 | 93fcfe39 | aliguori | qemu_log("Search PC...\n");
|
4856 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4857 | e8af50a3 | bellard | if (lj < j) {
|
4858 | e8af50a3 | bellard | lj++; |
4859 | e8af50a3 | bellard | while (lj < j)
|
4860 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4861 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4862 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4863 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4864 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
4865 | e8af50a3 | bellard | } |
4866 | e8af50a3 | bellard | } |
4867 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4868 | 2e70f6ef | pbrook | gen_io_start(); |
4869 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4870 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4871 | 2e70f6ef | pbrook | num_insns++; |
4872 | 0f8a249a | blueswir1 | |
4873 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4874 | 0f8a249a | blueswir1 | break;
|
4875 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4876 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4877 | 0f8a249a | blueswir1 | break;
|
4878 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4879 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4880 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4881 | d39c0b99 | bellard | break;
|
4882 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4883 | e80cfcfc | bellard | generate an exception */
|
4884 | 060718c1 | Richard Henderson | if (dc->singlestep) {
|
4885 | e80cfcfc | bellard | break;
|
4886 | e80cfcfc | bellard | } |
4887 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4888 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
4889 | 2e70f6ef | pbrook | num_insns < max_insns); |
4890 | e80cfcfc | bellard | |
4891 | e80cfcfc | bellard | exit_gen_loop:
|
4892 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
4893 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
4894 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
4895 | a7812ae4 | pbrook | tcg_temp_free_i64(cpu_tmp64); |
4896 | a7812ae4 | pbrook | tcg_temp_free_i32(cpu_tmp32); |
4897 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
4898 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
4899 | 2e70f6ef | pbrook | gen_io_end(); |
4900 | 72cbca10 | bellard | if (!dc->is_br) {
|
4901 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4902 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4903 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4904 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
4905 | 72cbca10 | bellard | } else {
|
4906 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4907 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4908 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
4909 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4910 | 72cbca10 | bellard | } |
4911 | 72cbca10 | bellard | } |
4912 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
4913 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4914 | e8af50a3 | bellard | if (spc) {
|
4915 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4916 | e8af50a3 | bellard | lj++; |
4917 | e8af50a3 | bellard | while (lj <= j)
|
4918 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4919 | e8af50a3 | bellard | #if 0
|
4920 | 93fcfe39 | aliguori | log_page_dump();
|
4921 | e8af50a3 | bellard | #endif
|
4922 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4923 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4924 | e8af50a3 | bellard | } else {
|
4925 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4926 | 2e70f6ef | pbrook | tb->icount = num_insns; |
4927 | e8af50a3 | bellard | } |
4928 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4929 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
4930 | 93fcfe39 | aliguori | qemu_log("--------------\n");
|
4931 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
4932 | 93fcfe39 | aliguori | log_target_disas(pc_start, last_pc + 4 - pc_start, 0); |
4933 | 93fcfe39 | aliguori | qemu_log("\n");
|
4934 | cf495bcf | bellard | } |
4935 | 7a3f1944 | bellard | #endif
|
4936 | 7a3f1944 | bellard | } |
4937 | 7a3f1944 | bellard | |
4938 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4939 | 7a3f1944 | bellard | { |
4940 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
4941 | 7a3f1944 | bellard | } |
4942 | 7a3f1944 | bellard | |
4943 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4944 | 7a3f1944 | bellard | { |
4945 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
4946 | 7a3f1944 | bellard | } |
4947 | 7a3f1944 | bellard | |
4948 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
4949 | e80cfcfc | bellard | { |
4950 | f5069b26 | blueswir1 | unsigned int i; |
4951 | c48fcb47 | blueswir1 | static int inited; |
4952 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4953 | f5069b26 | blueswir1 | NULL, // g0 not used |
4954 | f5069b26 | blueswir1 | "g1",
|
4955 | f5069b26 | blueswir1 | "g2",
|
4956 | f5069b26 | blueswir1 | "g3",
|
4957 | f5069b26 | blueswir1 | "g4",
|
4958 | f5069b26 | blueswir1 | "g5",
|
4959 | f5069b26 | blueswir1 | "g6",
|
4960 | f5069b26 | blueswir1 | "g7",
|
4961 | f5069b26 | blueswir1 | }; |
4962 | 714547bb | blueswir1 | static const char * const fregnames[64] = { |
4963 | 714547bb | blueswir1 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
4964 | 714547bb | blueswir1 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
4965 | 714547bb | blueswir1 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
4966 | 714547bb | blueswir1 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
4967 | 714547bb | blueswir1 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
4968 | 714547bb | blueswir1 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
4969 | 714547bb | blueswir1 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
4970 | 714547bb | blueswir1 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
4971 | 714547bb | blueswir1 | }; |
4972 | aaed909a | bellard | |
4973 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4974 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4975 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4976 | 1a2fb1c0 | blueswir1 | |
4977 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
4978 | a7812ae4 | pbrook | cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, |
4979 | a7812ae4 | pbrook | offsetof(CPUState, regwptr), |
4980 | a7812ae4 | pbrook | "regwptr");
|
4981 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4982 | a7812ae4 | pbrook | cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc), |
4983 | a7812ae4 | pbrook | "xcc");
|
4984 | a7812ae4 | pbrook | cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi), |
4985 | a7812ae4 | pbrook | "asi");
|
4986 | a7812ae4 | pbrook | cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs), |
4987 | a7812ae4 | pbrook | "fprs");
|
4988 | a7812ae4 | pbrook | cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr), |
4989 | 255e1fcb | blueswir1 | "gsr");
|
4990 | a7812ae4 | pbrook | cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4991 | 255e1fcb | blueswir1 | offsetof(CPUState, tick_cmpr), |
4992 | 255e1fcb | blueswir1 | "tick_cmpr");
|
4993 | a7812ae4 | pbrook | cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4994 | 255e1fcb | blueswir1 | offsetof(CPUState, stick_cmpr), |
4995 | 255e1fcb | blueswir1 | "stick_cmpr");
|
4996 | a7812ae4 | pbrook | cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4997 | 255e1fcb | blueswir1 | offsetof(CPUState, hstick_cmpr), |
4998 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
4999 | a7812ae4 | pbrook | cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp), |
5000 | 255e1fcb | blueswir1 | "hintp");
|
5001 | a7812ae4 | pbrook | cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba), |
5002 | a7812ae4 | pbrook | "htba");
|
5003 | a7812ae4 | pbrook | cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver), |
5004 | a7812ae4 | pbrook | "hver");
|
5005 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new(TCG_AREG0, |
5006 | 255e1fcb | blueswir1 | offsetof(CPUState, ssr), "ssr");
|
5007 | a7812ae4 | pbrook | cpu_ver = tcg_global_mem_new(TCG_AREG0, |
5008 | 255e1fcb | blueswir1 | offsetof(CPUState, version), "ver");
|
5009 | a7812ae4 | pbrook | cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, |
5010 | a7812ae4 | pbrook | offsetof(CPUState, softint), |
5011 | a7812ae4 | pbrook | "softint");
|
5012 | 255e1fcb | blueswir1 | #else
|
5013 | a7812ae4 | pbrook | cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), |
5014 | 255e1fcb | blueswir1 | "wim");
|
5015 | 1a2fb1c0 | blueswir1 | #endif
|
5016 | a7812ae4 | pbrook | cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), |
5017 | 77f193da | blueswir1 | "cond");
|
5018 | a7812ae4 | pbrook | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), |
5019 | dc99a3f2 | blueswir1 | "cc_src");
|
5020 | a7812ae4 | pbrook | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, |
5021 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
5022 | d9bdab86 | blueswir1 | "cc_src2");
|
5023 | a7812ae4 | pbrook | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), |
5024 | dc99a3f2 | blueswir1 | "cc_dst");
|
5025 | 8393617c | Blue Swirl | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), |
5026 | 8393617c | Blue Swirl | "cc_op");
|
5027 | a7812ae4 | pbrook | cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr), |
5028 | a7812ae4 | pbrook | "psr");
|
5029 | a7812ae4 | pbrook | cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr), |
5030 | 87e92502 | blueswir1 | "fsr");
|
5031 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc), |
5032 | 48d5c82b | blueswir1 | "pc");
|
5033 | a7812ae4 | pbrook | cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc), |
5034 | a7812ae4 | pbrook | "npc");
|
5035 | a7812ae4 | pbrook | cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
|
5036 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
5037 | a7812ae4 | pbrook | cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr), |
5038 | 255e1fcb | blueswir1 | "tbr");
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5039 | 255e1fcb | blueswir1 | #endif
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5040 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
5041 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, |
5042 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
5043 | f5069b26 | blueswir1 | gregnames[i]); |
5044 | 714547bb | blueswir1 | for (i = 0; i < TARGET_FPREGS; i++) |
5045 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, |
5046 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), |
5047 | a7812ae4 | pbrook | fregnames[i]); |
5048 | 714547bb | blueswir1 | |
5049 | c9e03d8f | blueswir1 | /* register helpers */
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5050 | c9e03d8f | blueswir1 | |
5051 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
5052 | c9e03d8f | blueswir1 | #include "helper.h" |
5053 | 1a2fb1c0 | blueswir1 | } |
5054 | 658138bc | bellard | } |
5055 | d2856f1a | aurel32 | |
5056 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
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5057 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
5058 | d2856f1a | aurel32 | { |
5059 | d2856f1a | aurel32 | target_ulong npc; |
5060 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
5061 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
5062 | d2856f1a | aurel32 | if (npc == 1) { |
5063 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
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5064 | d2856f1a | aurel32 | } else if (npc == 2) { |
5065 | d7da2a10 | Blue Swirl | /* jump PC: use 'cond' and the jump targets of the translation */
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5066 | d7da2a10 | Blue Swirl | if (env->cond) {
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5067 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
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5068 | d7da2a10 | Blue Swirl | } else {
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5069 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
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5070 | d7da2a10 | Blue Swirl | } |
5071 | d2856f1a | aurel32 | } else {
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5072 | d2856f1a | aurel32 | env->npc = npc; |
5073 | d2856f1a | aurel32 | } |
5074 | 14ed7adc | Igor Kovalenko | |
5075 | 14ed7adc | Igor Kovalenko | /* flush pending conditional evaluations before exposing cpu state */
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5076 | 14ed7adc | Igor Kovalenko | if (CC_OP != CC_OP_FLAGS) {
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5077 | 14ed7adc | Igor Kovalenko | helper_compute_psr(); |
5078 | 14ed7adc | Igor Kovalenko | } |
5079 | d2856f1a | aurel32 | } |