| 247 |
247 |
return addr;
|
| 248 |
248 |
}
|
| 249 |
249 |
|
|
250 |
/* returns true if access using this ASI is to have address translated by MMU
|
|
251 |
otherwise access is to raw physical address */
|
|
252 |
static inline int is_translating_asi(int asi)
|
|
253 |
{
|
|
254 |
#ifdef TARGET_SPARC64
|
|
255 |
/* Ultrasparc IIi translating asi
|
|
256 |
- note this list is defined by cpu implementation
|
|
257 |
*/
|
|
258 |
switch (asi) {
|
|
259 |
case 0x04 ... 0x11:
|
|
260 |
case 0x18 ... 0x19:
|
|
261 |
case 0x24 ... 0x2C:
|
|
262 |
case 0x70 ... 0x73:
|
|
263 |
case 0x78 ... 0x79:
|
|
264 |
case 0x80 ... 0xFF:
|
|
265 |
return 1;
|
|
266 |
|
|
267 |
default:
|
|
268 |
return 0;
|
|
269 |
}
|
|
270 |
#else
|
|
271 |
/* TODO: check sparc32 bits */
|
|
272 |
return 0;
|
|
273 |
#endif
|
|
274 |
}
|
|
275 |
|
|
276 |
static inline target_ulong asi_address_mask(CPUState *env1,
|
|
277 |
int asi, target_ulong addr)
|
|
278 |
{
|
|
279 |
if (is_translating_asi(asi)) {
|
|
280 |
return address_mask(env, addr);
|
|
281 |
} else {
|
|
282 |
return addr;
|
|
283 |
}
|
|
284 |
}
|
|
285 |
|
| 250 |
286 |
static void raise_exception(int tt)
|
| 251 |
287 |
{
|
| 252 |
288 |
env->exception_index = tt;
|
| ... | ... | |
| 2151 |
2187 |
raise_exception(TT_PRIV_ACT);
|
| 2152 |
2188 |
|
| 2153 |
2189 |
helper_check_align(addr, size - 1);
|
| 2154 |
|
addr = address_mask(env, addr);
|
|
2190 |
addr = asi_address_mask(env, asi, addr);
|
| 2155 |
2191 |
|
| 2156 |
2192 |
switch (asi) {
|
| 2157 |
2193 |
case 0x82: // Primary no-fault
|
| ... | ... | |
| 2254 |
2290 |
raise_exception(TT_PRIV_ACT);
|
| 2255 |
2291 |
|
| 2256 |
2292 |
helper_check_align(addr, size - 1);
|
| 2257 |
|
addr = address_mask(env, addr);
|
|
2293 |
addr = asi_address_mask(env, asi, addr);
|
| 2258 |
2294 |
|
| 2259 |
2295 |
/* Convert to little endian */
|
| 2260 |
2296 |
switch (asi) {
|
| ... | ... | |
| 2331 |
2367 |
raise_exception(TT_PRIV_ACT);
|
| 2332 |
2368 |
|
| 2333 |
2369 |
helper_check_align(addr, size - 1);
|
|
2370 |
addr = asi_address_mask(env, asi, addr);
|
|
2371 |
|
| 2334 |
2372 |
switch (asi) {
|
| 2335 |
2373 |
case 0x82: // Primary no-fault
|
| 2336 |
2374 |
case 0x8a: // Primary no-fault LE
|
| ... | ... | |
| 2682 |
2720 |
raise_exception(TT_PRIV_ACT);
|
| 2683 |
2721 |
|
| 2684 |
2722 |
helper_check_align(addr, size - 1);
|
|
2723 |
addr = asi_address_mask(env, asi, addr);
|
|
2724 |
|
| 2685 |
2725 |
/* Convert to little endian */
|
| 2686 |
2726 |
switch (asi) {
|
| 2687 |
2727 |
case 0x0c: // Nucleus Little Endian (LE)
|
| ... | ... | |
| 3056 |
3096 |
&& !(env->hpstate & HS_PRIV)))
|
| 3057 |
3097 |
raise_exception(TT_PRIV_ACT);
|
| 3058 |
3098 |
|
|
3099 |
addr = asi_address_mask(env, asi, addr);
|
|
3100 |
|
| 3059 |
3101 |
switch (asi) {
|
| 3060 |
3102 |
#if !defined(CONFIG_USER_ONLY)
|
| 3061 |
3103 |
case 0x24: // Nucleus quad LDD 128 bit atomic
|
| ... | ... | |
| 3103 |
3145 |
target_ulong val;
|
| 3104 |
3146 |
|
| 3105 |
3147 |
helper_check_align(addr, 3);
|
|
3148 |
addr = asi_address_mask(env, asi, addr);
|
|
3149 |
|
| 3106 |
3150 |
switch (asi) {
|
| 3107 |
3151 |
case 0xf0: // Block load primary
|
| 3108 |
3152 |
case 0xf1: // Block load secondary
|
| ... | ... | |
| 3145 |
3189 |
target_ulong val = 0;
|
| 3146 |
3190 |
|
| 3147 |
3191 |
helper_check_align(addr, 3);
|
|
3192 |
addr = asi_address_mask(env, asi, addr);
|
|
3193 |
|
| 3148 |
3194 |
switch (asi) {
|
| 3149 |
3195 |
case 0xe0: // UA2007 Block commit store primary (cache flush)
|
| 3150 |
3196 |
case 0xe1: // UA2007 Block commit store secondary (cache flush)
|