Revision 12de9a39 target-ppc/translate_init.c
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 3095 | 3095 |
/* Non-embedded PowerPC */ |
| 3096 | 3096 |
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC */ |
| 3097 | 3097 |
#define POWERPC_INSNS_6xx (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \ |
| 3098 |
PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
|
|
| 3098 |
PPC_MEM_EIEIO | PPC_MEM_TLBIE) |
|
| 3099 | 3099 |
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602 */ |
| 3100 | 3100 |
#define POWERPC_INSNS_WORKS (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \ |
| 3101 | 3101 |
PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \ |
| 3102 | 3102 |
PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \ |
| 3103 |
PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB) |
|
| 3103 |
PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ | PPC_MFTB | \ |
|
| 3104 |
PPC_SEGMENT) |
|
| 3104 | 3105 |
|
| 3105 | 3106 |
/* POWER : same as 601, without mfmsr, mfsr */ |
| 3106 | 3107 |
#if defined(TODO) |
| ... | ... | |
| 3111 | 3112 |
|
| 3112 | 3113 |
/* PowerPC 601 */ |
| 3113 | 3114 |
#define POWERPC_INSNS_601 (POWERPC_INSNS_6xx | PPC_CACHE_DCBZ | \ |
| 3114 |
PPC_EXTERN | PPC_POWER_BR) |
|
| 3115 |
PPC_SEGMENT | PPC_EXTERN | PPC_POWER_BR)
|
|
| 3115 | 3116 |
#define POWERPC_MSRM_601 (0x000000000000FE70ULL) |
| 3116 | 3117 |
//#define POWERPC_MMU_601 (POWERPC_MMU_601) |
| 3117 | 3118 |
//#define POWERPC_EXCP_601 (POWERPC_EXCP_601) |
| ... | ... | |
| 3164 | 3165 |
PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \ |
| 3165 | 3166 |
PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \ |
| 3166 | 3167 |
PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_CACHE_DCBZ |\ |
| 3167 |
PPC_602_SPEC) |
|
| 3168 |
PPC_SEGMENT | PPC_602_SPEC)
|
|
| 3168 | 3169 |
#define POWERPC_MSRM_602 (0x000000000033FF73ULL) |
| 3169 | 3170 |
#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx) |
| 3170 | 3171 |
//#define POWERPC_EXCP_602 (POWERPC_EXCP_602) |
| ... | ... | |
| 3942 | 3943 |
|
| 3943 | 3944 |
#if defined (TARGET_PPC64) |
| 3944 | 3945 |
#define POWERPC_INSNS_WORK64 (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT | \ |
| 3945 |
PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
|
|
| 3946 |
PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
|
|
| 3947 |
PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB) |
|
| 3946 |
PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE | \
|
|
| 3947 |
PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX | \
|
|
| 3948 |
PPC_MEM_TLBSYNC | PPC_CACHE_DCBZT | PPC_MFTB)
|
|
| 3948 | 3949 |
/* PowerPC 970 */ |
| 3949 | 3950 |
#define POWERPC_INSNS_970 (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ |
| 3950 | 3951 |
PPC_64B | PPC_ALTIVEC | \ |
| 3951 |
PPC_64_BRIDGE | PPC_SLBI)
|
|
| 3952 |
PPC_SEGMENT_64B | PPC_SLBI)
|
|
| 3952 | 3953 |
#define POWERPC_MSRM_970 (0x900000000204FF36ULL) |
| 3953 |
#define POWERPC_MMU_970 (POWERPC_MMU_64BRIDGE)
|
|
| 3954 |
#define POWERPC_MMU_970 (POWERPC_MMU_64B) |
|
| 3954 | 3955 |
//#define POWERPC_EXCP_970 (POWERPC_EXCP_970) |
| 3955 | 3956 |
#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970) |
| 3956 | 3957 |
#define POWERPC_BFDM_970 (bfd_mach_ppc64) |
| ... | ... | |
| 3990 | 3991 |
/* Memory management */ |
| 3991 | 3992 |
/* XXX: not correct */ |
| 3992 | 3993 |
gen_low_BATs(env); |
| 3993 |
#if 0 // TODO |
|
| 3994 |
env->slb_nr = 32; |
|
| 3994 |
/* XXX : not implemented */ |
|
| 3995 |
spr_register(env, SPR_MMUCFG, "MMUCFG", |
|
| 3996 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 3997 |
&spr_read_generic, SPR_NOACCESS, |
|
| 3998 |
0x00000000); /* TOFIX */ |
|
| 3999 |
/* XXX : not implemented */ |
|
| 4000 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0", |
|
| 4001 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4002 |
&spr_read_generic, &spr_write_generic, |
|
| 4003 |
0x00000000); /* TOFIX */ |
|
| 4004 |
spr_register(env, SPR_HIOR, "SPR_HIOR", |
|
| 4005 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4006 |
&spr_read_generic, &spr_write_generic, |
|
| 4007 |
0xFFF00000); /* XXX: This is a hack */ |
|
| 4008 |
#if !defined(CONFIG_USER_ONLY) |
|
| 4009 |
env->excp_prefix = 0xFFF00000; |
|
| 3995 | 4010 |
#endif |
| 4011 |
env->slb_nr = 32; |
|
| 3996 | 4012 |
init_excp_970(env); |
| 3997 | 4013 |
env->dcache_line_size = 128; |
| 3998 | 4014 |
env->icache_line_size = 128; |
| ... | ... | |
| 4003 | 4019 |
/* PowerPC 970FX (aka G5) */ |
| 4004 | 4020 |
#define POWERPC_INSNS_970FX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ |
| 4005 | 4021 |
PPC_64B | PPC_ALTIVEC | \ |
| 4006 |
PPC_64_BRIDGE | PPC_SLBI)
|
|
| 4022 |
PPC_SEGMENT_64B | PPC_SLBI)
|
|
| 4007 | 4023 |
#define POWERPC_MSRM_970FX (0x800000000204FF36ULL) |
| 4008 |
#define POWERPC_MMU_970FX (POWERPC_MMU_64BRIDGE)
|
|
| 4024 |
#define POWERPC_MMU_970FX (POWERPC_MMU_64B) |
|
| 4009 | 4025 |
#define POWERPC_EXCP_970FX (POWERPC_EXCP_970) |
| 4010 | 4026 |
#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970) |
| 4011 | 4027 |
#define POWERPC_BFDM_970FX (bfd_mach_ppc64) |
| ... | ... | |
| 4045 | 4061 |
/* Memory management */ |
| 4046 | 4062 |
/* XXX: not correct */ |
| 4047 | 4063 |
gen_low_BATs(env); |
| 4048 |
#if 0 // TODO |
|
| 4049 |
env->slb_nr = 32; |
|
| 4064 |
/* XXX : not implemented */ |
|
| 4065 |
spr_register(env, SPR_MMUCFG, "MMUCFG", |
|
| 4066 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4067 |
&spr_read_generic, SPR_NOACCESS, |
|
| 4068 |
0x00000000); /* TOFIX */ |
|
| 4069 |
/* XXX : not implemented */ |
|
| 4070 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0", |
|
| 4071 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4072 |
&spr_read_generic, &spr_write_generic, |
|
| 4073 |
0x00000000); /* TOFIX */ |
|
| 4074 |
spr_register(env, SPR_HIOR, "SPR_HIOR", |
|
| 4075 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4076 |
&spr_read_generic, &spr_write_generic, |
|
| 4077 |
0xFFF00000); /* XXX: This is a hack */ |
|
| 4078 |
#if !defined(CONFIG_USER_ONLY) |
|
| 4079 |
env->excp_prefix = 0xFFF00000; |
|
| 4050 | 4080 |
#endif |
| 4081 |
env->slb_nr = 32; |
|
| 4051 | 4082 |
init_excp_970(env); |
| 4052 | 4083 |
env->dcache_line_size = 128; |
| 4053 | 4084 |
env->icache_line_size = 128; |
| ... | ... | |
| 4058 | 4089 |
/* PowerPC 970 GX */ |
| 4059 | 4090 |
#define POWERPC_INSNS_970GX (POWERPC_INSNS_WORK64 | PPC_FLOAT_FSQRT | \ |
| 4060 | 4091 |
PPC_64B | PPC_ALTIVEC | \ |
| 4061 |
PPC_64_BRIDGE | PPC_SLBI)
|
|
| 4092 |
PPC_SEGMENT_64B | PPC_SLBI)
|
|
| 4062 | 4093 |
#define POWERPC_MSRM_970GX (0x800000000204FF36ULL) |
| 4063 |
#define POWERPC_MMU_970GX (POWERPC_MMU_64BRIDGE)
|
|
| 4094 |
#define POWERPC_MMU_970GX (POWERPC_MMU_64B) |
|
| 4064 | 4095 |
#define POWERPC_EXCP_970GX (POWERPC_EXCP_970) |
| 4065 | 4096 |
#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970) |
| 4066 | 4097 |
#define POWERPC_BFDM_970GX (bfd_mach_ppc64) |
| ... | ... | |
| 4100 | 4131 |
/* Memory management */ |
| 4101 | 4132 |
/* XXX: not correct */ |
| 4102 | 4133 |
gen_low_BATs(env); |
| 4103 |
#if 0 // TODO |
|
| 4104 |
env->slb_nr = 32; |
|
| 4134 |
/* XXX : not implemented */ |
|
| 4135 |
spr_register(env, SPR_MMUCFG, "MMUCFG", |
|
| 4136 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4137 |
&spr_read_generic, SPR_NOACCESS, |
|
| 4138 |
0x00000000); /* TOFIX */ |
|
| 4139 |
/* XXX : not implemented */ |
|
| 4140 |
spr_register(env, SPR_MMUCSR0, "MMUCSR0", |
|
| 4141 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4142 |
&spr_read_generic, &spr_write_generic, |
|
| 4143 |
0x00000000); /* TOFIX */ |
|
| 4144 |
spr_register(env, SPR_HIOR, "SPR_HIOR", |
|
| 4145 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 4146 |
&spr_read_generic, &spr_write_generic, |
|
| 4147 |
0xFFF00000); /* XXX: This is a hack */ |
|
| 4148 |
#if !defined(CONFIG_USER_ONLY) |
|
| 4149 |
env->excp_prefix = 0xFFF00000; |
|
| 4105 | 4150 |
#endif |
| 4151 |
env->slb_nr = 32; |
|
| 4106 | 4152 |
init_excp_970(env); |
| 4107 | 4153 |
env->dcache_line_size = 128; |
| 4108 | 4154 |
env->icache_line_size = 128; |
| ... | ... | |
| 6010 | 6056 |
case POWERPC_MMU_64B: |
| 6011 | 6057 |
mmu_model = "PowerPC 64"; |
| 6012 | 6058 |
break; |
| 6013 |
case POWERPC_MMU_64BRIDGE: |
|
| 6014 |
mmu_model = "PowerPC 64 bridge"; |
|
| 6015 |
break; |
|
| 6016 | 6059 |
#endif |
| 6017 | 6060 |
default: |
| 6018 | 6061 |
mmu_model = "Unknown or invalid"; |
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