root / hw / mips_int.c @ 136be99e
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1 | 7b9cbadb | Aurelien Jarno | /*
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2 | 7b9cbadb | Aurelien Jarno | * QEMU MIPS interrupt support
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3 | 7b9cbadb | Aurelien Jarno | *
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4 | 7b9cbadb | Aurelien Jarno | * Permission is hereby granted, free of charge, to any person obtaining a copy
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5 | 7b9cbadb | Aurelien Jarno | * of this software and associated documentation files (the "Software"), to deal
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6 | 7b9cbadb | Aurelien Jarno | * in the Software without restriction, including without limitation the rights
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7 | 7b9cbadb | Aurelien Jarno | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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8 | 7b9cbadb | Aurelien Jarno | * copies of the Software, and to permit persons to whom the Software is
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9 | 7b9cbadb | Aurelien Jarno | * furnished to do so, subject to the following conditions:
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10 | 7b9cbadb | Aurelien Jarno | *
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11 | 7b9cbadb | Aurelien Jarno | * The above copyright notice and this permission notice shall be included in
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12 | 7b9cbadb | Aurelien Jarno | * all copies or substantial portions of the Software.
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13 | 7b9cbadb | Aurelien Jarno | *
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14 | 7b9cbadb | Aurelien Jarno | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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15 | 7b9cbadb | Aurelien Jarno | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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16 | 7b9cbadb | Aurelien Jarno | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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17 | 7b9cbadb | Aurelien Jarno | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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18 | 7b9cbadb | Aurelien Jarno | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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19 | 7b9cbadb | Aurelien Jarno | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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20 | 7b9cbadb | Aurelien Jarno | * THE SOFTWARE.
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21 | 7b9cbadb | Aurelien Jarno | */
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22 | 7b9cbadb | Aurelien Jarno | |
23 | 87ecb68b | pbrook | #include "hw.h" |
24 | b970ea8f | Blue Swirl | #include "mips_cpudevs.h" |
25 | 4de9b249 | ths | #include "cpu.h" |
26 | 4de9b249 | ths | |
27 | d537cf6c | pbrook | static void cpu_mips_irq_request(void *opaque, int irq, int level) |
28 | 4de9b249 | ths | { |
29 | 61c56c8c | Andreas Färber | CPUMIPSState *env = (CPUMIPSState *)opaque; |
30 | 4de9b249 | ths | |
31 | 39d51eb8 | ths | if (irq < 0 || irq > 7) |
32 | 4de9b249 | ths | return;
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33 | 4de9b249 | ths | |
34 | 4de9b249 | ths | if (level) {
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35 | 39d51eb8 | ths | env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
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36 | 4de9b249 | ths | } else {
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37 | a4bc3afc | ths | env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
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38 | 4de9b249 | ths | } |
39 | 36388314 | Edgar E. Iglesias | |
40 | 36388314 | Edgar E. Iglesias | if (env->CP0_Cause & CP0Ca_IP_mask) {
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41 | 36388314 | Edgar E. Iglesias | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
42 | 36388314 | Edgar E. Iglesias | } else {
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43 | 36388314 | Edgar E. Iglesias | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
44 | 36388314 | Edgar E. Iglesias | } |
45 | 4de9b249 | ths | } |
46 | d537cf6c | pbrook | |
47 | 61c56c8c | Andreas Färber | void cpu_mips_irq_init_cpu(CPUMIPSState *env)
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48 | d537cf6c | pbrook | { |
49 | d537cf6c | pbrook | qemu_irq *qi; |
50 | d537cf6c | pbrook | int i;
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51 | d537cf6c | pbrook | |
52 | d537cf6c | pbrook | qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
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53 | d537cf6c | pbrook | for (i = 0; i < 8; i++) { |
54 | d537cf6c | pbrook | env->irq[i] = qi[i]; |
55 | d537cf6c | pbrook | } |
56 | d537cf6c | pbrook | } |
57 | 5dc5d9f0 | Aurelien Jarno | |
58 | 61c56c8c | Andreas Färber | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) |
59 | 5dc5d9f0 | Aurelien Jarno | { |
60 | 5dc5d9f0 | Aurelien Jarno | if (irq < 0 || irq > 2) { |
61 | 5dc5d9f0 | Aurelien Jarno | return;
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62 | 5dc5d9f0 | Aurelien Jarno | } |
63 | 5dc5d9f0 | Aurelien Jarno | |
64 | 5dc5d9f0 | Aurelien Jarno | qemu_set_irq(env->irq[irq], level); |
65 | 5dc5d9f0 | Aurelien Jarno | } |