root / hw / mips_r4k.c @ 136be99e
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1 | e16fe40c | ths | /*
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2 | e16fe40c | ths | * QEMU/MIPS pseudo-board
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3 | e16fe40c | ths | *
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4 | e16fe40c | ths | * emulates a simple machine with ISA-like bus.
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5 | e16fe40c | ths | * ISA IO space mapped to the 0x14000000 (PHYS) and
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6 | e16fe40c | ths | * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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7 | e16fe40c | ths | * All peripherial devices are attached to this "bus" with
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8 | e16fe40c | ths | * the standard PC ISA addresses.
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9 | e16fe40c | ths | */
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10 | 87ecb68b | pbrook | #include "hw.h" |
11 | 87ecb68b | pbrook | #include "mips.h" |
12 | b970ea8f | Blue Swirl | #include "mips_cpudevs.h" |
13 | 87ecb68b | pbrook | #include "pc.h" |
14 | 87ecb68b | pbrook | #include "isa.h" |
15 | 87ecb68b | pbrook | #include "net.h" |
16 | 87ecb68b | pbrook | #include "sysemu.h" |
17 | 87ecb68b | pbrook | #include "boards.h" |
18 | b305b5ba | ths | #include "flash.h" |
19 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
20 | bba831e8 | Paul Brook | #include "mips-bios.h" |
21 | ec82026c | Gerd Hoffmann | #include "ide.h" |
22 | ca20cf32 | Blue Swirl | #include "loader.h" |
23 | ca20cf32 | Blue Swirl | #include "elf.h" |
24 | 1d914fa0 | Isaku Yamahata | #include "mc146818rtc.h" |
25 | b1277b03 | Jan Kiszka | #include "i8254.h" |
26 | 2446333c | Blue Swirl | #include "blockdev.h" |
27 | cfe5f011 | Avi Kivity | #include "exec-memory.h" |
28 | 44cbbf18 | ths | |
29 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
30 | e4bcb14c | ths | |
31 | 58126404 | pbrook | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
32 | 58126404 | pbrook | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
33 | 58126404 | pbrook | static const int ide_irq[2] = { 14, 15 }; |
34 | 58126404 | pbrook | |
35 | 64d7e9a4 | Blue Swirl | static ISADevice *pit; /* PIT i8254 */ |
36 | 697584ab | bellard | |
37 | 1b66074b | ths | /* i8254 PIT is attached to the IRQ0 at PIC i8259 */
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38 | 6af0bf9c | bellard | |
39 | 7df526e3 | ths | static struct _loaderparams { |
40 | 7df526e3 | ths | int ram_size;
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41 | 7df526e3 | ths | const char *kernel_filename; |
42 | 7df526e3 | ths | const char *kernel_cmdline; |
43 | 7df526e3 | ths | const char *initrd_filename; |
44 | 7df526e3 | ths | } loaderparams; |
45 | 7df526e3 | ths | |
46 | 0ae16450 | Avi Kivity | static void mips_qemu_write (void *opaque, target_phys_addr_t addr, |
47 | 0ae16450 | Avi Kivity | uint64_t val, unsigned size)
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48 | 6ae81775 | ths | { |
49 | 6ae81775 | ths | if ((addr & 0xffff) == 0 && val == 42) |
50 | 6ae81775 | ths | qemu_system_reset_request (); |
51 | 6ae81775 | ths | else if ((addr & 0xffff) == 4 && val == 42) |
52 | 6ae81775 | ths | qemu_system_shutdown_request (); |
53 | 6ae81775 | ths | } |
54 | 6ae81775 | ths | |
55 | 0ae16450 | Avi Kivity | static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr, |
56 | 0ae16450 | Avi Kivity | unsigned size)
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57 | 6ae81775 | ths | { |
58 | 6ae81775 | ths | return 0; |
59 | 6ae81775 | ths | } |
60 | 6ae81775 | ths | |
61 | 0ae16450 | Avi Kivity | static const MemoryRegionOps mips_qemu_ops = { |
62 | 0ae16450 | Avi Kivity | .read = mips_qemu_read, |
63 | 0ae16450 | Avi Kivity | .write = mips_qemu_write, |
64 | 0ae16450 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
65 | 6ae81775 | ths | }; |
66 | 6ae81775 | ths | |
67 | e16ad5b0 | Aurelien Jarno | typedef struct ResetData { |
68 | 61c56c8c | Andreas Färber | CPUMIPSState *env; |
69 | e16ad5b0 | Aurelien Jarno | uint64_t vector; |
70 | e16ad5b0 | Aurelien Jarno | } ResetData; |
71 | e16ad5b0 | Aurelien Jarno | |
72 | e16ad5b0 | Aurelien Jarno | static int64_t load_kernel(void) |
73 | 6ae81775 | ths | { |
74 | 409dbce5 | Aurelien Jarno | int64_t entry, kernel_high; |
75 | e90e795e | Aurelien Jarno | long kernel_size, initrd_size, params_size;
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76 | c227f099 | Anthony Liguori | ram_addr_t initrd_offset; |
77 | e90e795e | Aurelien Jarno | uint32_t *params_buf; |
78 | ca20cf32 | Blue Swirl | int big_endian;
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79 | 6ae81775 | ths | |
80 | ca20cf32 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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81 | ca20cf32 | Blue Swirl | big_endian = 1;
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82 | ca20cf32 | Blue Swirl | #else
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83 | ca20cf32 | Blue Swirl | big_endian = 0;
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84 | ca20cf32 | Blue Swirl | #endif
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85 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, |
86 | 409dbce5 | Aurelien Jarno | NULL, (uint64_t *)&entry, NULL, |
87 | 409dbce5 | Aurelien Jarno | (uint64_t *)&kernel_high, big_endian, |
88 | 409dbce5 | Aurelien Jarno | ELF_MACHINE, 1);
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89 | c570fd16 | ths | if (kernel_size >= 0) { |
90 | c570fd16 | ths | if ((entry & ~0x7fffffffULL) == 0x80000000) |
91 | 5dc4b744 | ths | entry = (int32_t)entry; |
92 | c570fd16 | ths | } else {
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93 | 9042c0e2 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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94 | 7df526e3 | ths | loaderparams.kernel_filename); |
95 | 9042c0e2 | ths | exit(1);
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96 | 6ae81775 | ths | } |
97 | 6ae81775 | ths | |
98 | 6ae81775 | ths | /* load initrd */
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99 | 6ae81775 | ths | initrd_size = 0;
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100 | 74287114 | ths | initrd_offset = 0;
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101 | 7df526e3 | ths | if (loaderparams.initrd_filename) {
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102 | 7df526e3 | ths | initrd_size = get_image_size (loaderparams.initrd_filename); |
103 | 74287114 | ths | if (initrd_size > 0) { |
104 | 74287114 | ths | initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
105 | 74287114 | ths | if (initrd_offset + initrd_size > ram_size) {
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106 | 74287114 | ths | fprintf(stderr, |
107 | 74287114 | ths | "qemu: memory too small for initial ram disk '%s'\n",
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108 | 7df526e3 | ths | loaderparams.initrd_filename); |
109 | 74287114 | ths | exit(1);
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110 | 74287114 | ths | } |
111 | dcac9679 | pbrook | initrd_size = load_image_targphys(loaderparams.initrd_filename, |
112 | dcac9679 | pbrook | initrd_offset, |
113 | dcac9679 | pbrook | ram_size - initrd_offset); |
114 | 74287114 | ths | } |
115 | 6ae81775 | ths | if (initrd_size == (target_ulong) -1) { |
116 | 6ae81775 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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117 | 7df526e3 | ths | loaderparams.initrd_filename); |
118 | 6ae81775 | ths | exit(1);
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119 | 6ae81775 | ths | } |
120 | 6ae81775 | ths | } |
121 | 6ae81775 | ths | |
122 | 6ae81775 | ths | /* Store command line. */
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123 | e90e795e | Aurelien Jarno | params_size = 264;
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124 | 7267c094 | Anthony Liguori | params_buf = g_malloc(params_size); |
125 | e90e795e | Aurelien Jarno | |
126 | e90e795e | Aurelien Jarno | params_buf[0] = tswap32(ram_size);
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127 | e90e795e | Aurelien Jarno | params_buf[1] = tswap32(0x12345678); |
128 | e90e795e | Aurelien Jarno | |
129 | 6ae81775 | ths | if (initrd_size > 0) { |
130 | 409dbce5 | Aurelien Jarno | snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s", |
131 | 409dbce5 | Aurelien Jarno | cpu_mips_phys_to_kseg0(NULL, initrd_offset),
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132 | e90e795e | Aurelien Jarno | initrd_size, loaderparams.kernel_cmdline); |
133 | d7585251 | pbrook | } else {
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134 | e90e795e | Aurelien Jarno | snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline); |
135 | 6ae81775 | ths | } |
136 | 6ae81775 | ths | |
137 | e90e795e | Aurelien Jarno | rom_add_blob_fixed("params", params_buf, params_size,
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138 | e90e795e | Aurelien Jarno | (16 << 20) - 264); |
139 | e90e795e | Aurelien Jarno | |
140 | e16ad5b0 | Aurelien Jarno | return entry;
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141 | 6ae81775 | ths | } |
142 | 6ae81775 | ths | |
143 | 6ae81775 | ths | static void main_cpu_reset(void *opaque) |
144 | 6ae81775 | ths | { |
145 | e16ad5b0 | Aurelien Jarno | ResetData *s = (ResetData *)opaque; |
146 | 61c56c8c | Andreas Färber | CPUMIPSState *env = s->env; |
147 | 6ae81775 | ths | |
148 | 1bba0dc9 | Andreas Färber | cpu_state_reset(env); |
149 | e16ad5b0 | Aurelien Jarno | env->active_tc.PC = s->vector; |
150 | 6ae81775 | ths | } |
151 | 66a93e0f | bellard | |
152 | b305b5ba | ths | static const int sector_len = 32 * 1024; |
153 | 70705261 | ths | static
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154 | c227f099 | Anthony Liguori | void mips_r4k_init (ram_addr_t ram_size,
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155 | 3023f332 | aliguori | const char *boot_device, |
156 | 6af0bf9c | bellard | const char *kernel_filename, const char *kernel_cmdline, |
157 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model) |
158 | 6af0bf9c | bellard | { |
159 | 5cea8590 | Paul Brook | char *filename;
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160 | 0ae16450 | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
161 | 0ae16450 | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
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162 | cfe5f011 | Avi Kivity | MemoryRegion *bios; |
163 | 0ae16450 | Avi Kivity | MemoryRegion *iomem = g_new(MemoryRegion, 1);
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164 | f7bcd4e3 | ths | int bios_size;
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165 | 61c56c8c | Andreas Färber | CPUMIPSState *env; |
166 | e16ad5b0 | Aurelien Jarno | ResetData *reset_info; |
167 | 58126404 | pbrook | int i;
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168 | d537cf6c | pbrook | qemu_irq *i8259; |
169 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
170 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
171 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
172 | 3d08ff69 | Blue Swirl | int be;
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173 | c68ea704 | bellard | |
174 | 33d68b5f | ths | /* init CPUs */
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175 | 33d68b5f | ths | if (cpu_model == NULL) { |
176 | 60aa19ab | ths | #ifdef TARGET_MIPS64
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177 | 33d68b5f | ths | cpu_model = "R4000";
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178 | 33d68b5f | ths | #else
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179 | 1c32f43e | ths | cpu_model = "24Kf";
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180 | 33d68b5f | ths | #endif
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181 | 33d68b5f | ths | } |
182 | aaed909a | bellard | env = cpu_init(cpu_model); |
183 | aaed909a | bellard | if (!env) {
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184 | aaed909a | bellard | fprintf(stderr, "Unable to find CPU definition\n");
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185 | aaed909a | bellard | exit(1);
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186 | aaed909a | bellard | } |
187 | 7267c094 | Anthony Liguori | reset_info = g_malloc0(sizeof(ResetData));
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188 | e16ad5b0 | Aurelien Jarno | reset_info->env = env; |
189 | e16ad5b0 | Aurelien Jarno | reset_info->vector = env->active_tc.PC; |
190 | e16ad5b0 | Aurelien Jarno | qemu_register_reset(main_cpu_reset, reset_info); |
191 | c68ea704 | bellard | |
192 | 6af0bf9c | bellard | /* allocate RAM */
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193 | 0ccff151 | aurel32 | if (ram_size > (256 << 20)) { |
194 | 0ccff151 | aurel32 | fprintf(stderr, |
195 | 0ccff151 | aurel32 | "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
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196 | 0ccff151 | aurel32 | ((unsigned int)ram_size / (1 << 20))); |
197 | 0ccff151 | aurel32 | exit(1);
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198 | 0ccff151 | aurel32 | } |
199 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "mips_r4k.ram", ram_size);
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200 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
201 | dcac9679 | pbrook | |
202 | 0ae16450 | Avi Kivity | memory_region_add_subregion(address_space_mem, 0, ram);
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203 | 66a93e0f | bellard | |
204 | 0ae16450 | Avi Kivity | memory_region_init_io(iomem, &mips_qemu_ops, NULL, "mips-qemu", 0x10000); |
205 | 0ae16450 | Avi Kivity | memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
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206 | 6ae81775 | ths | |
207 | 66a93e0f | bellard | /* Try to load a BIOS image. If this fails, we continue regardless,
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208 | 66a93e0f | bellard | but initialize the hardware ourselves. When a kernel gets
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209 | 66a93e0f | bellard | preloaded we also initialize the hardware, since the BIOS wasn't
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210 | 66a93e0f | bellard | run. */
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211 | 1192dad8 | j_mayer | if (bios_name == NULL) |
212 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
213 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
214 | 5cea8590 | Paul Brook | if (filename) {
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215 | 5cea8590 | Paul Brook | bios_size = get_image_size(filename); |
216 | 5cea8590 | Paul Brook | } else {
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217 | 5cea8590 | Paul Brook | bios_size = -1;
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218 | 5cea8590 | Paul Brook | } |
219 | 3d08ff69 | Blue Swirl | #ifdef TARGET_WORDS_BIGENDIAN
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220 | 3d08ff69 | Blue Swirl | be = 1;
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221 | 3d08ff69 | Blue Swirl | #else
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222 | 3d08ff69 | Blue Swirl | be = 0;
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223 | 3d08ff69 | Blue Swirl | #endif
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224 | 2909b29a | ths | if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { |
225 | cfe5f011 | Avi Kivity | bios = g_new(MemoryRegion, 1);
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226 | c5705a77 | Avi Kivity | memory_region_init_ram(bios, "mips_r4k.bios", BIOS_SIZE);
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227 | c5705a77 | Avi Kivity | vmstate_register_ram_global(bios); |
228 | cfe5f011 | Avi Kivity | memory_region_set_readonly(bios, true);
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229 | cfe5f011 | Avi Kivity | memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
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230 | 01e0451a | Anthony Liguori | |
231 | 5cea8590 | Paul Brook | load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
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232 | 751c6a17 | Gerd Hoffmann | } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { |
233 | b305b5ba | ths | uint32_t mips_rom = 0x00400000;
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234 | cfe5f011 | Avi Kivity | if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom, |
235 | 3d08ff69 | Blue Swirl | dinfo->bdrv, sector_len, |
236 | 3d08ff69 | Blue Swirl | mips_rom / sector_len, |
237 | 01e0451a | Anthony Liguori | 4, 0, 0, 0, 0, be)) { |
238 | b305b5ba | ths | fprintf(stderr, "qemu: Error registering flash memory.\n");
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239 | b305b5ba | ths | } |
240 | b305b5ba | ths | } |
241 | b305b5ba | ths | else {
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242 | 66a93e0f | bellard | /* not fatal */
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243 | 66a93e0f | bellard | fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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244 | 5cea8590 | Paul Brook | bios_name); |
245 | 5cea8590 | Paul Brook | } |
246 | 5cea8590 | Paul Brook | if (filename) {
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247 | 7267c094 | Anthony Liguori | g_free(filename); |
248 | 6af0bf9c | bellard | } |
249 | 66a93e0f | bellard | |
250 | 66a93e0f | bellard | if (kernel_filename) {
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251 | 7df526e3 | ths | loaderparams.ram_size = ram_size; |
252 | 7df526e3 | ths | loaderparams.kernel_filename = kernel_filename; |
253 | 7df526e3 | ths | loaderparams.kernel_cmdline = kernel_cmdline; |
254 | 7df526e3 | ths | loaderparams.initrd_filename = initrd_filename; |
255 | e16ad5b0 | Aurelien Jarno | reset_info->vector = load_kernel(); |
256 | 6af0bf9c | bellard | } |
257 | 6af0bf9c | bellard | |
258 | e16fe40c | ths | /* Init CPU internal devices */
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259 | d537cf6c | pbrook | cpu_mips_irq_init_cpu(env); |
260 | c68ea704 | bellard | cpu_mips_clock_init(env); |
261 | 6af0bf9c | bellard | |
262 | d537cf6c | pbrook | /* The PIC is attached to the MIPS CPU INT0 pin */
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263 | 48a18b3c | Hervé Poussineau | isa_bus = isa_bus_new(NULL, get_system_io());
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264 | 48a18b3c | Hervé Poussineau | i8259 = i8259_init(isa_bus, env->irq[2]);
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265 | 48a18b3c | Hervé Poussineau | isa_bus_irqs(isa_bus, i8259); |
266 | d537cf6c | pbrook | |
267 | 48a18b3c | Hervé Poussineau | rtc_init(isa_bus, 2000, NULL); |
268 | afdfa781 | ths | |
269 | 0699b548 | bellard | /* Register 64 KB of ISA IO space at 0x14000000 */
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270 | 968d683c | Alexander Graf | isa_mmio_init(0x14000000, 0x00010000); |
271 | 0699b548 | bellard | isa_mem_base = 0x10000000;
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272 | 0699b548 | bellard | |
273 | 319ba9f5 | Jan Kiszka | pit = pit_init(isa_bus, 0x40, 0, NULL); |
274 | afdfa781 | ths | |
275 | eddbd288 | ths | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
276 | eddbd288 | ths | if (serial_hds[i]) {
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277 | 48a18b3c | Hervé Poussineau | serial_isa_init(isa_bus, i, serial_hds[i]); |
278 | eddbd288 | ths | } |
279 | eddbd288 | ths | } |
280 | eddbd288 | ths | |
281 | 48a18b3c | Hervé Poussineau | isa_vga_init(isa_bus); |
282 | 9827e95c | bellard | |
283 | 0ae18cee | aliguori | if (nd_table[0].vlan) |
284 | 48a18b3c | Hervé Poussineau | isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]); |
285 | 58126404 | pbrook | |
286 | 75717903 | Isaku Yamahata | ide_drive_get(hd, MAX_IDE_BUS); |
287 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) |
288 | 48a18b3c | Hervé Poussineau | isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], |
289 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i], |
290 | e4bcb14c | ths | hd[MAX_IDE_DEVS * i + 1]);
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291 | 70705261 | ths | |
292 | 48a18b3c | Hervé Poussineau | isa_create_simple(isa_bus, "i8042");
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293 | 6af0bf9c | bellard | } |
294 | 6af0bf9c | bellard | |
295 | f80f9ec9 | Anthony Liguori | static QEMUMachine mips_machine = {
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296 | eec2743e | ths | .name = "mips",
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297 | eec2743e | ths | .desc = "mips r4k platform",
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298 | eec2743e | ths | .init = mips_r4k_init, |
299 | 6af0bf9c | bellard | }; |
300 | f80f9ec9 | Anthony Liguori | |
301 | f80f9ec9 | Anthony Liguori | static void mips_machine_init(void) |
302 | f80f9ec9 | Anthony Liguori | { |
303 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mips_machine); |
304 | f80f9ec9 | Anthony Liguori | } |
305 | f80f9ec9 | Anthony Liguori | |
306 | f80f9ec9 | Anthony Liguori | machine_init(mips_machine_init); |