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1 | 9ee6e8bb | pbrook | /*
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2 | 9ee6e8bb | pbrook | * Arm PrimeCell PL061 General Purpose IO with additional
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3 | 9ee6e8bb | pbrook | * Luminary Micro Stellaris bits.
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4 | 9ee6e8bb | pbrook | *
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5 | 9ee6e8bb | pbrook | * Copyright (c) 2007 CodeSourcery.
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6 | 9ee6e8bb | pbrook | * Written by Paul Brook
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7 | 9ee6e8bb | pbrook | *
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8 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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9 | 9ee6e8bb | pbrook | */
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10 | 9ee6e8bb | pbrook | |
11 | 40905a6a | Paul Brook | #include "sysbus.h" |
12 | 9ee6e8bb | pbrook | |
13 | 9ee6e8bb | pbrook | //#define DEBUG_PL061 1
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14 | 9ee6e8bb | pbrook | |
15 | 9ee6e8bb | pbrook | #ifdef DEBUG_PL061
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16 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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17 | 001faf32 | Blue Swirl | do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) |
18 | 001faf32 | Blue Swirl | #define BADF(fmt, ...) \
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19 | 001faf32 | Blue Swirl | do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) |
20 | 9ee6e8bb | pbrook | #else
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21 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while(0) |
22 | 001faf32 | Blue Swirl | #define BADF(fmt, ...) \
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23 | 001faf32 | Blue Swirl | do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) |
24 | 9ee6e8bb | pbrook | #endif
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25 | 9ee6e8bb | pbrook | |
26 | 9ee6e8bb | pbrook | static const uint8_t pl061_id[12] = |
27 | 7063f49f | Peter Maydell | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
28 | 7063f49f | Peter Maydell | static const uint8_t pl061_id_luminary[12] = |
29 | 9ee6e8bb | pbrook | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; |
30 | 9ee6e8bb | pbrook | |
31 | 9ee6e8bb | pbrook | typedef struct { |
32 | 40905a6a | Paul Brook | SysBusDevice busdev; |
33 | 3cf89f8a | Avi Kivity | MemoryRegion iomem; |
34 | a35faa94 | Peter Maydell | uint32_t locked; |
35 | a35faa94 | Peter Maydell | uint32_t data; |
36 | a35faa94 | Peter Maydell | uint32_t old_data; |
37 | a35faa94 | Peter Maydell | uint32_t dir; |
38 | a35faa94 | Peter Maydell | uint32_t isense; |
39 | a35faa94 | Peter Maydell | uint32_t ibe; |
40 | a35faa94 | Peter Maydell | uint32_t iev; |
41 | a35faa94 | Peter Maydell | uint32_t im; |
42 | a35faa94 | Peter Maydell | uint32_t istate; |
43 | a35faa94 | Peter Maydell | uint32_t afsel; |
44 | a35faa94 | Peter Maydell | uint32_t dr2r; |
45 | a35faa94 | Peter Maydell | uint32_t dr4r; |
46 | a35faa94 | Peter Maydell | uint32_t dr8r; |
47 | a35faa94 | Peter Maydell | uint32_t odr; |
48 | a35faa94 | Peter Maydell | uint32_t pur; |
49 | a35faa94 | Peter Maydell | uint32_t pdr; |
50 | a35faa94 | Peter Maydell | uint32_t slr; |
51 | a35faa94 | Peter Maydell | uint32_t den; |
52 | a35faa94 | Peter Maydell | uint32_t cr; |
53 | a35faa94 | Peter Maydell | uint32_t float_high; |
54 | b3aaff11 | Peter Maydell | uint32_t amsel; |
55 | 9ee6e8bb | pbrook | qemu_irq irq; |
56 | 9ee6e8bb | pbrook | qemu_irq out[8];
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57 | 7063f49f | Peter Maydell | const unsigned char *id; |
58 | 9ee6e8bb | pbrook | } pl061_state; |
59 | 9ee6e8bb | pbrook | |
60 | a35faa94 | Peter Maydell | static const VMStateDescription vmstate_pl061 = { |
61 | a35faa94 | Peter Maydell | .name = "pl061",
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62 | b3aaff11 | Peter Maydell | .version_id = 2,
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63 | a35faa94 | Peter Maydell | .minimum_version_id = 1,
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64 | a35faa94 | Peter Maydell | .fields = (VMStateField[]) { |
65 | a35faa94 | Peter Maydell | VMSTATE_UINT32(locked, pl061_state), |
66 | a35faa94 | Peter Maydell | VMSTATE_UINT32(data, pl061_state), |
67 | a35faa94 | Peter Maydell | VMSTATE_UINT32(old_data, pl061_state), |
68 | a35faa94 | Peter Maydell | VMSTATE_UINT32(dir, pl061_state), |
69 | a35faa94 | Peter Maydell | VMSTATE_UINT32(isense, pl061_state), |
70 | a35faa94 | Peter Maydell | VMSTATE_UINT32(ibe, pl061_state), |
71 | a35faa94 | Peter Maydell | VMSTATE_UINT32(iev, pl061_state), |
72 | a35faa94 | Peter Maydell | VMSTATE_UINT32(im, pl061_state), |
73 | a35faa94 | Peter Maydell | VMSTATE_UINT32(istate, pl061_state), |
74 | a35faa94 | Peter Maydell | VMSTATE_UINT32(afsel, pl061_state), |
75 | a35faa94 | Peter Maydell | VMSTATE_UINT32(dr2r, pl061_state), |
76 | a35faa94 | Peter Maydell | VMSTATE_UINT32(dr4r, pl061_state), |
77 | a35faa94 | Peter Maydell | VMSTATE_UINT32(dr8r, pl061_state), |
78 | a35faa94 | Peter Maydell | VMSTATE_UINT32(odr, pl061_state), |
79 | a35faa94 | Peter Maydell | VMSTATE_UINT32(pur, pl061_state), |
80 | a35faa94 | Peter Maydell | VMSTATE_UINT32(pdr, pl061_state), |
81 | a35faa94 | Peter Maydell | VMSTATE_UINT32(slr, pl061_state), |
82 | a35faa94 | Peter Maydell | VMSTATE_UINT32(den, pl061_state), |
83 | a35faa94 | Peter Maydell | VMSTATE_UINT32(cr, pl061_state), |
84 | a35faa94 | Peter Maydell | VMSTATE_UINT32(float_high, pl061_state), |
85 | b3aaff11 | Peter Maydell | VMSTATE_UINT32_V(amsel, pl061_state, 2),
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86 | a35faa94 | Peter Maydell | VMSTATE_END_OF_LIST() |
87 | a35faa94 | Peter Maydell | } |
88 | a35faa94 | Peter Maydell | }; |
89 | a35faa94 | Peter Maydell | |
90 | 9ee6e8bb | pbrook | static void pl061_update(pl061_state *s) |
91 | 9ee6e8bb | pbrook | { |
92 | 9ee6e8bb | pbrook | uint8_t changed; |
93 | 9ee6e8bb | pbrook | uint8_t mask; |
94 | 775616c3 | pbrook | uint8_t out; |
95 | 9ee6e8bb | pbrook | int i;
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96 | 9ee6e8bb | pbrook | |
97 | 775616c3 | pbrook | /* Outputs float high. */
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98 | 775616c3 | pbrook | /* FIXME: This is board dependent. */
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99 | 775616c3 | pbrook | out = (s->data & s->dir) | ~s->dir; |
100 | 775616c3 | pbrook | changed = s->old_data ^ out; |
101 | 9ee6e8bb | pbrook | if (!changed)
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102 | 9ee6e8bb | pbrook | return;
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103 | 9ee6e8bb | pbrook | |
104 | 775616c3 | pbrook | s->old_data = out; |
105 | 9ee6e8bb | pbrook | for (i = 0; i < 8; i++) { |
106 | 9ee6e8bb | pbrook | mask = 1 << i;
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107 | b78c2b3a | Peter Maydell | if (changed & mask) {
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108 | 775616c3 | pbrook | DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); |
109 | 775616c3 | pbrook | qemu_set_irq(s->out[i], (out & mask) != 0);
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110 | 9ee6e8bb | pbrook | } |
111 | 9ee6e8bb | pbrook | } |
112 | 9ee6e8bb | pbrook | |
113 | 9ee6e8bb | pbrook | /* FIXME: Implement input interrupts. */
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114 | 9ee6e8bb | pbrook | } |
115 | 9ee6e8bb | pbrook | |
116 | 3cf89f8a | Avi Kivity | static uint64_t pl061_read(void *opaque, target_phys_addr_t offset, |
117 | 3cf89f8a | Avi Kivity | unsigned size)
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118 | 9ee6e8bb | pbrook | { |
119 | 9ee6e8bb | pbrook | pl061_state *s = (pl061_state *)opaque; |
120 | 9ee6e8bb | pbrook | |
121 | 9ee6e8bb | pbrook | if (offset >= 0xfd0 && offset < 0x1000) { |
122 | 7063f49f | Peter Maydell | return s->id[(offset - 0xfd0) >> 2]; |
123 | 9ee6e8bb | pbrook | } |
124 | 9ee6e8bb | pbrook | if (offset < 0x400) { |
125 | 9ee6e8bb | pbrook | return s->data & (offset >> 2); |
126 | 9ee6e8bb | pbrook | } |
127 | 9ee6e8bb | pbrook | switch (offset) {
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128 | 9ee6e8bb | pbrook | case 0x400: /* Direction */ |
129 | 9ee6e8bb | pbrook | return s->dir;
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130 | 9ee6e8bb | pbrook | case 0x404: /* Interrupt sense */ |
131 | 9ee6e8bb | pbrook | return s->isense;
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132 | 9ee6e8bb | pbrook | case 0x408: /* Interrupt both edges */ |
133 | 9ee6e8bb | pbrook | return s->ibe;
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134 | ff2712ba | Stefan Weil | case 0x40c: /* Interrupt event */ |
135 | 9ee6e8bb | pbrook | return s->iev;
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136 | 9ee6e8bb | pbrook | case 0x410: /* Interrupt mask */ |
137 | 9ee6e8bb | pbrook | return s->im;
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138 | 9ee6e8bb | pbrook | case 0x414: /* Raw interrupt status */ |
139 | 9ee6e8bb | pbrook | return s->istate;
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140 | 9ee6e8bb | pbrook | case 0x418: /* Masked interrupt status */ |
141 | 9ee6e8bb | pbrook | return s->istate | s->im;
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142 | 9ee6e8bb | pbrook | case 0x420: /* Alternate function select */ |
143 | 9ee6e8bb | pbrook | return s->afsel;
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144 | 9ee6e8bb | pbrook | case 0x500: /* 2mA drive */ |
145 | 9ee6e8bb | pbrook | return s->dr2r;
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146 | 9ee6e8bb | pbrook | case 0x504: /* 4mA drive */ |
147 | 9ee6e8bb | pbrook | return s->dr4r;
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148 | 9ee6e8bb | pbrook | case 0x508: /* 8mA drive */ |
149 | 9ee6e8bb | pbrook | return s->dr8r;
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150 | 9ee6e8bb | pbrook | case 0x50c: /* Open drain */ |
151 | 9ee6e8bb | pbrook | return s->odr;
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152 | 9ee6e8bb | pbrook | case 0x510: /* Pull-up */ |
153 | 9ee6e8bb | pbrook | return s->pur;
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154 | 9ee6e8bb | pbrook | case 0x514: /* Pull-down */ |
155 | 9ee6e8bb | pbrook | return s->pdr;
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156 | 9ee6e8bb | pbrook | case 0x518: /* Slew rate control */ |
157 | 9ee6e8bb | pbrook | return s->slr;
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158 | 9ee6e8bb | pbrook | case 0x51c: /* Digital enable */ |
159 | 9ee6e8bb | pbrook | return s->den;
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160 | 9ee6e8bb | pbrook | case 0x520: /* Lock */ |
161 | 9ee6e8bb | pbrook | return s->locked;
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162 | 9ee6e8bb | pbrook | case 0x524: /* Commit */ |
163 | 9ee6e8bb | pbrook | return s->cr;
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164 | b3aaff11 | Peter Maydell | case 0x528: /* Analog mode select */ |
165 | b3aaff11 | Peter Maydell | return s->amsel;
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166 | 9ee6e8bb | pbrook | default:
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167 | 2ac71179 | Paul Brook | hw_error("pl061_read: Bad offset %x\n", (int)offset); |
168 | 9ee6e8bb | pbrook | return 0; |
169 | 9ee6e8bb | pbrook | } |
170 | 9ee6e8bb | pbrook | } |
171 | 9ee6e8bb | pbrook | |
172 | c227f099 | Anthony Liguori | static void pl061_write(void *opaque, target_phys_addr_t offset, |
173 | 3cf89f8a | Avi Kivity | uint64_t value, unsigned size)
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174 | 9ee6e8bb | pbrook | { |
175 | 9ee6e8bb | pbrook | pl061_state *s = (pl061_state *)opaque; |
176 | 9ee6e8bb | pbrook | uint8_t mask; |
177 | 9ee6e8bb | pbrook | |
178 | 9ee6e8bb | pbrook | if (offset < 0x400) { |
179 | 9ee6e8bb | pbrook | mask = (offset >> 2) & s->dir;
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180 | 9ee6e8bb | pbrook | s->data = (s->data & ~mask) | (value & mask); |
181 | 9ee6e8bb | pbrook | pl061_update(s); |
182 | 9ee6e8bb | pbrook | return;
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183 | 9ee6e8bb | pbrook | } |
184 | 9ee6e8bb | pbrook | switch (offset) {
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185 | 9ee6e8bb | pbrook | case 0x400: /* Direction */ |
186 | a35faa94 | Peter Maydell | s->dir = value & 0xff;
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187 | 9ee6e8bb | pbrook | break;
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188 | 9ee6e8bb | pbrook | case 0x404: /* Interrupt sense */ |
189 | a35faa94 | Peter Maydell | s->isense = value & 0xff;
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190 | 9ee6e8bb | pbrook | break;
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191 | 9ee6e8bb | pbrook | case 0x408: /* Interrupt both edges */ |
192 | a35faa94 | Peter Maydell | s->ibe = value & 0xff;
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193 | 9ee6e8bb | pbrook | break;
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194 | ff2712ba | Stefan Weil | case 0x40c: /* Interrupt event */ |
195 | a35faa94 | Peter Maydell | s->iev = value & 0xff;
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196 | 9ee6e8bb | pbrook | break;
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197 | 9ee6e8bb | pbrook | case 0x410: /* Interrupt mask */ |
198 | a35faa94 | Peter Maydell | s->im = value & 0xff;
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199 | 9ee6e8bb | pbrook | break;
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200 | 9ee6e8bb | pbrook | case 0x41c: /* Interrupt clear */ |
201 | 9ee6e8bb | pbrook | s->istate &= ~value; |
202 | 9ee6e8bb | pbrook | break;
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203 | 9ee6e8bb | pbrook | case 0x420: /* Alternate function select */ |
204 | 9ee6e8bb | pbrook | mask = s->cr; |
205 | 9ee6e8bb | pbrook | s->afsel = (s->afsel & ~mask) | (value & mask); |
206 | 9ee6e8bb | pbrook | break;
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207 | 9ee6e8bb | pbrook | case 0x500: /* 2mA drive */ |
208 | a35faa94 | Peter Maydell | s->dr2r = value & 0xff;
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209 | 9ee6e8bb | pbrook | break;
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210 | 9ee6e8bb | pbrook | case 0x504: /* 4mA drive */ |
211 | a35faa94 | Peter Maydell | s->dr4r = value & 0xff;
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212 | 9ee6e8bb | pbrook | break;
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213 | 9ee6e8bb | pbrook | case 0x508: /* 8mA drive */ |
214 | a35faa94 | Peter Maydell | s->dr8r = value & 0xff;
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215 | 9ee6e8bb | pbrook | break;
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216 | 9ee6e8bb | pbrook | case 0x50c: /* Open drain */ |
217 | a35faa94 | Peter Maydell | s->odr = value & 0xff;
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218 | 9ee6e8bb | pbrook | break;
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219 | 9ee6e8bb | pbrook | case 0x510: /* Pull-up */ |
220 | a35faa94 | Peter Maydell | s->pur = value & 0xff;
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221 | 9ee6e8bb | pbrook | break;
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222 | 9ee6e8bb | pbrook | case 0x514: /* Pull-down */ |
223 | a35faa94 | Peter Maydell | s->pdr = value & 0xff;
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224 | 9ee6e8bb | pbrook | break;
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225 | 9ee6e8bb | pbrook | case 0x518: /* Slew rate control */ |
226 | a35faa94 | Peter Maydell | s->slr = value & 0xff;
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227 | 9ee6e8bb | pbrook | break;
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228 | 9ee6e8bb | pbrook | case 0x51c: /* Digital enable */ |
229 | a35faa94 | Peter Maydell | s->den = value & 0xff;
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230 | 9ee6e8bb | pbrook | break;
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231 | 9ee6e8bb | pbrook | case 0x520: /* Lock */ |
232 | 9ee6e8bb | pbrook | s->locked = (value != 0xacce551);
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233 | 9ee6e8bb | pbrook | break;
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234 | 9ee6e8bb | pbrook | case 0x524: /* Commit */ |
235 | 9ee6e8bb | pbrook | if (!s->locked)
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236 | a35faa94 | Peter Maydell | s->cr = value & 0xff;
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237 | 9ee6e8bb | pbrook | break;
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238 | b3aaff11 | Peter Maydell | case 0x528: |
239 | b3aaff11 | Peter Maydell | s->amsel = value & 0xff;
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240 | b3aaff11 | Peter Maydell | break;
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241 | 9ee6e8bb | pbrook | default:
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242 | 2ac71179 | Paul Brook | hw_error("pl061_write: Bad offset %x\n", (int)offset); |
243 | 9ee6e8bb | pbrook | } |
244 | 9ee6e8bb | pbrook | pl061_update(s); |
245 | 9ee6e8bb | pbrook | } |
246 | 9ee6e8bb | pbrook | |
247 | 9ee6e8bb | pbrook | static void pl061_reset(pl061_state *s) |
248 | 9ee6e8bb | pbrook | { |
249 | 9ee6e8bb | pbrook | s->locked = 1;
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250 | 9ee6e8bb | pbrook | s->cr = 0xff;
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251 | 9ee6e8bb | pbrook | } |
252 | 9ee6e8bb | pbrook | |
253 | 9596ebb7 | pbrook | static void pl061_set_irq(void * opaque, int irq, int level) |
254 | 9ee6e8bb | pbrook | { |
255 | 9ee6e8bb | pbrook | pl061_state *s = (pl061_state *)opaque; |
256 | 9ee6e8bb | pbrook | uint8_t mask; |
257 | 9ee6e8bb | pbrook | |
258 | 9ee6e8bb | pbrook | mask = 1 << irq;
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259 | 9ee6e8bb | pbrook | if ((s->dir & mask) == 0) { |
260 | 9ee6e8bb | pbrook | s->data &= ~mask; |
261 | 9ee6e8bb | pbrook | if (level)
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262 | 9ee6e8bb | pbrook | s->data |= mask; |
263 | 9ee6e8bb | pbrook | pl061_update(s); |
264 | 9ee6e8bb | pbrook | } |
265 | 9ee6e8bb | pbrook | } |
266 | 9ee6e8bb | pbrook | |
267 | 3cf89f8a | Avi Kivity | static const MemoryRegionOps pl061_ops = { |
268 | 3cf89f8a | Avi Kivity | .read = pl061_read, |
269 | 3cf89f8a | Avi Kivity | .write = pl061_write, |
270 | 3cf89f8a | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
271 | 9ee6e8bb | pbrook | }; |
272 | 9ee6e8bb | pbrook | |
273 | 7063f49f | Peter Maydell | static int pl061_init(SysBusDevice *dev, const unsigned char *id) |
274 | 9ee6e8bb | pbrook | { |
275 | 40905a6a | Paul Brook | pl061_state *s = FROM_SYSBUS(pl061_state, dev); |
276 | 7063f49f | Peter Maydell | s->id = id; |
277 | 3cf89f8a | Avi Kivity | memory_region_init_io(&s->iomem, &pl061_ops, s, "pl061", 0x1000); |
278 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->iomem); |
279 | 40905a6a | Paul Brook | sysbus_init_irq(dev, &s->irq); |
280 | 40905a6a | Paul Brook | qdev_init_gpio_in(&dev->qdev, pl061_set_irq, 8);
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281 | 40905a6a | Paul Brook | qdev_init_gpio_out(&dev->qdev, s->out, 8);
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282 | 9ee6e8bb | pbrook | pl061_reset(s); |
283 | 81a322d4 | Gerd Hoffmann | return 0; |
284 | 9ee6e8bb | pbrook | } |
285 | 40905a6a | Paul Brook | |
286 | 7063f49f | Peter Maydell | static int pl061_init_luminary(SysBusDevice *dev) |
287 | 7063f49f | Peter Maydell | { |
288 | 7063f49f | Peter Maydell | return pl061_init(dev, pl061_id_luminary);
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289 | 7063f49f | Peter Maydell | } |
290 | 7063f49f | Peter Maydell | |
291 | 7063f49f | Peter Maydell | static int pl061_init_arm(SysBusDevice *dev) |
292 | 7063f49f | Peter Maydell | { |
293 | 7063f49f | Peter Maydell | return pl061_init(dev, pl061_id);
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294 | 7063f49f | Peter Maydell | } |
295 | 7063f49f | Peter Maydell | |
296 | 999e12bb | Anthony Liguori | static void pl061_class_init(ObjectClass *klass, void *data) |
297 | 999e12bb | Anthony Liguori | { |
298 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
299 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
300 | 999e12bb | Anthony Liguori | |
301 | 999e12bb | Anthony Liguori | k->init = pl061_init_arm; |
302 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pl061; |
303 | 999e12bb | Anthony Liguori | } |
304 | 999e12bb | Anthony Liguori | |
305 | 39bffca2 | Anthony Liguori | static TypeInfo pl061_info = {
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306 | 39bffca2 | Anthony Liguori | .name = "pl061",
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307 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
308 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(pl061_state),
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309 | 39bffca2 | Anthony Liguori | .class_init = pl061_class_init, |
310 | a35faa94 | Peter Maydell | }; |
311 | a35faa94 | Peter Maydell | |
312 | 999e12bb | Anthony Liguori | static void pl061_luminary_class_init(ObjectClass *klass, void *data) |
313 | 999e12bb | Anthony Liguori | { |
314 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
315 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
316 | 999e12bb | Anthony Liguori | |
317 | 999e12bb | Anthony Liguori | k->init = pl061_init_luminary; |
318 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pl061; |
319 | 999e12bb | Anthony Liguori | } |
320 | 999e12bb | Anthony Liguori | |
321 | 39bffca2 | Anthony Liguori | static TypeInfo pl061_luminary_info = {
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322 | 39bffca2 | Anthony Liguori | .name = "pl061_luminary",
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323 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
324 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(pl061_state),
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325 | 39bffca2 | Anthony Liguori | .class_init = pl061_luminary_class_init, |
326 | a35faa94 | Peter Maydell | }; |
327 | a35faa94 | Peter Maydell | |
328 | 83f7d43a | Andreas Färber | static void pl061_register_types(void) |
329 | 40905a6a | Paul Brook | { |
330 | 39bffca2 | Anthony Liguori | type_register_static(&pl061_info); |
331 | 39bffca2 | Anthony Liguori | type_register_static(&pl061_luminary_info); |
332 | 40905a6a | Paul Brook | } |
333 | 40905a6a | Paul Brook | |
334 | 83f7d43a | Andreas Färber | type_init(pl061_register_types) |