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1 | 1dc324d2 | Michael S. Tsirkin | #ifndef SHPC_H
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2 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_H
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3 | 1dc324d2 | Michael S. Tsirkin | |
4 | 1dc324d2 | Michael S. Tsirkin | #include "qemu-common.h" |
5 | 1dc324d2 | Michael S. Tsirkin | #include "memory.h" |
6 | 1dc324d2 | Michael S. Tsirkin | #include "vmstate.h" |
7 | 1dc324d2 | Michael S. Tsirkin | |
8 | 1dc324d2 | Michael S. Tsirkin | struct SHPCDevice {
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9 | 1dc324d2 | Michael S. Tsirkin | /* Capability offset in device's config space */
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10 | 1dc324d2 | Michael S. Tsirkin | int cap;
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11 | 1dc324d2 | Michael S. Tsirkin | |
12 | 1dc324d2 | Michael S. Tsirkin | /* # of hot-pluggable slots */
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13 | 1dc324d2 | Michael S. Tsirkin | int nslots;
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14 | 1dc324d2 | Michael S. Tsirkin | |
15 | 1dc324d2 | Michael S. Tsirkin | /* SHPC WRS: working register set */
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16 | 1dc324d2 | Michael S. Tsirkin | uint8_t *config; |
17 | 1dc324d2 | Michael S. Tsirkin | |
18 | 1dc324d2 | Michael S. Tsirkin | /* Used to enable checks on load. Note that writable bits are
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19 | 1dc324d2 | Michael S. Tsirkin | * never checked even if set in cmask. */
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20 | 1dc324d2 | Michael S. Tsirkin | uint8_t *cmask; |
21 | 1dc324d2 | Michael S. Tsirkin | |
22 | 1dc324d2 | Michael S. Tsirkin | /* Used to implement R/W bytes */
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23 | 1dc324d2 | Michael S. Tsirkin | uint8_t *wmask; |
24 | 1dc324d2 | Michael S. Tsirkin | |
25 | 1dc324d2 | Michael S. Tsirkin | /* Used to implement RW1C(Write 1 to Clear) bytes */
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26 | 1dc324d2 | Michael S. Tsirkin | uint8_t *w1cmask; |
27 | 1dc324d2 | Michael S. Tsirkin | |
28 | 1dc324d2 | Michael S. Tsirkin | /* MMIO for the SHPC BAR */
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29 | 1dc324d2 | Michael S. Tsirkin | MemoryRegion mmio; |
30 | 1dc324d2 | Michael S. Tsirkin | |
31 | 1dc324d2 | Michael S. Tsirkin | /* Bus controlled by this SHPC */
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32 | 1dc324d2 | Michael S. Tsirkin | PCIBus *sec_bus; |
33 | 1dc324d2 | Michael S. Tsirkin | |
34 | 1dc324d2 | Michael S. Tsirkin | /* MSI already requested for this event */
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35 | 1dc324d2 | Michael S. Tsirkin | int msi_requested;
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36 | 1dc324d2 | Michael S. Tsirkin | }; |
37 | 1dc324d2 | Michael S. Tsirkin | |
38 | 1dc324d2 | Michael S. Tsirkin | void shpc_reset(PCIDevice *d);
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39 | 1dc324d2 | Michael S. Tsirkin | int shpc_bar_size(PCIDevice *dev);
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40 | 1dc324d2 | Michael S. Tsirkin | int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned off); |
41 | 1dc324d2 | Michael S. Tsirkin | void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar);
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42 | 1dc324d2 | Michael S. Tsirkin | void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len); |
43 | 1dc324d2 | Michael S. Tsirkin | |
44 | 1dc324d2 | Michael S. Tsirkin | extern VMStateInfo shpc_vmstate_info;
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45 | 1dc324d2 | Michael S. Tsirkin | #define SHPC_VMSTATE(_field, _type) \
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46 | 1dc324d2 | Michael S. Tsirkin | VMSTATE_BUFFER_UNSAFE_INFO(_field, _type, 0, shpc_vmstate_info, 0) |
47 | 1dc324d2 | Michael S. Tsirkin | |
48 | 1dc324d2 | Michael S. Tsirkin | #endif |