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1 | 4acb54ba | Edgar E. Iglesias | /*
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2 | 4acb54ba | Edgar E. Iglesias | * MicroBlaze virtual CPU header
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3 | 4acb54ba | Edgar E. Iglesias | *
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4 | 4acb54ba | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias
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5 | 4acb54ba | Edgar E. Iglesias | *
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6 | 4acb54ba | Edgar E. Iglesias | * This library is free software; you can redistribute it and/or
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7 | 4acb54ba | Edgar E. Iglesias | * modify it under the terms of the GNU Lesser General Public
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8 | 4acb54ba | Edgar E. Iglesias | * License as published by the Free Software Foundation; either
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9 | 4acb54ba | Edgar E. Iglesias | * version 2 of the License, or (at your option) any later version.
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10 | 4acb54ba | Edgar E. Iglesias | *
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11 | 4acb54ba | Edgar E. Iglesias | * This library is distributed in the hope that it will be useful,
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12 | 4acb54ba | Edgar E. Iglesias | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4acb54ba | Edgar E. Iglesias | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4acb54ba | Edgar E. Iglesias | * General Public License for more details.
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15 | 4acb54ba | Edgar E. Iglesias | *
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16 | 4acb54ba | Edgar E. Iglesias | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4acb54ba | Edgar E. Iglesias | */
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19 | 4acb54ba | Edgar E. Iglesias | #ifndef CPU_MICROBLAZE_H
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20 | 4acb54ba | Edgar E. Iglesias | #define CPU_MICROBLAZE_H
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21 | 4acb54ba | Edgar E. Iglesias | |
22 | 4acb54ba | Edgar E. Iglesias | #define TARGET_LONG_BITS 32 |
23 | 4acb54ba | Edgar E. Iglesias | |
24 | 4acb54ba | Edgar E. Iglesias | #define CPUState struct CPUMBState |
25 | 4acb54ba | Edgar E. Iglesias | |
26 | 4acb54ba | Edgar E. Iglesias | #include "cpu-defs.h" |
27 | 4acb54ba | Edgar E. Iglesias | struct CPUMBState;
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28 | 4acb54ba | Edgar E. Iglesias | #if !defined(CONFIG_USER_ONLY)
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29 | 4acb54ba | Edgar E. Iglesias | #include "mmu.h" |
30 | 4acb54ba | Edgar E. Iglesias | #endif
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31 | 4acb54ba | Edgar E. Iglesias | |
32 | 4acb54ba | Edgar E. Iglesias | #define TARGET_HAS_ICE 1 |
33 | 4acb54ba | Edgar E. Iglesias | |
34 | 4acb54ba | Edgar E. Iglesias | #define ELF_MACHINE EM_XILINX_MICROBLAZE
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35 | 4acb54ba | Edgar E. Iglesias | |
36 | 4acb54ba | Edgar E. Iglesias | #define EXCP_NMI 1 |
37 | 4acb54ba | Edgar E. Iglesias | #define EXCP_MMU 2 |
38 | 4acb54ba | Edgar E. Iglesias | #define EXCP_IRQ 3 |
39 | 4acb54ba | Edgar E. Iglesias | #define EXCP_BREAK 4 |
40 | 4acb54ba | Edgar E. Iglesias | #define EXCP_HW_BREAK 5 |
41 | cedb936b | Edgar E. Iglesias | #define EXCP_HW_EXCP 6 |
42 | 4acb54ba | Edgar E. Iglesias | |
43 | 4acb54ba | Edgar E. Iglesias | /* Register aliases. R0 - R15 */
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44 | 4acb54ba | Edgar E. Iglesias | #define R_SP 1 |
45 | 4acb54ba | Edgar E. Iglesias | #define SR_PC 0 |
46 | 4acb54ba | Edgar E. Iglesias | #define SR_MSR 1 |
47 | 4acb54ba | Edgar E. Iglesias | #define SR_EAR 3 |
48 | 4acb54ba | Edgar E. Iglesias | #define SR_ESR 5 |
49 | 4acb54ba | Edgar E. Iglesias | #define SR_FSR 7 |
50 | 4acb54ba | Edgar E. Iglesias | #define SR_BTR 0xb |
51 | 4acb54ba | Edgar E. Iglesias | #define SR_EDR 0xd |
52 | 4acb54ba | Edgar E. Iglesias | |
53 | 4acb54ba | Edgar E. Iglesias | /* MSR flags. */
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54 | 4acb54ba | Edgar E. Iglesias | #define MSR_BE (1<<0) /* 0x001 */ |
55 | 4acb54ba | Edgar E. Iglesias | #define MSR_IE (1<<1) /* 0x002 */ |
56 | 4acb54ba | Edgar E. Iglesias | #define MSR_C (1<<2) /* 0x004 */ |
57 | 4acb54ba | Edgar E. Iglesias | #define MSR_BIP (1<<3) /* 0x008 */ |
58 | 4acb54ba | Edgar E. Iglesias | #define MSR_FSL (1<<4) /* 0x010 */ |
59 | 4acb54ba | Edgar E. Iglesias | #define MSR_ICE (1<<5) /* 0x020 */ |
60 | 4acb54ba | Edgar E. Iglesias | #define MSR_DZ (1<<6) /* 0x040 */ |
61 | 4acb54ba | Edgar E. Iglesias | #define MSR_DCE (1<<7) /* 0x080 */ |
62 | 4acb54ba | Edgar E. Iglesias | #define MSR_EE (1<<8) /* 0x100 */ |
63 | 4acb54ba | Edgar E. Iglesias | #define MSR_EIP (1<<9) /* 0x200 */ |
64 | 4acb54ba | Edgar E. Iglesias | #define MSR_CC (1<<31) |
65 | 4acb54ba | Edgar E. Iglesias | |
66 | 4acb54ba | Edgar E. Iglesias | /* Machine State Register (MSR) Fields */
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67 | 4acb54ba | Edgar E. Iglesias | #define MSR_UM (1<<11) /* User Mode */ |
68 | 4acb54ba | Edgar E. Iglesias | #define MSR_UMS (1<<12) /* User Mode Save */ |
69 | 4acb54ba | Edgar E. Iglesias | #define MSR_VM (1<<13) /* Virtual Mode */ |
70 | 4acb54ba | Edgar E. Iglesias | #define MSR_VMS (1<<14) /* Virtual Mode Save */ |
71 | 4acb54ba | Edgar E. Iglesias | |
72 | 4acb54ba | Edgar E. Iglesias | #define MSR_KERNEL MSR_EE|MSR_VM
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73 | 4acb54ba | Edgar E. Iglesias | //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
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74 | 4acb54ba | Edgar E. Iglesias | #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
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75 | 4acb54ba | Edgar E. Iglesias | //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
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76 | 4acb54ba | Edgar E. Iglesias | |
77 | 4acb54ba | Edgar E. Iglesias | /* Exception State Register (ESR) Fields */
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78 | 4acb54ba | Edgar E. Iglesias | #define ESR_DIZ (1<<11) /* Zone Protection */ |
79 | 4acb54ba | Edgar E. Iglesias | #define ESR_S (1<<10) /* Store instruction */ |
80 | 4acb54ba | Edgar E. Iglesias | |
81 | cedb936b | Edgar E. Iglesias | #define ESR_EC_FSL 0 |
82 | cedb936b | Edgar E. Iglesias | #define ESR_EC_UNALIGNED_DATA 1 |
83 | cedb936b | Edgar E. Iglesias | #define ESR_EC_ILLEGAL_OP 2 |
84 | cedb936b | Edgar E. Iglesias | #define ESR_EC_INSN_BUS 3 |
85 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DATA_BUS 4 |
86 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DIVZERO 5 |
87 | cedb936b | Edgar E. Iglesias | #define ESR_EC_FPU 6 |
88 | cedb936b | Edgar E. Iglesias | #define ESR_EC_PRIVINSN 7 |
89 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DATA_STORAGE 8 |
90 | cedb936b | Edgar E. Iglesias | #define ESR_EC_INSN_STORAGE 9 |
91 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DATA_TLB 10 |
92 | cedb936b | Edgar E. Iglesias | #define ESR_EC_INSN_TLB 11 |
93 | 4acb54ba | Edgar E. Iglesias | |
94 | 4acb54ba | Edgar E. Iglesias | /* Version reg. */
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95 | 4acb54ba | Edgar E. Iglesias | /* Basic PVR mask */
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96 | 4acb54ba | Edgar E. Iglesias | #define PVR0_PVR_FULL_MASK 0x80000000 |
97 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_BARREL_MASK 0x40000000 |
98 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_DIV_MASK 0x20000000 |
99 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_HW_MUL_MASK 0x10000000 |
100 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_FPU_MASK 0x08000000 |
101 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_EXC_MASK 0x04000000 |
102 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_ICACHE_MASK 0x02000000 |
103 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_DCACHE_MASK 0x01000000 |
104 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_MMU 0x00800000 /* new */ |
105 | 4acb54ba | Edgar E. Iglesias | #define PVR0_VERSION_MASK 0x0000FF00 |
106 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USER1_MASK 0x000000FF |
107 | 4acb54ba | Edgar E. Iglesias | |
108 | 4acb54ba | Edgar E. Iglesias | /* User 2 PVR mask */
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109 | 4acb54ba | Edgar E. Iglesias | #define PVR1_USER2_MASK 0xFFFFFFFF |
110 | 4acb54ba | Edgar E. Iglesias | |
111 | 4acb54ba | Edgar E. Iglesias | /* Configuration PVR masks */
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112 | 4acb54ba | Edgar E. Iglesias | #define PVR2_D_OPB_MASK 0x80000000 |
113 | 4acb54ba | Edgar E. Iglesias | #define PVR2_D_LMB_MASK 0x40000000 |
114 | 4acb54ba | Edgar E. Iglesias | #define PVR2_I_OPB_MASK 0x20000000 |
115 | 4acb54ba | Edgar E. Iglesias | #define PVR2_I_LMB_MASK 0x10000000 |
116 | 4acb54ba | Edgar E. Iglesias | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 |
117 | 4acb54ba | Edgar E. Iglesias | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 |
118 | 4acb54ba | Edgar E. Iglesias | #define PVR2_D_PLB_MASK 0x02000000 /* new */ |
119 | 4acb54ba | Edgar E. Iglesias | #define PVR2_I_PLB_MASK 0x01000000 /* new */ |
120 | 4acb54ba | Edgar E. Iglesias | #define PVR2_INTERCONNECT 0x00800000 /* new */ |
121 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ |
122 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ |
123 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_MSR_INSTR 0x00020000 |
124 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_PCMP_INSTR 0x00010000 |
125 | 4acb54ba | Edgar E. Iglesias | #define PVR2_AREA_OPTIMISED 0x00008000 |
126 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_BARREL_MASK 0x00004000 |
127 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_DIV_MASK 0x00002000 |
128 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_HW_MUL_MASK 0x00001000 |
129 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_FPU_MASK 0x00000800 |
130 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_MUL64_MASK 0x00000400 |
131 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ |
132 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_IPLBEXC 0x00000100 |
133 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_DPLBEXC 0x00000080 |
134 | 4acb54ba | Edgar E. Iglesias | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 |
135 | 4acb54ba | Edgar E. Iglesias | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 |
136 | 4acb54ba | Edgar E. Iglesias | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 |
137 | 4acb54ba | Edgar E. Iglesias | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 |
138 | 4acb54ba | Edgar E. Iglesias | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 |
139 | 4acb54ba | Edgar E. Iglesias | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 |
140 | 4acb54ba | Edgar E. Iglesias | #define PVR2_FPU_EXC_MASK 0x00000001 |
141 | 4acb54ba | Edgar E. Iglesias | |
142 | 4acb54ba | Edgar E. Iglesias | /* Debug and exception PVR masks */
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143 | 4acb54ba | Edgar E. Iglesias | #define PVR3_DEBUG_ENABLED_MASK 0x80000000 |
144 | 4acb54ba | Edgar E. Iglesias | #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 |
145 | 4acb54ba | Edgar E. Iglesias | #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 |
146 | 4acb54ba | Edgar E. Iglesias | #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 |
147 | 4acb54ba | Edgar E. Iglesias | #define PVR3_FSL_LINKS_MASK 0x00000380 |
148 | 4acb54ba | Edgar E. Iglesias | |
149 | 4acb54ba | Edgar E. Iglesias | /* ICache config PVR masks */
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150 | 4acb54ba | Edgar E. Iglesias | #define PVR4_USE_ICACHE_MASK 0x80000000 |
151 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 |
152 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 |
153 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 |
154 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 |
155 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 |
156 | 4acb54ba | Edgar E. Iglesias | |
157 | 4acb54ba | Edgar E. Iglesias | /* DCache config PVR masks */
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158 | 4acb54ba | Edgar E. Iglesias | #define PVR5_USE_DCACHE_MASK 0x80000000 |
159 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 |
160 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 |
161 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 |
162 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 |
163 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 |
164 | 4acb54ba | Edgar E. Iglesias | |
165 | 4acb54ba | Edgar E. Iglesias | /* ICache base address PVR mask */
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166 | 4acb54ba | Edgar E. Iglesias | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF |
167 | 4acb54ba | Edgar E. Iglesias | |
168 | 4acb54ba | Edgar E. Iglesias | /* ICache high address PVR mask */
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169 | 4acb54ba | Edgar E. Iglesias | #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF |
170 | 4acb54ba | Edgar E. Iglesias | |
171 | 4acb54ba | Edgar E. Iglesias | /* DCache base address PVR mask */
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172 | 4acb54ba | Edgar E. Iglesias | #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF |
173 | 4acb54ba | Edgar E. Iglesias | |
174 | 4acb54ba | Edgar E. Iglesias | /* DCache high address PVR mask */
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175 | 4acb54ba | Edgar E. Iglesias | #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF |
176 | 4acb54ba | Edgar E. Iglesias | |
177 | 4acb54ba | Edgar E. Iglesias | /* Target family PVR mask */
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178 | 4acb54ba | Edgar E. Iglesias | #define PVR10_TARGET_FAMILY_MASK 0xFF000000 |
179 | 4acb54ba | Edgar E. Iglesias | |
180 | 4acb54ba | Edgar E. Iglesias | /* MMU descrtiption */
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181 | 4acb54ba | Edgar E. Iglesias | #define PVR11_USE_MMU 0xC0000000 |
182 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_ITLB_SIZE 0x38000000 |
183 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_DTLB_SIZE 0x07000000 |
184 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_TLB_ACCESS 0x00C00000 |
185 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_ZONES 0x003C0000 |
186 | 4acb54ba | Edgar E. Iglesias | /* MSR Reset value PVR mask */
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187 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF |
188 | 4acb54ba | Edgar E. Iglesias | |
189 | 4acb54ba | Edgar E. Iglesias | |
190 | 4acb54ba | Edgar E. Iglesias | |
191 | 4acb54ba | Edgar E. Iglesias | /* CPU flags. */
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192 | 4acb54ba | Edgar E. Iglesias | |
193 | 4acb54ba | Edgar E. Iglesias | /* Condition codes. */
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194 | 4acb54ba | Edgar E. Iglesias | #define CC_GE 5 |
195 | 4acb54ba | Edgar E. Iglesias | #define CC_GT 4 |
196 | 4acb54ba | Edgar E. Iglesias | #define CC_LE 3 |
197 | 4acb54ba | Edgar E. Iglesias | #define CC_LT 2 |
198 | 4acb54ba | Edgar E. Iglesias | #define CC_NE 1 |
199 | 4acb54ba | Edgar E. Iglesias | #define CC_EQ 0 |
200 | 4acb54ba | Edgar E. Iglesias | |
201 | 4acb54ba | Edgar E. Iglesias | #define NB_MMU_MODES 3 |
202 | 4acb54ba | Edgar E. Iglesias | typedef struct CPUMBState { |
203 | 4acb54ba | Edgar E. Iglesias | uint32_t debug; |
204 | 4acb54ba | Edgar E. Iglesias | uint32_t btaken; |
205 | 4acb54ba | Edgar E. Iglesias | uint32_t btarget; |
206 | 4acb54ba | Edgar E. Iglesias | uint32_t bimm; |
207 | 4acb54ba | Edgar E. Iglesias | |
208 | 4acb54ba | Edgar E. Iglesias | uint32_t imm; |
209 | 4acb54ba | Edgar E. Iglesias | uint32_t regs[33];
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210 | 4acb54ba | Edgar E. Iglesias | uint32_t sregs[24];
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211 | 4acb54ba | Edgar E. Iglesias | |
212 | 4acb54ba | Edgar E. Iglesias | /* Internal flags. */
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213 | cedb936b | Edgar E. Iglesias | #define IMM_FLAG 4 |
214 | cedb936b | Edgar E. Iglesias | #define MSR_EE_FLAG (1 << 8) |
215 | 4acb54ba | Edgar E. Iglesias | #define DRTI_FLAG (1 << 16) |
216 | 4acb54ba | Edgar E. Iglesias | #define DRTE_FLAG (1 << 17) |
217 | 4acb54ba | Edgar E. Iglesias | #define DRTB_FLAG (1 << 18) |
218 | 4acb54ba | Edgar E. Iglesias | #define D_FLAG (1 << 19) /* Bit in ESR. */ |
219 | 4acb54ba | Edgar E. Iglesias | /* TB dependant CPUState. */
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220 | cedb936b | Edgar E. Iglesias | #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG \
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221 | cedb936b | Edgar E. Iglesias | | DRTE_FLAG | DRTB_FLAG | MSR_EE_FLAG) |
222 | 4acb54ba | Edgar E. Iglesias | uint32_t iflags; |
223 | 4acb54ba | Edgar E. Iglesias | |
224 | 4acb54ba | Edgar E. Iglesias | struct {
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225 | 4acb54ba | Edgar E. Iglesias | uint32_t regs[16];
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226 | 4acb54ba | Edgar E. Iglesias | } pvr; |
227 | 4acb54ba | Edgar E. Iglesias | |
228 | 4acb54ba | Edgar E. Iglesias | #if !defined(CONFIG_USER_ONLY)
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229 | 4acb54ba | Edgar E. Iglesias | /* Unified MMU. */
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230 | 4acb54ba | Edgar E. Iglesias | struct microblaze_mmu mmu;
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231 | 4acb54ba | Edgar E. Iglesias | #endif
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232 | 4acb54ba | Edgar E. Iglesias | |
233 | 4acb54ba | Edgar E. Iglesias | CPU_COMMON |
234 | 4acb54ba | Edgar E. Iglesias | } CPUMBState; |
235 | 4acb54ba | Edgar E. Iglesias | |
236 | 4acb54ba | Edgar E. Iglesias | CPUState *cpu_mb_init(const char *cpu_model); |
237 | 4acb54ba | Edgar E. Iglesias | int cpu_mb_exec(CPUState *s);
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238 | 4acb54ba | Edgar E. Iglesias | void cpu_mb_close(CPUState *s);
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239 | 4acb54ba | Edgar E. Iglesias | void do_interrupt(CPUState *env);
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240 | 4acb54ba | Edgar E. Iglesias | /* you can call this signal handler from your SIGBUS and SIGSEGV
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241 | 4acb54ba | Edgar E. Iglesias | signal handlers to inform the virtual CPU of exceptions. non zero
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242 | 4acb54ba | Edgar E. Iglesias | is returned if the signal was handled by the virtual CPU. */
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243 | 4acb54ba | Edgar E. Iglesias | int cpu_mb_signal_handler(int host_signum, void *pinfo, |
244 | 4acb54ba | Edgar E. Iglesias | void *puc);
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245 | 4acb54ba | Edgar E. Iglesias | |
246 | 4acb54ba | Edgar E. Iglesias | enum {
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247 | 4acb54ba | Edgar E. Iglesias | CC_OP_DYNAMIC, /* Use env->cc_op */
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248 | 4acb54ba | Edgar E. Iglesias | CC_OP_FLAGS, |
249 | 4acb54ba | Edgar E. Iglesias | CC_OP_CMP, |
250 | 4acb54ba | Edgar E. Iglesias | }; |
251 | 4acb54ba | Edgar E. Iglesias | |
252 | 4acb54ba | Edgar E. Iglesias | /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
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253 | 4acb54ba | Edgar E. Iglesias | #define TARGET_PAGE_BITS 12 |
254 | 4acb54ba | Edgar E. Iglesias | #define MMAP_SHIFT TARGET_PAGE_BITS
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255 | 4acb54ba | Edgar E. Iglesias | |
256 | 4acb54ba | Edgar E. Iglesias | #define cpu_init cpu_mb_init
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257 | 4acb54ba | Edgar E. Iglesias | #define cpu_exec cpu_mb_exec
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258 | 4acb54ba | Edgar E. Iglesias | #define cpu_gen_code cpu_mb_gen_code
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259 | 4acb54ba | Edgar E. Iglesias | #define cpu_signal_handler cpu_mb_signal_handler
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260 | 4acb54ba | Edgar E. Iglesias | |
261 | 4acb54ba | Edgar E. Iglesias | #define CPU_SAVE_VERSION 1 |
262 | 4acb54ba | Edgar E. Iglesias | |
263 | 4acb54ba | Edgar E. Iglesias | /* MMU modes definitions */
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264 | 4acb54ba | Edgar E. Iglesias | #define MMU_MODE0_SUFFIX _nommu
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265 | 4acb54ba | Edgar E. Iglesias | #define MMU_MODE1_SUFFIX _kernel
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266 | 4acb54ba | Edgar E. Iglesias | #define MMU_MODE2_SUFFIX _user
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267 | 4acb54ba | Edgar E. Iglesias | #define MMU_NOMMU_IDX 0 |
268 | 4acb54ba | Edgar E. Iglesias | #define MMU_KERNEL_IDX 1 |
269 | 4acb54ba | Edgar E. Iglesias | #define MMU_USER_IDX 2 |
270 | 4acb54ba | Edgar E. Iglesias | /* See NB_MMU_MODES further up the file. */
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271 | 4acb54ba | Edgar E. Iglesias | |
272 | 4acb54ba | Edgar E. Iglesias | static inline int cpu_mmu_index (CPUState *env) |
273 | 4acb54ba | Edgar E. Iglesias | { |
274 | 4acb54ba | Edgar E. Iglesias | /* Are we in nommu mode?. */
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275 | 4acb54ba | Edgar E. Iglesias | if (!(env->sregs[SR_MSR] & MSR_VM))
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276 | 4acb54ba | Edgar E. Iglesias | return MMU_NOMMU_IDX;
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277 | 4acb54ba | Edgar E. Iglesias | |
278 | 4acb54ba | Edgar E. Iglesias | if (env->sregs[SR_MSR] & MSR_UM)
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279 | 4acb54ba | Edgar E. Iglesias | return MMU_USER_IDX;
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280 | 4acb54ba | Edgar E. Iglesias | return MMU_KERNEL_IDX;
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281 | 4acb54ba | Edgar E. Iglesias | } |
282 | 4acb54ba | Edgar E. Iglesias | |
283 | 4acb54ba | Edgar E. Iglesias | int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
284 | 4acb54ba | Edgar E. Iglesias | int mmu_idx, int is_softmmu); |
285 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
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286 | 4acb54ba | Edgar E. Iglesias | |
287 | 4acb54ba | Edgar E. Iglesias | #if defined(CONFIG_USER_ONLY)
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288 | 4acb54ba | Edgar E. Iglesias | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
289 | 4acb54ba | Edgar E. Iglesias | { |
290 | 4acb54ba | Edgar E. Iglesias | if (newsp)
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291 | 4acb54ba | Edgar E. Iglesias | env->regs[R_SP] = newsp; |
292 | 4acb54ba | Edgar E. Iglesias | env->regs[3] = 0; |
293 | 4acb54ba | Edgar E. Iglesias | } |
294 | 4acb54ba | Edgar E. Iglesias | #endif
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295 | 4acb54ba | Edgar E. Iglesias | |
296 | 4acb54ba | Edgar E. Iglesias | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
297 | 4acb54ba | Edgar E. Iglesias | { |
298 | 4acb54ba | Edgar E. Iglesias | } |
299 | 4acb54ba | Edgar E. Iglesias | |
300 | 4acb54ba | Edgar E. Iglesias | static inline int cpu_interrupts_enabled(CPUState *env) |
301 | 4acb54ba | Edgar E. Iglesias | { |
302 | 4acb54ba | Edgar E. Iglesias | return env->sregs[SR_MSR] & MSR_IE;
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303 | 4acb54ba | Edgar E. Iglesias | } |
304 | 4acb54ba | Edgar E. Iglesias | |
305 | 4acb54ba | Edgar E. Iglesias | #include "cpu-all.h" |
306 | 4acb54ba | Edgar E. Iglesias | #include "exec-all.h" |
307 | 4acb54ba | Edgar E. Iglesias | |
308 | 4acb54ba | Edgar E. Iglesias | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
309 | 4acb54ba | Edgar E. Iglesias | { |
310 | 4acb54ba | Edgar E. Iglesias | env->sregs[SR_PC] = tb->pc; |
311 | 4acb54ba | Edgar E. Iglesias | } |
312 | 4acb54ba | Edgar E. Iglesias | |
313 | 4acb54ba | Edgar E. Iglesias | static inline target_ulong cpu_get_pc(CPUState *env) |
314 | 4acb54ba | Edgar E. Iglesias | { |
315 | 4acb54ba | Edgar E. Iglesias | return env->sregs[SR_PC];
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316 | 4acb54ba | Edgar E. Iglesias | } |
317 | 4acb54ba | Edgar E. Iglesias | |
318 | 4acb54ba | Edgar E. Iglesias | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
319 | 4acb54ba | Edgar E. Iglesias | target_ulong *cs_base, int *flags)
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320 | 4acb54ba | Edgar E. Iglesias | { |
321 | 4acb54ba | Edgar E. Iglesias | *pc = env->sregs[SR_PC]; |
322 | 4acb54ba | Edgar E. Iglesias | *cs_base = 0;
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323 | cedb936b | Edgar E. Iglesias | env->iflags |= env->sregs[SR_MSR] & MSR_EE; |
324 | 4acb54ba | Edgar E. Iglesias | *flags = env->iflags & IFLAGS_TB_MASK; |
325 | 4acb54ba | Edgar E. Iglesias | } |
326 | faed1c2a | Edgar E. Iglesias | |
327 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
328 | faed1c2a | Edgar E. Iglesias | int is_asi, int size); |
329 | 4acb54ba | Edgar E. Iglesias | #endif |