Revision 13b55754
| b/cpu-i386.h | ||
|---|---|---|
| 85 | 85 |
#define VIP_MASK 0x00100000 |
| 86 | 86 |
#define ID_MASK 0x00200000 |
| 87 | 87 |
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| 88 |
#define CR0_PE_MASK (1 << 0) |
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| 89 |
#define CR0_TS_MASK (1 << 3) |
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| 90 |
#define CR0_WP_MASK (1 << 16) |
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| 91 |
#define CR0_AM_MASK (1 << 18) |
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| 92 |
#define CR0_PG_MASK (1 << 31) |
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| 93 |
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| 94 |
#define CR4_VME_MASK (1 << 0) |
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#define CR4_PVI_MASK (1 << 1) |
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#define CR4_TSD_MASK (1 << 2) |
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#define CR4_DE_MASK (1 << 3) |
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| 98 |
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| 88 | 99 |
#define EXCP00_DIVZ 0 |
| 89 | 100 |
#define EXCP01_SSTP 1 |
| 90 | 101 |
#define EXCP02_NMI 2 |
| ... | ... | |
| 161 | 172 |
#endif |
| 162 | 173 |
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| 163 | 174 |
typedef struct SegmentCache {
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uint32_t selector; |
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| 164 | 176 |
uint8_t *base; |
| 165 | 177 |
unsigned long limit; |
| 166 | 178 |
uint8_t seg_32bit; |
| 167 | 179 |
} SegmentCache; |
| 168 | 180 |
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typedef struct SegmentDescriptorTable {
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uint8_t *base; |
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unsigned long limit; |
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/* this is the returned base when reading the register, just to |
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avoid that the emulated program modifies it */ |
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unsigned long emu_base; |
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} SegmentDescriptorTable; |
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| 177 | 181 |
typedef struct CPUX86State {
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| 178 | 182 |
/* standard registers */ |
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uint32_t regs[8]; |
| ... | ... | |
| 205 | 209 |
} fp_convert; |
| 206 | 210 |
|
| 207 | 211 |
/* segments */ |
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uint32_t segs[6]; /* selector values */
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SegmentCache seg_cache[6]; /* info taken from LDT/GDT */
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SegmentDescriptorTable gdt;
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SegmentDescriptorTable ldt;
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SegmentDescriptorTable idt;
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SegmentCache segs[6]; /* selector values */
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SegmentCache ldt;
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SegmentCache tr;
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SegmentCache gdt; /* only base and limit are used */
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SegmentCache idt; /* only base and limit are used */
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| 213 | 217 |
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| 214 | 218 |
/* exception/interrupt handling */ |
| 215 | 219 |
jmp_buf jmp_env; |
| 216 | 220 |
int exception_index; |
| 217 | 221 |
int error_code; |
| 218 |
uint32_t cr2; |
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uint32_t cr[5]; /* NOTE: cr1 is unused */ |
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uint32_t dr[8]; /* debug registers */ |
|
| 219 | 224 |
int interrupt_request; |
| 220 | 225 |
|
| 221 | 226 |
/* user data */ |
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