root / hw / puv3_dma.c @ 13ef70f6
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1 | 1ea34899 | Guan Xuetao | /*
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2 | 1ea34899 | Guan Xuetao | * DMA device simulation in PKUnity SoC
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3 | 1ea34899 | Guan Xuetao | *
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4 | 1ea34899 | Guan Xuetao | * Copyright (C) 2010-2012 Guan Xuetao
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5 | 1ea34899 | Guan Xuetao | *
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6 | 1ea34899 | Guan Xuetao | * This program is free software; you can redistribute it and/or modify
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7 | 1ea34899 | Guan Xuetao | * it under the terms of the GNU General Public License version 2 as
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8 | 1ea34899 | Guan Xuetao | * published by the Free Software Foundation, or any later version.
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9 | 1ea34899 | Guan Xuetao | * See the COPYING file in the top-level directory.
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10 | 1ea34899 | Guan Xuetao | */
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11 | 1ea34899 | Guan Xuetao | #include "hw.h" |
12 | 1ea34899 | Guan Xuetao | #include "sysbus.h" |
13 | 1ea34899 | Guan Xuetao | |
14 | 1ea34899 | Guan Xuetao | #undef DEBUG_PUV3
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15 | 1ea34899 | Guan Xuetao | #include "puv3.h" |
16 | 1ea34899 | Guan Xuetao | |
17 | 1ea34899 | Guan Xuetao | #define PUV3_DMA_CH_NR (6) |
18 | 1ea34899 | Guan Xuetao | #define PUV3_DMA_CH_MASK (0xff) |
19 | 1ea34899 | Guan Xuetao | #define PUV3_DMA_CH(offset) ((offset) >> 8) |
20 | 1ea34899 | Guan Xuetao | |
21 | 1ea34899 | Guan Xuetao | typedef struct { |
22 | 1ea34899 | Guan Xuetao | SysBusDevice busdev; |
23 | 1ea34899 | Guan Xuetao | MemoryRegion iomem; |
24 | 1ea34899 | Guan Xuetao | uint32_t reg_CFG[PUV3_DMA_CH_NR]; |
25 | 1ea34899 | Guan Xuetao | } PUV3DMAState; |
26 | 1ea34899 | Guan Xuetao | |
27 | 1ea34899 | Guan Xuetao | static uint64_t puv3_dma_read(void *opaque, target_phys_addr_t offset, |
28 | 1ea34899 | Guan Xuetao | unsigned size)
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29 | 1ea34899 | Guan Xuetao | { |
30 | 1ea34899 | Guan Xuetao | PUV3DMAState *s = opaque; |
31 | 1ea34899 | Guan Xuetao | uint32_t ret = 0;
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32 | 1ea34899 | Guan Xuetao | |
33 | 1ea34899 | Guan Xuetao | assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR); |
34 | 1ea34899 | Guan Xuetao | |
35 | 1ea34899 | Guan Xuetao | switch (offset & PUV3_DMA_CH_MASK) {
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36 | 1ea34899 | Guan Xuetao | case 0x10: |
37 | 1ea34899 | Guan Xuetao | ret = s->reg_CFG[PUV3_DMA_CH(offset)]; |
38 | 1ea34899 | Guan Xuetao | break;
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39 | 1ea34899 | Guan Xuetao | default:
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40 | 1ea34899 | Guan Xuetao | DPRINTF("Bad offset 0x%x\n", offset);
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41 | 1ea34899 | Guan Xuetao | } |
42 | 1ea34899 | Guan Xuetao | DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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43 | 1ea34899 | Guan Xuetao | |
44 | 1ea34899 | Guan Xuetao | return ret;
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45 | 1ea34899 | Guan Xuetao | } |
46 | 1ea34899 | Guan Xuetao | |
47 | 1ea34899 | Guan Xuetao | static void puv3_dma_write(void *opaque, target_phys_addr_t offset, |
48 | 1ea34899 | Guan Xuetao | uint64_t value, unsigned size)
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49 | 1ea34899 | Guan Xuetao | { |
50 | 1ea34899 | Guan Xuetao | PUV3DMAState *s = opaque; |
51 | 1ea34899 | Guan Xuetao | |
52 | 1ea34899 | Guan Xuetao | assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR); |
53 | 1ea34899 | Guan Xuetao | |
54 | 1ea34899 | Guan Xuetao | switch (offset & PUV3_DMA_CH_MASK) {
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55 | 1ea34899 | Guan Xuetao | case 0x10: |
56 | 1ea34899 | Guan Xuetao | s->reg_CFG[PUV3_DMA_CH(offset)] = value; |
57 | 1ea34899 | Guan Xuetao | break;
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58 | 1ea34899 | Guan Xuetao | default:
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59 | 1ea34899 | Guan Xuetao | DPRINTF("Bad offset 0x%x\n", offset);
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60 | 1ea34899 | Guan Xuetao | } |
61 | 1ea34899 | Guan Xuetao | DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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62 | 1ea34899 | Guan Xuetao | } |
63 | 1ea34899 | Guan Xuetao | |
64 | 1ea34899 | Guan Xuetao | static const MemoryRegionOps puv3_dma_ops = { |
65 | 1ea34899 | Guan Xuetao | .read = puv3_dma_read, |
66 | 1ea34899 | Guan Xuetao | .write = puv3_dma_write, |
67 | 1ea34899 | Guan Xuetao | .impl = { |
68 | 1ea34899 | Guan Xuetao | .min_access_size = 4,
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69 | 1ea34899 | Guan Xuetao | .max_access_size = 4,
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70 | 1ea34899 | Guan Xuetao | }, |
71 | 1ea34899 | Guan Xuetao | .endianness = DEVICE_NATIVE_ENDIAN, |
72 | 1ea34899 | Guan Xuetao | }; |
73 | 1ea34899 | Guan Xuetao | |
74 | 1ea34899 | Guan Xuetao | static int puv3_dma_init(SysBusDevice *dev) |
75 | 1ea34899 | Guan Xuetao | { |
76 | 1ea34899 | Guan Xuetao | PUV3DMAState *s = FROM_SYSBUS(PUV3DMAState, dev); |
77 | 1ea34899 | Guan Xuetao | int i;
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78 | 1ea34899 | Guan Xuetao | |
79 | 1ea34899 | Guan Xuetao | for (i = 0; i < PUV3_DMA_CH_NR; i++) { |
80 | 1ea34899 | Guan Xuetao | s->reg_CFG[i] = 0x0;
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81 | 1ea34899 | Guan Xuetao | } |
82 | 1ea34899 | Guan Xuetao | |
83 | 1ea34899 | Guan Xuetao | memory_region_init_io(&s->iomem, &puv3_dma_ops, s, "puv3_dma",
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84 | 1ea34899 | Guan Xuetao | PUV3_REGS_OFFSET); |
85 | 1ea34899 | Guan Xuetao | sysbus_init_mmio(dev, &s->iomem); |
86 | 1ea34899 | Guan Xuetao | |
87 | 1ea34899 | Guan Xuetao | return 0; |
88 | 1ea34899 | Guan Xuetao | } |
89 | 1ea34899 | Guan Xuetao | |
90 | 1ea34899 | Guan Xuetao | static void puv3_dma_class_init(ObjectClass *klass, void *data) |
91 | 1ea34899 | Guan Xuetao | { |
92 | 1ea34899 | Guan Xuetao | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); |
93 | 1ea34899 | Guan Xuetao | |
94 | 1ea34899 | Guan Xuetao | sdc->init = puv3_dma_init; |
95 | 1ea34899 | Guan Xuetao | } |
96 | 1ea34899 | Guan Xuetao | |
97 | 1ea34899 | Guan Xuetao | static const TypeInfo puv3_dma_info = { |
98 | 1ea34899 | Guan Xuetao | .name = "puv3_dma",
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99 | 1ea34899 | Guan Xuetao | .parent = TYPE_SYS_BUS_DEVICE, |
100 | 1ea34899 | Guan Xuetao | .instance_size = sizeof(PUV3DMAState),
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101 | 1ea34899 | Guan Xuetao | .class_init = puv3_dma_class_init, |
102 | 1ea34899 | Guan Xuetao | }; |
103 | 1ea34899 | Guan Xuetao | |
104 | 1ea34899 | Guan Xuetao | static void puv3_dma_register_type(void) |
105 | 1ea34899 | Guan Xuetao | { |
106 | 1ea34899 | Guan Xuetao | type_register_static(&puv3_dma_info); |
107 | 1ea34899 | Guan Xuetao | } |
108 | 1ea34899 | Guan Xuetao | |
109 | 1ea34899 | Guan Xuetao | type_init(puv3_dma_register_type) |