Revision 142593c9
b/hw/arm/digic.c | ||
---|---|---|
24 | 24 |
|
25 | 25 |
#define DIGIC4_TIMER_BASE(n) (0xc0210000 + (n) * 0x100) |
26 | 26 |
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27 |
#define DIGIC_UART_BASE 0xc0800000 |
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28 |
|
|
27 | 29 |
static void digic_init(Object *obj) |
28 | 30 |
{ |
29 | 31 |
DigicState *s = DIGIC(obj); |
... | ... | |
43 | 45 |
snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i); |
44 | 46 |
object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL); |
45 | 47 |
} |
48 |
|
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49 |
object_initialize(&s->uart, sizeof(s->uart), TYPE_DIGIC_UART); |
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dev = DEVICE(&s->uart); |
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qdev_set_parent_bus(dev, sysbus_get_default()); |
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52 |
object_property_add_child(obj, "uart", OBJECT(&s->uart), NULL); |
|
46 | 53 |
} |
47 | 54 |
|
48 | 55 |
static void digic_realize(DeviceState *dev, Error **errp) |
... | ... | |
74 | 81 |
sbd = SYS_BUS_DEVICE(&s->timer[i]); |
75 | 82 |
sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i)); |
76 | 83 |
} |
84 |
|
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85 |
object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); |
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86 |
if (err != NULL) { |
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error_propagate(errp, err); |
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return; |
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} |
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90 |
|
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sbd = SYS_BUS_DEVICE(&s->uart); |
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sysbus_mmio_map(sbd, 0, DIGIC_UART_BASE); |
|
77 | 93 |
} |
78 | 94 |
|
79 | 95 |
static void digic_class_init(ObjectClass *oc, void *data) |
b/hw/char/Makefile.objs | ||
---|---|---|
14 | 14 |
obj-$(CONFIG_OMAP) += omap_uart.o |
15 | 15 |
obj-$(CONFIG_SH4) += sh_serial.o |
16 | 16 |
obj-$(CONFIG_PSERIES) += spapr_vty.o |
17 |
obj-$(CONFIG_DIGIC) += digic-uart.o |
|
17 | 18 |
|
18 | 19 |
common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o |
19 | 20 |
common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o |
b/hw/char/digic-uart.c | ||
---|---|---|
1 |
/* |
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2 |
* QEMU model of the Canon DIGIC UART block. |
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3 |
* |
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4 |
* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> |
|
5 |
* |
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* This model is based on reverse engineering efforts |
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* made by CHDK (http://chdk.wikia.com) and |
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* Magic Lantern (http://www.magiclantern.fm) projects |
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* contributors. |
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10 |
* |
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* See "Serial terminal" docs here: |
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12 |
* http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers |
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13 |
* |
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* The QEMU model of the Milkymist UART block by Michael Walle |
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* is used as a template. |
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16 |
* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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20 |
* (at your option) any later version. |
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21 |
* |
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* This program is distributed in the hope that it will be useful, |
|
23 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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24 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
|
26 |
* |
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27 |
*/ |
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28 |
|
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29 |
#include "hw/hw.h" |
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#include "hw/sysbus.h" |
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#include "sysemu/char.h" |
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32 |
|
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#include "hw/char/digic-uart.h" |
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34 |
|
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enum { |
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ST_RX_RDY = (1 << 0), |
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ST_TX_RDY = (1 << 1), |
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}; |
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39 |
|
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40 |
static uint64_t digic_uart_read(void *opaque, hwaddr addr, |
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unsigned size) |
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42 |
{ |
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43 |
DigicUartState *s = opaque; |
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uint64_t ret = 0; |
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45 |
|
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addr >>= 2; |
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47 |
|
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48 |
switch (addr) { |
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case R_RX: |
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s->reg_st &= ~(ST_RX_RDY); |
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ret = s->reg_rx; |
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break; |
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53 |
|
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case R_ST: |
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ret = s->reg_st; |
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56 |
break; |
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57 |
|
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58 |
default: |
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qemu_log_mask(LOG_UNIMP, |
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"digic-uart: read access to unknown register 0x" |
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61 |
TARGET_FMT_plx, addr << 2); |
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62 |
} |
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63 |
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return ret; |
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} |
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66 |
|
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67 |
static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value, |
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unsigned size) |
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69 |
{ |
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DigicUartState *s = opaque; |
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unsigned char ch = value; |
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72 |
|
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addr >>= 2; |
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74 |
|
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75 |
switch (addr) { |
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76 |
case R_TX: |
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77 |
if (s->chr) { |
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78 |
qemu_chr_fe_write_all(s->chr, &ch, 1); |
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79 |
} |
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80 |
break; |
|
81 |
|
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82 |
case R_ST: |
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/* |
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* Ignore write to R_ST. |
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85 |
* |
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* The point is that this register is actively used |
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* during receiving and transmitting symbols, |
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* but we don't know the function of most of bits. |
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* |
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* Ignoring writes to R_ST is only a simplification |
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* of the model. It has no perceptible side effects |
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* for existing guests. |
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93 |
*/ |
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94 |
break; |
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95 |
|
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96 |
default: |
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97 |
qemu_log_mask(LOG_UNIMP, |
|
98 |
"digic-uart: write access to unknown register 0x" |
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99 |
TARGET_FMT_plx, addr << 2); |
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100 |
} |
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101 |
} |
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102 |
|
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103 |
static const MemoryRegionOps uart_mmio_ops = { |
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.read = digic_uart_read, |
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105 |
.write = digic_uart_write, |
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106 |
.valid = { |
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107 |
.min_access_size = 4, |
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108 |
.max_access_size = 4, |
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109 |
}, |
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110 |
.endianness = DEVICE_NATIVE_ENDIAN, |
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111 |
}; |
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112 |
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113 |
static int uart_can_rx(void *opaque) |
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114 |
{ |
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115 |
DigicUartState *s = opaque; |
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116 |
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117 |
return !(s->reg_st & ST_RX_RDY); |
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118 |
} |
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119 |
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120 |
static void uart_rx(void *opaque, const uint8_t *buf, int size) |
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121 |
{ |
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122 |
DigicUartState *s = opaque; |
|
123 |
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124 |
assert(uart_can_rx(opaque)); |
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125 |
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126 |
s->reg_st |= ST_RX_RDY; |
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127 |
s->reg_rx = *buf; |
|
128 |
} |
|
129 |
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130 |
static void uart_event(void *opaque, int event) |
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131 |
{ |
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132 |
} |
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133 |
|
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134 |
static void digic_uart_reset(DeviceState *d) |
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135 |
{ |
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136 |
DigicUartState *s = DIGIC_UART(d); |
|
137 |
|
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138 |
s->reg_rx = 0; |
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139 |
s->reg_st = ST_TX_RDY; |
|
140 |
} |
|
141 |
|
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142 |
static void digic_uart_realize(DeviceState *dev, Error **errp) |
|
143 |
{ |
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144 |
DigicUartState *s = DIGIC_UART(dev); |
|
145 |
|
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146 |
s->chr = qemu_char_get_next_serial(); |
|
147 |
if (s->chr) { |
|
148 |
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); |
|
149 |
} |
|
150 |
} |
|
151 |
|
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152 |
static void digic_uart_init(Object *obj) |
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153 |
{ |
|
154 |
DigicUartState *s = DIGIC_UART(obj); |
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155 |
|
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156 |
memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s, |
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157 |
TYPE_DIGIC_UART, 0x18); |
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158 |
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region); |
|
159 |
} |
|
160 |
|
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161 |
static const VMStateDescription vmstate_digic_uart = { |
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162 |
.name = "digic-uart", |
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163 |
.version_id = 1, |
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164 |
.minimum_version_id = 1, |
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165 |
.minimum_version_id_old = 1, |
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166 |
.fields = (VMStateField[]) { |
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167 |
VMSTATE_UINT32(reg_rx, DigicUartState), |
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168 |
VMSTATE_UINT32(reg_st, DigicUartState), |
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169 |
VMSTATE_END_OF_LIST() |
|
170 |
} |
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171 |
}; |
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172 |
|
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173 |
static void digic_uart_class_init(ObjectClass *klass, void *data) |
|
174 |
{ |
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175 |
DeviceClass *dc = DEVICE_CLASS(klass); |
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176 |
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177 |
dc->realize = digic_uart_realize; |
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178 |
dc->reset = digic_uart_reset; |
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179 |
dc->vmsd = &vmstate_digic_uart; |
|
180 |
} |
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181 |
|
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182 |
static const TypeInfo digic_uart_info = { |
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.name = TYPE_DIGIC_UART, |
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184 |
.parent = TYPE_SYS_BUS_DEVICE, |
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185 |
.instance_size = sizeof(DigicUartState), |
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.instance_init = digic_uart_init, |
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187 |
.class_init = digic_uart_class_init, |
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188 |
}; |
|
189 |
|
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190 |
static void digic_uart_register_types(void) |
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191 |
{ |
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192 |
type_register_static(&digic_uart_info); |
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} |
|
194 |
|
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195 |
type_init(digic_uart_register_types) |
b/include/hw/arm/digic.h | ||
---|---|---|
21 | 21 |
#include "cpu.h" |
22 | 22 |
|
23 | 23 |
#include "hw/timer/digic-timer.h" |
24 |
#include "hw/char/digic-uart.h" |
|
24 | 25 |
|
25 | 26 |
#define TYPE_DIGIC "digic" |
26 | 27 |
|
... | ... | |
36 | 37 |
ARMCPU cpu; |
37 | 38 |
|
38 | 39 |
DigicTimerState timer[DIGIC4_NB_TIMERS]; |
40 |
DigicUartState uart; |
|
39 | 41 |
} DigicState; |
40 | 42 |
|
41 | 43 |
#endif /* HW_ARM_DIGIC_H */ |
b/include/hw/char/digic-uart.h | ||
---|---|---|
1 |
/* |
|
2 |
* Canon DIGIC UART block declarations. |
|
3 |
* |
|
4 |
* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com> |
|
5 |
* |
|
6 |
* This program is free software; you can redistribute it and/or modify |
|
7 |
* it under the terms of the GNU General Public License as published by |
|
8 |
* the Free Software Foundation; either version 2 of the License, or |
|
9 |
* (at your option) any later version. |
|
10 |
* |
|
11 |
* This program is distributed in the hope that it will be useful, |
|
12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
14 |
* GNU General Public License for more details. |
|
15 |
* |
|
16 |
*/ |
|
17 |
|
|
18 |
#ifndef HW_CHAR_DIGIC_UART_H |
|
19 |
#define HW_CHAR_DIGIC_UART_H |
|
20 |
|
|
21 |
#include "hw/sysbus.h" |
|
22 |
#include "qemu/typedefs.h" |
|
23 |
|
|
24 |
#define TYPE_DIGIC_UART "digic-uart" |
|
25 |
#define DIGIC_UART(obj) \ |
|
26 |
OBJECT_CHECK(DigicUartState, (obj), TYPE_DIGIC_UART) |
|
27 |
|
|
28 |
enum { |
|
29 |
R_TX = 0x00, |
|
30 |
R_RX, |
|
31 |
R_ST = (0x14 >> 2), |
|
32 |
R_MAX |
|
33 |
}; |
|
34 |
|
|
35 |
typedef struct DigicUartState { |
|
36 |
/*< private >*/ |
|
37 |
SysBusDevice parent_obj; |
|
38 |
/*< public >*/ |
|
39 |
|
|
40 |
MemoryRegion regs_region; |
|
41 |
CharDriverState *chr; |
|
42 |
|
|
43 |
uint32_t reg_rx; |
|
44 |
uint32_t reg_st; |
|
45 |
} DigicUartState; |
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46 |
|
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47 |
#endif /* HW_CHAR_DIGIC_UART_H */ |
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