root / hw / pc.c @ 1452411b
History | View | Annotate | Download (44.7 kB)
1 |
/*
|
---|---|
2 |
* QEMU PC System Emulator
|
3 |
*
|
4 |
* Copyright (c) 2003-2004 Fabrice Bellard
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "hw.h" |
25 |
#include "pc.h" |
26 |
#include "fdc.h" |
27 |
#include "pci.h" |
28 |
#include "block.h" |
29 |
#include "sysemu.h" |
30 |
#include "audio/audio.h" |
31 |
#include "net.h" |
32 |
#include "smbus.h" |
33 |
#include "boards.h" |
34 |
#include "monitor.h" |
35 |
#include "fw_cfg.h" |
36 |
#include "hpet_emul.h" |
37 |
#include "watchdog.h" |
38 |
#include "smbios.h" |
39 |
|
40 |
/* output Bochs bios info messages */
|
41 |
//#define DEBUG_BIOS
|
42 |
|
43 |
/* Show multiboot debug output */
|
44 |
//#define DEBUG_MULTIBOOT
|
45 |
|
46 |
#define BIOS_FILENAME "bios.bin" |
47 |
#define VGABIOS_FILENAME "vgabios.bin" |
48 |
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" |
49 |
|
50 |
#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
51 |
|
52 |
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
|
53 |
#define ACPI_DATA_SIZE 0x10000 |
54 |
#define BIOS_CFG_IOPORT 0x510 |
55 |
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
56 |
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
57 |
#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
58 |
|
59 |
#define MAX_IDE_BUS 2 |
60 |
|
61 |
static fdctrl_t *floppy_controller;
|
62 |
static RTCState *rtc_state;
|
63 |
static PITState *pit;
|
64 |
static IOAPICState *ioapic;
|
65 |
static PCIDevice *i440fx_state;
|
66 |
|
67 |
typedef struct rom_reset_data { |
68 |
uint8_t *data; |
69 |
target_phys_addr_t addr; |
70 |
unsigned size;
|
71 |
} RomResetData; |
72 |
|
73 |
static void option_rom_reset(void *_rrd) |
74 |
{ |
75 |
RomResetData *rrd = _rrd; |
76 |
|
77 |
cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size); |
78 |
} |
79 |
|
80 |
static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size) |
81 |
{ |
82 |
RomResetData *rrd = qemu_malloc(sizeof *rrd);
|
83 |
|
84 |
rrd->data = qemu_malloc(size); |
85 |
cpu_physical_memory_read(addr, rrd->data, size); |
86 |
rrd->addr = addr; |
87 |
rrd->size = size; |
88 |
qemu_register_reset(option_rom_reset, rrd); |
89 |
} |
90 |
|
91 |
typedef struct isa_irq_state { |
92 |
qemu_irq *i8259; |
93 |
} IsaIrqState; |
94 |
|
95 |
static void isa_irq_handler(void *opaque, int n, int level) |
96 |
{ |
97 |
IsaIrqState *isa = (IsaIrqState *)opaque; |
98 |
|
99 |
qemu_set_irq(isa->i8259[n], level); |
100 |
} |
101 |
|
102 |
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
103 |
{ |
104 |
} |
105 |
|
106 |
/* MSDOS compatibility mode FPU exception support */
|
107 |
static qemu_irq ferr_irq;
|
108 |
/* XXX: add IGNNE support */
|
109 |
void cpu_set_ferr(CPUX86State *s)
|
110 |
{ |
111 |
qemu_irq_raise(ferr_irq); |
112 |
} |
113 |
|
114 |
static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
115 |
{ |
116 |
qemu_irq_lower(ferr_irq); |
117 |
} |
118 |
|
119 |
/* TSC handling */
|
120 |
uint64_t cpu_get_tsc(CPUX86State *env) |
121 |
{ |
122 |
/* Note: when using kqemu, it is more logical to return the host TSC
|
123 |
because kqemu does not trap the RDTSC instruction for
|
124 |
performance reasons */
|
125 |
#ifdef CONFIG_KQEMU
|
126 |
if (env->kqemu_enabled) {
|
127 |
return cpu_get_real_ticks();
|
128 |
} else
|
129 |
#endif
|
130 |
{ |
131 |
return cpu_get_ticks();
|
132 |
} |
133 |
} |
134 |
|
135 |
/* SMM support */
|
136 |
void cpu_smm_update(CPUState *env)
|
137 |
{ |
138 |
if (i440fx_state && env == first_cpu)
|
139 |
i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
|
140 |
} |
141 |
|
142 |
|
143 |
/* IRQ handling */
|
144 |
int cpu_get_pic_interrupt(CPUState *env)
|
145 |
{ |
146 |
int intno;
|
147 |
|
148 |
intno = apic_get_interrupt(env); |
149 |
if (intno >= 0) { |
150 |
/* set irq request if a PIC irq is still pending */
|
151 |
/* XXX: improve that */
|
152 |
pic_update_irq(isa_pic); |
153 |
return intno;
|
154 |
} |
155 |
/* read the irq from the PIC */
|
156 |
if (!apic_accept_pic_intr(env))
|
157 |
return -1; |
158 |
|
159 |
intno = pic_read_irq(isa_pic); |
160 |
return intno;
|
161 |
} |
162 |
|
163 |
static void pic_irq_request(void *opaque, int irq, int level) |
164 |
{ |
165 |
CPUState *env = first_cpu; |
166 |
|
167 |
if (env->apic_state) {
|
168 |
while (env) {
|
169 |
if (apic_accept_pic_intr(env))
|
170 |
apic_deliver_pic_intr(env, level); |
171 |
env = env->next_cpu; |
172 |
} |
173 |
} else {
|
174 |
if (level)
|
175 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
176 |
else
|
177 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
178 |
} |
179 |
} |
180 |
|
181 |
/* PC cmos mappings */
|
182 |
|
183 |
#define REG_EQUIPMENT_BYTE 0x14 |
184 |
|
185 |
static int cmos_get_fd_drive_type(int fd0) |
186 |
{ |
187 |
int val;
|
188 |
|
189 |
switch (fd0) {
|
190 |
case 0: |
191 |
/* 1.44 Mb 3"5 drive */
|
192 |
val = 4;
|
193 |
break;
|
194 |
case 1: |
195 |
/* 2.88 Mb 3"5 drive */
|
196 |
val = 5;
|
197 |
break;
|
198 |
case 2: |
199 |
/* 1.2 Mb 5"5 drive */
|
200 |
val = 2;
|
201 |
break;
|
202 |
default:
|
203 |
val = 0;
|
204 |
break;
|
205 |
} |
206 |
return val;
|
207 |
} |
208 |
|
209 |
static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd) |
210 |
{ |
211 |
RTCState *s = rtc_state; |
212 |
int cylinders, heads, sectors;
|
213 |
bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
214 |
rtc_set_memory(s, type_ofs, 47);
|
215 |
rtc_set_memory(s, info_ofs, cylinders); |
216 |
rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
217 |
rtc_set_memory(s, info_ofs + 2, heads);
|
218 |
rtc_set_memory(s, info_ofs + 3, 0xff); |
219 |
rtc_set_memory(s, info_ofs + 4, 0xff); |
220 |
rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
221 |
rtc_set_memory(s, info_ofs + 6, cylinders);
|
222 |
rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
223 |
rtc_set_memory(s, info_ofs + 8, sectors);
|
224 |
} |
225 |
|
226 |
/* convert boot_device letter to something recognizable by the bios */
|
227 |
static int boot_device2nibble(char boot_device) |
228 |
{ |
229 |
switch(boot_device) {
|
230 |
case 'a': |
231 |
case 'b': |
232 |
return 0x01; /* floppy boot */ |
233 |
case 'c': |
234 |
return 0x02; /* hard drive boot */ |
235 |
case 'd': |
236 |
return 0x03; /* CD-ROM boot */ |
237 |
case 'n': |
238 |
return 0x04; /* Network boot */ |
239 |
} |
240 |
return 0; |
241 |
} |
242 |
|
243 |
/* copy/pasted from cmos_init, should be made a general function
|
244 |
and used there as well */
|
245 |
static int pc_boot_set(void *opaque, const char *boot_device) |
246 |
{ |
247 |
Monitor *mon = cur_mon; |
248 |
#define PC_MAX_BOOT_DEVICES 3 |
249 |
RTCState *s = (RTCState *)opaque; |
250 |
int nbds, bds[3] = { 0, }; |
251 |
int i;
|
252 |
|
253 |
nbds = strlen(boot_device); |
254 |
if (nbds > PC_MAX_BOOT_DEVICES) {
|
255 |
monitor_printf(mon, "Too many boot devices for PC\n");
|
256 |
return(1); |
257 |
} |
258 |
for (i = 0; i < nbds; i++) { |
259 |
bds[i] = boot_device2nibble(boot_device[i]); |
260 |
if (bds[i] == 0) { |
261 |
monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
|
262 |
boot_device[i]); |
263 |
return(1); |
264 |
} |
265 |
} |
266 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
267 |
rtc_set_memory(s, 0x38, (bds[2] << 4)); |
268 |
return(0); |
269 |
} |
270 |
|
271 |
/* hd_table must contain 4 block drivers */
|
272 |
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, |
273 |
const char *boot_device, BlockDriverState **hd_table) |
274 |
{ |
275 |
RTCState *s = rtc_state; |
276 |
int nbds, bds[3] = { 0, }; |
277 |
int val;
|
278 |
int fd0, fd1, nb;
|
279 |
int i;
|
280 |
|
281 |
/* various important CMOS locations needed by PC/Bochs bios */
|
282 |
|
283 |
/* memory size */
|
284 |
val = 640; /* base memory in K */ |
285 |
rtc_set_memory(s, 0x15, val);
|
286 |
rtc_set_memory(s, 0x16, val >> 8); |
287 |
|
288 |
val = (ram_size / 1024) - 1024; |
289 |
if (val > 65535) |
290 |
val = 65535;
|
291 |
rtc_set_memory(s, 0x17, val);
|
292 |
rtc_set_memory(s, 0x18, val >> 8); |
293 |
rtc_set_memory(s, 0x30, val);
|
294 |
rtc_set_memory(s, 0x31, val >> 8); |
295 |
|
296 |
if (above_4g_mem_size) {
|
297 |
rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
298 |
rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
299 |
rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
300 |
} |
301 |
|
302 |
if (ram_size > (16 * 1024 * 1024)) |
303 |
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
304 |
else
|
305 |
val = 0;
|
306 |
if (val > 65535) |
307 |
val = 65535;
|
308 |
rtc_set_memory(s, 0x34, val);
|
309 |
rtc_set_memory(s, 0x35, val >> 8); |
310 |
|
311 |
/* set the number of CPU */
|
312 |
rtc_set_memory(s, 0x5f, smp_cpus - 1); |
313 |
|
314 |
/* set boot devices, and disable floppy signature check if requested */
|
315 |
#define PC_MAX_BOOT_DEVICES 3 |
316 |
nbds = strlen(boot_device); |
317 |
if (nbds > PC_MAX_BOOT_DEVICES) {
|
318 |
fprintf(stderr, "Too many boot devices for PC\n");
|
319 |
exit(1);
|
320 |
} |
321 |
for (i = 0; i < nbds; i++) { |
322 |
bds[i] = boot_device2nibble(boot_device[i]); |
323 |
if (bds[i] == 0) { |
324 |
fprintf(stderr, "Invalid boot device for PC: '%c'\n",
|
325 |
boot_device[i]); |
326 |
exit(1);
|
327 |
} |
328 |
} |
329 |
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
330 |
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
331 |
|
332 |
/* floppy type */
|
333 |
|
334 |
fd0 = fdctrl_get_drive_type(floppy_controller, 0);
|
335 |
fd1 = fdctrl_get_drive_type(floppy_controller, 1);
|
336 |
|
337 |
val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
|
338 |
rtc_set_memory(s, 0x10, val);
|
339 |
|
340 |
val = 0;
|
341 |
nb = 0;
|
342 |
if (fd0 < 3) |
343 |
nb++; |
344 |
if (fd1 < 3) |
345 |
nb++; |
346 |
switch (nb) {
|
347 |
case 0: |
348 |
break;
|
349 |
case 1: |
350 |
val |= 0x01; /* 1 drive, ready for boot */ |
351 |
break;
|
352 |
case 2: |
353 |
val |= 0x41; /* 2 drives, ready for boot */ |
354 |
break;
|
355 |
} |
356 |
val |= 0x02; /* FPU is there */ |
357 |
val |= 0x04; /* PS/2 mouse installed */ |
358 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
359 |
|
360 |
/* hard drives */
|
361 |
|
362 |
rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
363 |
if (hd_table[0]) |
364 |
cmos_init_hd(0x19, 0x1b, hd_table[0]); |
365 |
if (hd_table[1]) |
366 |
cmos_init_hd(0x1a, 0x24, hd_table[1]); |
367 |
|
368 |
val = 0;
|
369 |
for (i = 0; i < 4; i++) { |
370 |
if (hd_table[i]) {
|
371 |
int cylinders, heads, sectors, translation;
|
372 |
/* NOTE: bdrv_get_geometry_hint() returns the physical
|
373 |
geometry. It is always such that: 1 <= sects <= 63, 1
|
374 |
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
|
375 |
geometry can be different if a translation is done. */
|
376 |
translation = bdrv_get_translation_hint(hd_table[i]); |
377 |
if (translation == BIOS_ATA_TRANSLATION_AUTO) {
|
378 |
bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
379 |
if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
380 |
/* No translation. */
|
381 |
translation = 0;
|
382 |
} else {
|
383 |
/* LBA translation. */
|
384 |
translation = 1;
|
385 |
} |
386 |
} else {
|
387 |
translation--; |
388 |
} |
389 |
val |= translation << (i * 2);
|
390 |
} |
391 |
} |
392 |
rtc_set_memory(s, 0x39, val);
|
393 |
} |
394 |
|
395 |
void ioport_set_a20(int enable) |
396 |
{ |
397 |
/* XXX: send to all CPUs ? */
|
398 |
cpu_x86_set_a20(first_cpu, enable); |
399 |
} |
400 |
|
401 |
int ioport_get_a20(void) |
402 |
{ |
403 |
return ((first_cpu->a20_mask >> 20) & 1); |
404 |
} |
405 |
|
406 |
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val) |
407 |
{ |
408 |
ioport_set_a20((val >> 1) & 1); |
409 |
/* XXX: bit 0 is fast reset */
|
410 |
} |
411 |
|
412 |
static uint32_t ioport92_read(void *opaque, uint32_t addr) |
413 |
{ |
414 |
return ioport_get_a20() << 1; |
415 |
} |
416 |
|
417 |
/***********************************************************/
|
418 |
/* Bochs BIOS debug ports */
|
419 |
|
420 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
421 |
{ |
422 |
static const char shutdown_str[8] = "Shutdown"; |
423 |
static int shutdown_index = 0; |
424 |
|
425 |
switch(addr) {
|
426 |
/* Bochs BIOS messages */
|
427 |
case 0x400: |
428 |
case 0x401: |
429 |
fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
|
430 |
exit(1);
|
431 |
case 0x402: |
432 |
case 0x403: |
433 |
#ifdef DEBUG_BIOS
|
434 |
fprintf(stderr, "%c", val);
|
435 |
#endif
|
436 |
break;
|
437 |
case 0x8900: |
438 |
/* same as Bochs power off */
|
439 |
if (val == shutdown_str[shutdown_index]) {
|
440 |
shutdown_index++; |
441 |
if (shutdown_index == 8) { |
442 |
shutdown_index = 0;
|
443 |
qemu_system_shutdown_request(); |
444 |
} |
445 |
} else {
|
446 |
shutdown_index = 0;
|
447 |
} |
448 |
break;
|
449 |
|
450 |
/* LGPL'ed VGA BIOS messages */
|
451 |
case 0x501: |
452 |
case 0x502: |
453 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
454 |
exit(1);
|
455 |
case 0x500: |
456 |
case 0x503: |
457 |
#ifdef DEBUG_BIOS
|
458 |
fprintf(stderr, "%c", val);
|
459 |
#endif
|
460 |
break;
|
461 |
} |
462 |
} |
463 |
|
464 |
extern uint64_t node_cpumask[MAX_NODES];
|
465 |
|
466 |
static void *bochs_bios_init(void) |
467 |
{ |
468 |
void *fw_cfg;
|
469 |
uint8_t *smbios_table; |
470 |
size_t smbios_len; |
471 |
uint64_t *numa_fw_cfg; |
472 |
int i, j;
|
473 |
|
474 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
475 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
476 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
477 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
478 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
479 |
|
480 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
481 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
482 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
483 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
484 |
|
485 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
486 |
|
487 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
488 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
489 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
490 |
acpi_tables_len); |
491 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
492 |
|
493 |
smbios_table = smbios_get_table(&smbios_len); |
494 |
if (smbios_table)
|
495 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
496 |
smbios_table, smbios_len); |
497 |
|
498 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
499 |
* of nodes, one word for each VCPU->node and one word for each node to
|
500 |
* hold the amount of memory.
|
501 |
*/
|
502 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
503 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
504 |
for (i = 0; i < smp_cpus; i++) { |
505 |
for (j = 0; j < nb_numa_nodes; j++) { |
506 |
if (node_cpumask[j] & (1 << i)) { |
507 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
508 |
break;
|
509 |
} |
510 |
} |
511 |
} |
512 |
for (i = 0; i < nb_numa_nodes; i++) { |
513 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
514 |
} |
515 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
516 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
517 |
|
518 |
return fw_cfg;
|
519 |
} |
520 |
|
521 |
/* Generate an initial boot sector which sets state and jump to
|
522 |
a specified vector */
|
523 |
static void generate_bootsect(target_phys_addr_t option_rom, |
524 |
uint32_t gpr[8], uint16_t segs[6], uint16_t ip) |
525 |
{ |
526 |
uint8_t rom[512], *p, *reloc;
|
527 |
uint8_t sum; |
528 |
int i;
|
529 |
|
530 |
memset(rom, 0, sizeof(rom)); |
531 |
|
532 |
p = rom; |
533 |
/* Make sure we have an option rom signature */
|
534 |
*p++ = 0x55;
|
535 |
*p++ = 0xaa;
|
536 |
|
537 |
/* ROM size in sectors*/
|
538 |
*p++ = 1;
|
539 |
|
540 |
/* Hook int19 */
|
541 |
|
542 |
*p++ = 0x50; /* push ax */ |
543 |
*p++ = 0x1e; /* push ds */ |
544 |
*p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */ |
545 |
*p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */ |
546 |
|
547 |
*p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */ |
548 |
*p++ = 0x64; *p++ = 0x00; |
549 |
reloc = p; |
550 |
*p++ = 0x00; *p++ = 0x00; |
551 |
|
552 |
*p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */ |
553 |
*p++ = 0x66; *p++ = 0x00; |
554 |
|
555 |
*p++ = 0x1f; /* pop ds */ |
556 |
*p++ = 0x58; /* pop ax */ |
557 |
*p++ = 0xcb; /* lret */ |
558 |
|
559 |
/* Actual code */
|
560 |
*reloc = (p - rom); |
561 |
|
562 |
*p++ = 0xfa; /* CLI */ |
563 |
*p++ = 0xfc; /* CLD */ |
564 |
|
565 |
for (i = 0; i < 6; i++) { |
566 |
if (i == 1) /* Skip CS */ |
567 |
continue;
|
568 |
|
569 |
*p++ = 0xb8; /* MOV AX,imm16 */ |
570 |
*p++ = segs[i]; |
571 |
*p++ = segs[i] >> 8;
|
572 |
*p++ = 0x8e; /* MOV <seg>,AX */ |
573 |
*p++ = 0xc0 + (i << 3); |
574 |
} |
575 |
|
576 |
for (i = 0; i < 8; i++) { |
577 |
*p++ = 0x66; /* 32-bit operand size */ |
578 |
*p++ = 0xb8 + i; /* MOV <reg>,imm32 */ |
579 |
*p++ = gpr[i]; |
580 |
*p++ = gpr[i] >> 8;
|
581 |
*p++ = gpr[i] >> 16;
|
582 |
*p++ = gpr[i] >> 24;
|
583 |
} |
584 |
|
585 |
*p++ = 0xea; /* JMP FAR */ |
586 |
*p++ = ip; /* IP */
|
587 |
*p++ = ip >> 8;
|
588 |
*p++ = segs[1]; /* CS */ |
589 |
*p++ = segs[1] >> 8; |
590 |
|
591 |
/* sign rom */
|
592 |
sum = 0;
|
593 |
for (i = 0; i < (sizeof(rom) - 1); i++) |
594 |
sum += rom[i]; |
595 |
rom[sizeof(rom) - 1] = -sum; |
596 |
|
597 |
cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
|
598 |
option_rom_setup_reset(option_rom, sizeof (rom));
|
599 |
} |
600 |
|
601 |
static long get_file_size(FILE *f) |
602 |
{ |
603 |
long where, size;
|
604 |
|
605 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
606 |
|
607 |
where = ftell(f); |
608 |
fseek(f, 0, SEEK_END);
|
609 |
size = ftell(f); |
610 |
fseek(f, where, SEEK_SET); |
611 |
|
612 |
return size;
|
613 |
} |
614 |
|
615 |
#define MULTIBOOT_STRUCT_ADDR 0x9000 |
616 |
|
617 |
#if MULTIBOOT_STRUCT_ADDR > 0xf0000 |
618 |
#error multiboot struct needs to fit in 16 bit real mode |
619 |
#endif
|
620 |
|
621 |
static int load_multiboot(void *fw_cfg, |
622 |
FILE *f, |
623 |
const char *kernel_filename, |
624 |
const char *initrd_filename, |
625 |
const char *kernel_cmdline, |
626 |
uint8_t *header) |
627 |
{ |
628 |
int i, t, is_multiboot = 0; |
629 |
uint32_t flags = 0;
|
630 |
uint32_t mh_entry_addr; |
631 |
uint32_t mh_load_addr; |
632 |
uint32_t mb_kernel_size; |
633 |
uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR; |
634 |
uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
|
635 |
uint32_t mb_cmdline = mb_bootinfo + 0x200;
|
636 |
uint32_t mb_mod_end; |
637 |
|
638 |
/* Ok, let's see if it is a multiboot image.
|
639 |
The header is 12x32bit long, so the latest entry may be 8192 - 48. */
|
640 |
for (i = 0; i < (8192 - 48); i += 4) { |
641 |
if (ldl_p(header+i) == 0x1BADB002) { |
642 |
uint32_t checksum = ldl_p(header+i+8);
|
643 |
flags = ldl_p(header+i+4);
|
644 |
checksum += flags; |
645 |
checksum += (uint32_t)0x1BADB002;
|
646 |
if (!checksum) {
|
647 |
is_multiboot = 1;
|
648 |
break;
|
649 |
} |
650 |
} |
651 |
} |
652 |
|
653 |
if (!is_multiboot)
|
654 |
return 0; /* no multiboot */ |
655 |
|
656 |
#ifdef DEBUG_MULTIBOOT
|
657 |
fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
|
658 |
#endif
|
659 |
|
660 |
if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */ |
661 |
fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
|
662 |
} |
663 |
if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */ |
664 |
uint64_t elf_entry; |
665 |
int kernel_size;
|
666 |
fclose(f); |
667 |
kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL); |
668 |
if (kernel_size < 0) { |
669 |
fprintf(stderr, "Error while loading elf kernel\n");
|
670 |
exit(1);
|
671 |
} |
672 |
mh_load_addr = mh_entry_addr = elf_entry; |
673 |
mb_kernel_size = kernel_size; |
674 |
|
675 |
#ifdef DEBUG_MULTIBOOT
|
676 |
fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
|
677 |
mb_kernel_size, (size_t)mh_entry_addr); |
678 |
#endif
|
679 |
} else {
|
680 |
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
|
681 |
uint32_t mh_header_addr = ldl_p(header+i+12);
|
682 |
mh_load_addr = ldl_p(header+i+16);
|
683 |
#ifdef DEBUG_MULTIBOOT
|
684 |
uint32_t mh_load_end_addr = ldl_p(header+i+20);
|
685 |
uint32_t mh_bss_end_addr = ldl_p(header+i+24);
|
686 |
#endif
|
687 |
uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr); |
688 |
|
689 |
mh_entry_addr = ldl_p(header+i+28);
|
690 |
mb_kernel_size = get_file_size(f) - mb_kernel_text_offset; |
691 |
|
692 |
/* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
|
693 |
uint32_t mh_mode_type = ldl_p(header+i+32);
|
694 |
uint32_t mh_width = ldl_p(header+i+36);
|
695 |
uint32_t mh_height = ldl_p(header+i+40);
|
696 |
uint32_t mh_depth = ldl_p(header+i+44); */
|
697 |
|
698 |
#ifdef DEBUG_MULTIBOOT
|
699 |
fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
|
700 |
fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
|
701 |
fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
|
702 |
fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
|
703 |
#endif
|
704 |
|
705 |
fseek(f, mb_kernel_text_offset, SEEK_SET); |
706 |
|
707 |
#ifdef DEBUG_MULTIBOOT
|
708 |
fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
|
709 |
mb_kernel_size, mh_load_addr); |
710 |
#endif
|
711 |
|
712 |
if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
|
713 |
fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
|
714 |
kernel_filename, mb_kernel_size); |
715 |
exit(1);
|
716 |
} |
717 |
fclose(f); |
718 |
} |
719 |
|
720 |
/* blob size is only the kernel for now */
|
721 |
mb_mod_end = mh_load_addr + mb_kernel_size; |
722 |
|
723 |
/* load modules */
|
724 |
stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */ |
725 |
if (initrd_filename) {
|
726 |
uint32_t mb_mod_info = mb_bootinfo + 0x100;
|
727 |
uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
|
728 |
uint32_t mb_mod_start = mh_load_addr; |
729 |
uint32_t mb_mod_length = mb_kernel_size; |
730 |
char *next_initrd;
|
731 |
char *next_space;
|
732 |
int mb_mod_count = 0; |
733 |
|
734 |
do {
|
735 |
next_initrd = strchr(initrd_filename, ',');
|
736 |
if (next_initrd)
|
737 |
*next_initrd = '\0';
|
738 |
/* if a space comes after the module filename, treat everything
|
739 |
after that as parameters */
|
740 |
cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename, |
741 |
strlen(initrd_filename) + 1);
|
742 |
stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */ |
743 |
mb_mod_cmdline += strlen(initrd_filename) + 1;
|
744 |
if ((next_space = strchr(initrd_filename, ' '))) |
745 |
*next_space = '\0';
|
746 |
#ifdef DEBUG_MULTIBOOT
|
747 |
printf("multiboot loading module: %s\n", initrd_filename);
|
748 |
#endif
|
749 |
f = fopen(initrd_filename, "rb");
|
750 |
if (f) {
|
751 |
mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
|
752 |
& (TARGET_PAGE_MASK); |
753 |
mb_mod_length = get_file_size(f); |
754 |
mb_mod_end = mb_mod_start + mb_mod_length; |
755 |
|
756 |
if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
|
757 |
fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
|
758 |
initrd_filename, mb_mod_length); |
759 |
exit(1);
|
760 |
} |
761 |
|
762 |
mb_mod_count++; |
763 |
stl_phys(mb_mod_info + 0, mb_mod_start);
|
764 |
stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
|
765 |
#ifdef DEBUG_MULTIBOOT
|
766 |
printf("mod_start: %#x\nmod_end: %#x\n", mb_mod_start,
|
767 |
mb_mod_start + mb_mod_length); |
768 |
#endif
|
769 |
stl_phys(mb_mod_info + 12, 0x0); /* reserved */ |
770 |
} |
771 |
initrd_filename = next_initrd+1;
|
772 |
mb_mod_info += 16;
|
773 |
} while (next_initrd);
|
774 |
stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */ |
775 |
stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */ |
776 |
} |
777 |
|
778 |
/* Make sure we're getting kernel + modules back after reset */
|
779 |
option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr); |
780 |
|
781 |
/* Commandline support */
|
782 |
stl_phys(mb_bootinfo + 16, mb_cmdline);
|
783 |
t = strlen(kernel_filename); |
784 |
cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t); |
785 |
mb_cmdline += t; |
786 |
stb_phys(mb_cmdline++, ' ');
|
787 |
t = strlen(kernel_cmdline) + 1;
|
788 |
cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t); |
789 |
|
790 |
/* the kernel is where we want it to be now */
|
791 |
|
792 |
#define MULTIBOOT_FLAGS_MEMORY (1 << 0) |
793 |
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1) |
794 |
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2) |
795 |
#define MULTIBOOT_FLAGS_MODULES (1 << 3) |
796 |
#define MULTIBOOT_FLAGS_MMAP (1 << 6) |
797 |
stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY |
798 |
| MULTIBOOT_FLAGS_BOOT_DEVICE |
799 |
| MULTIBOOT_FLAGS_CMDLINE |
800 |
| MULTIBOOT_FLAGS_MODULES |
801 |
| MULTIBOOT_FLAGS_MMAP); |
802 |
stl_phys(mb_bootinfo + 4, 640); /* mem_lower */ |
803 |
stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */ |
804 |
stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */ |
805 |
stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */ |
806 |
|
807 |
#ifdef DEBUG_MULTIBOOT
|
808 |
fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
|
809 |
#endif
|
810 |
|
811 |
/* Pass variables to option rom */
|
812 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr); |
813 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo); |
814 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr); |
815 |
|
816 |
/* Make sure we're getting the config space back after reset */
|
817 |
option_rom_setup_reset(mb_bootinfo, 0x500);
|
818 |
|
819 |
option_rom[nb_option_roms] = "multiboot.bin";
|
820 |
nb_option_roms++; |
821 |
|
822 |
return 1; /* yes, we are multiboot */ |
823 |
} |
824 |
|
825 |
static void load_linux(void *fw_cfg, |
826 |
target_phys_addr_t option_rom, |
827 |
const char *kernel_filename, |
828 |
const char *initrd_filename, |
829 |
const char *kernel_cmdline, |
830 |
target_phys_addr_t max_ram_size) |
831 |
{ |
832 |
uint16_t protocol; |
833 |
uint32_t gpr[8];
|
834 |
uint16_t seg[6];
|
835 |
uint16_t real_seg; |
836 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
837 |
uint32_t initrd_max; |
838 |
uint8_t header[8192];
|
839 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
840 |
FILE *f, *fi; |
841 |
char *vmode;
|
842 |
|
843 |
/* Align to 16 bytes as a paranoia measure */
|
844 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
845 |
|
846 |
/* load the kernel header */
|
847 |
f = fopen(kernel_filename, "rb");
|
848 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
849 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
850 |
MIN(ARRAY_SIZE(header), kernel_size)) { |
851 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
852 |
kernel_filename); |
853 |
exit(1);
|
854 |
} |
855 |
|
856 |
/* kernel protocol version */
|
857 |
#if 0
|
858 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
859 |
#endif
|
860 |
if (ldl_p(header+0x202) == 0x53726448) |
861 |
protocol = lduw_p(header+0x206);
|
862 |
else {
|
863 |
/* This looks like a multiboot kernel. If it is, let's stop
|
864 |
treating it like a Linux kernel. */
|
865 |
if (load_multiboot(fw_cfg, f, kernel_filename,
|
866 |
initrd_filename, kernel_cmdline, header)) |
867 |
return;
|
868 |
protocol = 0;
|
869 |
} |
870 |
|
871 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
872 |
/* Low kernel */
|
873 |
real_addr = 0x90000;
|
874 |
cmdline_addr = 0x9a000 - cmdline_size;
|
875 |
prot_addr = 0x10000;
|
876 |
} else if (protocol < 0x202) { |
877 |
/* High but ancient kernel */
|
878 |
real_addr = 0x90000;
|
879 |
cmdline_addr = 0x9a000 - cmdline_size;
|
880 |
prot_addr = 0x100000;
|
881 |
} else {
|
882 |
/* High and recent kernel */
|
883 |
real_addr = 0x10000;
|
884 |
cmdline_addr = 0x20000;
|
885 |
prot_addr = 0x100000;
|
886 |
} |
887 |
|
888 |
#if 0
|
889 |
fprintf(stderr,
|
890 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
891 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
892 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
893 |
real_addr,
|
894 |
cmdline_addr,
|
895 |
prot_addr);
|
896 |
#endif
|
897 |
|
898 |
/* highest address for loading the initrd */
|
899 |
if (protocol >= 0x203) |
900 |
initrd_max = ldl_p(header+0x22c);
|
901 |
else
|
902 |
initrd_max = 0x37ffffff;
|
903 |
|
904 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
905 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
906 |
|
907 |
/* kernel command line */
|
908 |
pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
|
909 |
|
910 |
if (protocol >= 0x202) { |
911 |
stl_p(header+0x228, cmdline_addr);
|
912 |
} else {
|
913 |
stw_p(header+0x20, 0xA33F); |
914 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
915 |
} |
916 |
|
917 |
/* handle vga= parameter */
|
918 |
vmode = strstr(kernel_cmdline, "vga=");
|
919 |
if (vmode) {
|
920 |
unsigned int video_mode; |
921 |
/* skip "vga=" */
|
922 |
vmode += 4;
|
923 |
if (!strncmp(vmode, "normal", 6)) { |
924 |
video_mode = 0xffff;
|
925 |
} else if (!strncmp(vmode, "ext", 3)) { |
926 |
video_mode = 0xfffe;
|
927 |
} else if (!strncmp(vmode, "ask", 3)) { |
928 |
video_mode = 0xfffd;
|
929 |
} else {
|
930 |
video_mode = strtol(vmode, NULL, 0); |
931 |
} |
932 |
stw_p(header+0x1fa, video_mode);
|
933 |
} |
934 |
|
935 |
/* loader type */
|
936 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
937 |
If this code is substantially changed, you may want to consider
|
938 |
incrementing the revision. */
|
939 |
if (protocol >= 0x200) |
940 |
header[0x210] = 0xB0; |
941 |
|
942 |
/* heap */
|
943 |
if (protocol >= 0x201) { |
944 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
945 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
946 |
} |
947 |
|
948 |
/* load initrd */
|
949 |
if (initrd_filename) {
|
950 |
if (protocol < 0x200) { |
951 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
952 |
exit(1);
|
953 |
} |
954 |
|
955 |
fi = fopen(initrd_filename, "rb");
|
956 |
if (!fi) {
|
957 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
958 |
initrd_filename); |
959 |
exit(1);
|
960 |
} |
961 |
|
962 |
initrd_size = get_file_size(fi); |
963 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
964 |
|
965 |
if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
|
966 |
fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
|
967 |
initrd_filename); |
968 |
exit(1);
|
969 |
} |
970 |
fclose(fi); |
971 |
|
972 |
stl_p(header+0x218, initrd_addr);
|
973 |
stl_p(header+0x21c, initrd_size);
|
974 |
} |
975 |
|
976 |
/* store the finalized header and load the rest of the kernel */
|
977 |
cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header)); |
978 |
|
979 |
setup_size = header[0x1f1];
|
980 |
if (setup_size == 0) |
981 |
setup_size = 4;
|
982 |
|
983 |
setup_size = (setup_size+1)*512; |
984 |
/* Size of protected-mode code */
|
985 |
kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header); |
986 |
|
987 |
/* In case we have read too much already, copy that over */
|
988 |
if (setup_size < ARRAY_SIZE(header)) {
|
989 |
cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size); |
990 |
prot_addr += (ARRAY_SIZE(header) - setup_size); |
991 |
setup_size = ARRAY_SIZE(header); |
992 |
} |
993 |
|
994 |
if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
|
995 |
setup_size - ARRAY_SIZE(header), f) || |
996 |
!fread_targphys_ok(prot_addr, kernel_size, f)) { |
997 |
fprintf(stderr, "qemu: read error on kernel '%s'\n",
|
998 |
kernel_filename); |
999 |
exit(1);
|
1000 |
} |
1001 |
fclose(f); |
1002 |
|
1003 |
/* generate bootsector to set up the initial register state */
|
1004 |
real_seg = real_addr >> 4;
|
1005 |
seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg; |
1006 |
seg[1] = real_seg+0x20; /* CS */ |
1007 |
memset(gpr, 0, sizeof gpr); |
1008 |
gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */ |
1009 |
|
1010 |
option_rom_setup_reset(real_addr, setup_size); |
1011 |
option_rom_setup_reset(prot_addr, kernel_size); |
1012 |
option_rom_setup_reset(cmdline_addr, cmdline_size); |
1013 |
if (initrd_filename)
|
1014 |
option_rom_setup_reset(initrd_addr, initrd_size); |
1015 |
|
1016 |
generate_bootsect(option_rom, gpr, seg, 0);
|
1017 |
} |
1018 |
|
1019 |
static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
1020 |
static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
1021 |
static const int ide_irq[2] = { 14, 15 }; |
1022 |
|
1023 |
#define NE2000_NB_MAX 6 |
1024 |
|
1025 |
static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
1026 |
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
1027 |
|
1028 |
static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
1029 |
static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
1030 |
|
1031 |
static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
1032 |
static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
1033 |
|
1034 |
#ifdef HAS_AUDIO
|
1035 |
static void audio_init (PCIBus *pci_bus, qemu_irq *pic) |
1036 |
{ |
1037 |
struct soundhw *c;
|
1038 |
|
1039 |
for (c = soundhw; c->name; ++c) {
|
1040 |
if (c->enabled) {
|
1041 |
if (c->isa) {
|
1042 |
c->init.init_isa(pic); |
1043 |
} else {
|
1044 |
if (pci_bus) {
|
1045 |
c->init.init_pci(pci_bus); |
1046 |
} |
1047 |
} |
1048 |
} |
1049 |
} |
1050 |
} |
1051 |
#endif
|
1052 |
|
1053 |
static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic) |
1054 |
{ |
1055 |
static int nb_ne2k = 0; |
1056 |
|
1057 |
if (nb_ne2k == NE2000_NB_MAX)
|
1058 |
return;
|
1059 |
isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd); |
1060 |
nb_ne2k++; |
1061 |
} |
1062 |
|
1063 |
static int load_option_rom(const char *oprom, target_phys_addr_t start, |
1064 |
target_phys_addr_t end) |
1065 |
{ |
1066 |
int size;
|
1067 |
char *filename;
|
1068 |
|
1069 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom); |
1070 |
if (filename) {
|
1071 |
size = get_image_size(filename); |
1072 |
if (size > 0 && start + size > end) { |
1073 |
fprintf(stderr, "Not enough space to load option rom '%s'\n",
|
1074 |
oprom); |
1075 |
exit(1);
|
1076 |
} |
1077 |
size = load_image_targphys(filename, start, end - start); |
1078 |
qemu_free(filename); |
1079 |
} else {
|
1080 |
size = -1;
|
1081 |
} |
1082 |
if (size < 0) { |
1083 |
fprintf(stderr, "Could not load option rom '%s'\n", oprom);
|
1084 |
exit(1);
|
1085 |
} |
1086 |
/* Round up optiom rom size to the next 2k boundary */
|
1087 |
size = (size + 2047) & ~2047; |
1088 |
option_rom_setup_reset(start, size); |
1089 |
return size;
|
1090 |
} |
1091 |
|
1092 |
int cpu_is_bsp(CPUState *env)
|
1093 |
{ |
1094 |
return env->cpuid_apic_id == 0; |
1095 |
} |
1096 |
|
1097 |
static CPUState *pc_new_cpu(const char *cpu_model) |
1098 |
{ |
1099 |
CPUState *env; |
1100 |
|
1101 |
env = cpu_init(cpu_model); |
1102 |
if (!env) {
|
1103 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
1104 |
exit(1);
|
1105 |
} |
1106 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
1107 |
env->cpuid_apic_id = env->cpu_index; |
1108 |
/* APIC reset callback resets cpu */
|
1109 |
apic_init(env); |
1110 |
} else {
|
1111 |
qemu_register_reset((QEMUResetHandler*)cpu_reset, env); |
1112 |
} |
1113 |
return env;
|
1114 |
} |
1115 |
|
1116 |
/* PC hardware initialisation */
|
1117 |
static void pc_init1(ram_addr_t ram_size, |
1118 |
const char *boot_device, |
1119 |
const char *kernel_filename, |
1120 |
const char *kernel_cmdline, |
1121 |
const char *initrd_filename, |
1122 |
const char *cpu_model, |
1123 |
int pci_enabled)
|
1124 |
{ |
1125 |
char *filename;
|
1126 |
int ret, linux_boot, i;
|
1127 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
1128 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
1129 |
int bios_size, isa_bios_size, oprom_area_size;
|
1130 |
PCIBus *pci_bus; |
1131 |
PCIDevice *pci_dev; |
1132 |
ISADevice *isa_dev; |
1133 |
int piix3_devfn = -1; |
1134 |
CPUState *env; |
1135 |
qemu_irq *cpu_irq; |
1136 |
qemu_irq *isa_irq; |
1137 |
qemu_irq *i8259; |
1138 |
IsaIrqState *isa_irq_state; |
1139 |
DriveInfo *dinfo; |
1140 |
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
1141 |
BlockDriverState *fd[MAX_FD]; |
1142 |
int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
|
1143 |
void *fw_cfg;
|
1144 |
|
1145 |
if (ram_size >= 0xe0000000 ) { |
1146 |
above_4g_mem_size = ram_size - 0xe0000000;
|
1147 |
below_4g_mem_size = 0xe0000000;
|
1148 |
} else {
|
1149 |
below_4g_mem_size = ram_size; |
1150 |
} |
1151 |
|
1152 |
linux_boot = (kernel_filename != NULL);
|
1153 |
|
1154 |
/* init CPUs */
|
1155 |
if (cpu_model == NULL) { |
1156 |
#ifdef TARGET_X86_64
|
1157 |
cpu_model = "qemu64";
|
1158 |
#else
|
1159 |
cpu_model = "qemu32";
|
1160 |
#endif
|
1161 |
} |
1162 |
|
1163 |
for (i = 0; i < smp_cpus; i++) { |
1164 |
env = pc_new_cpu(cpu_model); |
1165 |
} |
1166 |
|
1167 |
vmport_init(); |
1168 |
|
1169 |
/* allocate RAM */
|
1170 |
ram_addr = qemu_ram_alloc(0xa0000);
|
1171 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
1172 |
|
1173 |
/* Allocate, even though we won't register, so we don't break the
|
1174 |
* phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
|
1175 |
* and some bios areas, which will be registered later
|
1176 |
*/
|
1177 |
ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); |
1178 |
ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
|
1179 |
cpu_register_physical_memory(0x100000,
|
1180 |
below_4g_mem_size - 0x100000,
|
1181 |
ram_addr); |
1182 |
|
1183 |
/* above 4giga memory allocation */
|
1184 |
if (above_4g_mem_size > 0) { |
1185 |
#if TARGET_PHYS_ADDR_BITS == 32 |
1186 |
hw_error("To much RAM for 32-bit physical address");
|
1187 |
#else
|
1188 |
ram_addr = qemu_ram_alloc(above_4g_mem_size); |
1189 |
cpu_register_physical_memory(0x100000000ULL,
|
1190 |
above_4g_mem_size, |
1191 |
ram_addr); |
1192 |
#endif
|
1193 |
} |
1194 |
|
1195 |
|
1196 |
/* BIOS load */
|
1197 |
if (bios_name == NULL) |
1198 |
bios_name = BIOS_FILENAME; |
1199 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
1200 |
if (filename) {
|
1201 |
bios_size = get_image_size(filename); |
1202 |
} else {
|
1203 |
bios_size = -1;
|
1204 |
} |
1205 |
if (bios_size <= 0 || |
1206 |
(bios_size % 65536) != 0) { |
1207 |
goto bios_error;
|
1208 |
} |
1209 |
bios_offset = qemu_ram_alloc(bios_size); |
1210 |
ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); |
1211 |
if (ret != bios_size) {
|
1212 |
bios_error:
|
1213 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
1214 |
exit(1);
|
1215 |
} |
1216 |
if (filename) {
|
1217 |
qemu_free(filename); |
1218 |
} |
1219 |
/* map the last 128KB of the BIOS in ISA space */
|
1220 |
isa_bios_size = bios_size; |
1221 |
if (isa_bios_size > (128 * 1024)) |
1222 |
isa_bios_size = 128 * 1024; |
1223 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
1224 |
isa_bios_size, |
1225 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
1226 |
|
1227 |
|
1228 |
|
1229 |
option_rom_offset = qemu_ram_alloc(0x20000);
|
1230 |
oprom_area_size = 0;
|
1231 |
cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); |
1232 |
|
1233 |
if (using_vga) {
|
1234 |
const char *vgabios_filename; |
1235 |
/* VGA BIOS load */
|
1236 |
if (cirrus_vga_enabled) {
|
1237 |
vgabios_filename = VGABIOS_CIRRUS_FILENAME; |
1238 |
} else {
|
1239 |
vgabios_filename = VGABIOS_FILENAME; |
1240 |
} |
1241 |
oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000); |
1242 |
} |
1243 |
/* Although video roms can grow larger than 0x8000, the area between
|
1244 |
* 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
|
1245 |
* for any other kind of option rom inside this area */
|
1246 |
if (oprom_area_size < 0x8000) |
1247 |
oprom_area_size = 0x8000;
|
1248 |
|
1249 |
/* map all the bios at the top of memory */
|
1250 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
1251 |
bios_size, bios_offset | IO_MEM_ROM); |
1252 |
|
1253 |
fw_cfg = bochs_bios_init(); |
1254 |
|
1255 |
if (linux_boot) {
|
1256 |
load_linux(fw_cfg, 0xc0000 + oprom_area_size,
|
1257 |
kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
1258 |
oprom_area_size += 2048;
|
1259 |
} |
1260 |
|
1261 |
for (i = 0; i < nb_option_roms; i++) { |
1262 |
oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
|
1263 |
0xe0000);
|
1264 |
} |
1265 |
|
1266 |
for (i = 0; i < nb_nics; i++) { |
1267 |
char nic_oprom[1024]; |
1268 |
const char *model = nd_table[i].model; |
1269 |
|
1270 |
if (!nd_table[i].bootable)
|
1271 |
continue;
|
1272 |
|
1273 |
if (model == NULL) |
1274 |
model = "ne2k_pci";
|
1275 |
snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model); |
1276 |
|
1277 |
oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
|
1278 |
0xe0000);
|
1279 |
} |
1280 |
|
1281 |
cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); |
1282 |
i8259 = i8259_init(cpu_irq[0]);
|
1283 |
isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
|
1284 |
isa_irq_state->i8259 = i8259; |
1285 |
isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 16);
|
1286 |
ferr_irq = isa_irq[13];
|
1287 |
|
1288 |
if (pci_enabled) {
|
1289 |
pci_bus = i440fx_init(&i440fx_state, isa_irq); |
1290 |
piix3_devfn = piix3_init(pci_bus, -1);
|
1291 |
} else {
|
1292 |
pci_bus = NULL;
|
1293 |
} |
1294 |
|
1295 |
/* init basic PC hardware */
|
1296 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
1297 |
|
1298 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
1299 |
|
1300 |
if (cirrus_vga_enabled) {
|
1301 |
if (pci_enabled) {
|
1302 |
pci_cirrus_vga_init(pci_bus); |
1303 |
} else {
|
1304 |
isa_cirrus_vga_init(); |
1305 |
} |
1306 |
} else if (vmsvga_enabled) { |
1307 |
if (pci_enabled)
|
1308 |
pci_vmsvga_init(pci_bus); |
1309 |
else
|
1310 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
1311 |
} else if (std_vga_enabled) { |
1312 |
if (pci_enabled) {
|
1313 |
pci_vga_init(pci_bus, 0, 0); |
1314 |
} else {
|
1315 |
isa_vga_init(); |
1316 |
} |
1317 |
} |
1318 |
|
1319 |
rtc_state = rtc_init(0x70, isa_irq[8], 2000); |
1320 |
|
1321 |
qemu_register_boot_set(pc_boot_set, rtc_state); |
1322 |
|
1323 |
register_ioport_read(0x92, 1, 1, ioport92_read, NULL); |
1324 |
register_ioport_write(0x92, 1, 1, ioport92_write, NULL); |
1325 |
|
1326 |
if (pci_enabled) {
|
1327 |
ioapic = ioapic_init(); |
1328 |
} |
1329 |
pit = pit_init(0x40, isa_irq[0]); |
1330 |
pcspk_init(pit); |
1331 |
if (!no_hpet) {
|
1332 |
hpet_init(isa_irq); |
1333 |
} |
1334 |
if (pci_enabled) {
|
1335 |
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); |
1336 |
} |
1337 |
|
1338 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1339 |
if (serial_hds[i]) {
|
1340 |
serial_init(serial_io[i], isa_irq[serial_irq[i]], 115200,
|
1341 |
serial_hds[i]); |
1342 |
} |
1343 |
} |
1344 |
|
1345 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1346 |
if (parallel_hds[i]) {
|
1347 |
parallel_init(parallel_io[i], isa_irq[parallel_irq[i]], |
1348 |
parallel_hds[i]); |
1349 |
} |
1350 |
} |
1351 |
|
1352 |
watchdog_pc_init(pci_bus); |
1353 |
|
1354 |
for(i = 0; i < nb_nics; i++) { |
1355 |
NICInfo *nd = &nd_table[i]; |
1356 |
|
1357 |
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) |
1358 |
pc_init_ne2k_isa(nd, isa_irq); |
1359 |
else
|
1360 |
pci_nic_init(nd, "ne2k_pci", NULL); |
1361 |
} |
1362 |
|
1363 |
piix4_acpi_system_hot_add_init(); |
1364 |
|
1365 |
if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
1366 |
fprintf(stderr, "qemu: too many IDE bus\n");
|
1367 |
exit(1);
|
1368 |
} |
1369 |
|
1370 |
for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
1371 |
dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
1372 |
hd[i] = dinfo ? dinfo->bdrv : NULL;
|
1373 |
} |
1374 |
|
1375 |
if (pci_enabled) {
|
1376 |
pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, isa_irq);
|
1377 |
} else {
|
1378 |
for(i = 0; i < MAX_IDE_BUS; i++) { |
1379 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], isa_irq[ide_irq[i]], |
1380 |
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
|
1381 |
} |
1382 |
} |
1383 |
|
1384 |
isa_dev = isa_create_simple("i8042", 0x60, 0x64); |
1385 |
isa_connect_irq(isa_dev, 0, isa_irq[1]); |
1386 |
isa_connect_irq(isa_dev, 1, isa_irq[12]); |
1387 |
DMA_init(0);
|
1388 |
#ifdef HAS_AUDIO
|
1389 |
audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
|
1390 |
#endif
|
1391 |
|
1392 |
for(i = 0; i < MAX_FD; i++) { |
1393 |
dinfo = drive_get(IF_FLOPPY, 0, i);
|
1394 |
fd[i] = dinfo ? dinfo->bdrv : NULL;
|
1395 |
} |
1396 |
floppy_controller = fdctrl_init(isa_irq[6], 2, 0, 0x3f0, fd); |
1397 |
|
1398 |
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); |
1399 |
|
1400 |
if (pci_enabled && usb_enabled) {
|
1401 |
usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
|
1402 |
} |
1403 |
|
1404 |
if (pci_enabled && acpi_enabled) {
|
1405 |
uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ |
1406 |
i2c_bus *smbus; |
1407 |
|
1408 |
/* TODO: Populate SPD eeprom data. */
|
1409 |
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, isa_irq[9]); |
1410 |
for (i = 0; i < 8; i++) { |
1411 |
DeviceState *eeprom; |
1412 |
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
|
1413 |
qdev_prop_set_uint32(eeprom, "address", 0x50 + i); |
1414 |
qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256)); |
1415 |
qdev_init(eeprom); |
1416 |
} |
1417 |
} |
1418 |
|
1419 |
if (i440fx_state) {
|
1420 |
i440fx_init_memory_mappings(i440fx_state); |
1421 |
} |
1422 |
|
1423 |
if (pci_enabled) {
|
1424 |
int max_bus;
|
1425 |
int bus;
|
1426 |
|
1427 |
max_bus = drive_get_max_bus(IF_SCSI); |
1428 |
for (bus = 0; bus <= max_bus; bus++) { |
1429 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1430 |
} |
1431 |
} |
1432 |
|
1433 |
/* Add virtio balloon device */
|
1434 |
if (pci_enabled && virtio_balloon) {
|
1435 |
pci_dev = pci_create("virtio-balloon-pci", virtio_balloon_devaddr);
|
1436 |
qdev_init(&pci_dev->qdev); |
1437 |
} |
1438 |
|
1439 |
/* Add virtio console devices */
|
1440 |
if (pci_enabled) {
|
1441 |
for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { |
1442 |
if (virtcon_hds[i]) {
|
1443 |
pci_create_simple(pci_bus, -1, "virtio-console-pci"); |
1444 |
} |
1445 |
} |
1446 |
} |
1447 |
} |
1448 |
|
1449 |
static void pc_init_pci(ram_addr_t ram_size, |
1450 |
const char *boot_device, |
1451 |
const char *kernel_filename, |
1452 |
const char *kernel_cmdline, |
1453 |
const char *initrd_filename, |
1454 |
const char *cpu_model) |
1455 |
{ |
1456 |
pc_init1(ram_size, boot_device, |
1457 |
kernel_filename, kernel_cmdline, |
1458 |
initrd_filename, cpu_model, 1);
|
1459 |
} |
1460 |
|
1461 |
static void pc_init_isa(ram_addr_t ram_size, |
1462 |
const char *boot_device, |
1463 |
const char *kernel_filename, |
1464 |
const char *kernel_cmdline, |
1465 |
const char *initrd_filename, |
1466 |
const char *cpu_model) |
1467 |
{ |
1468 |
pc_init1(ram_size, boot_device, |
1469 |
kernel_filename, kernel_cmdline, |
1470 |
initrd_filename, cpu_model, 0);
|
1471 |
} |
1472 |
|
1473 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
1474 |
BIOS will read it and start S3 resume at POST Entry */
|
1475 |
void cmos_set_s3_resume(void) |
1476 |
{ |
1477 |
if (rtc_state)
|
1478 |
rtc_set_memory(rtc_state, 0xF, 0xFE); |
1479 |
} |
1480 |
|
1481 |
static QEMUMachine pc_machine = {
|
1482 |
.name = "pc-0.11",
|
1483 |
.alias = "pc",
|
1484 |
.desc = "Standard PC",
|
1485 |
.init = pc_init_pci, |
1486 |
.max_cpus = 255,
|
1487 |
.is_default = 1,
|
1488 |
}; |
1489 |
|
1490 |
static QEMUMachine pc_machine_v0_10 = {
|
1491 |
.name = "pc-0.10",
|
1492 |
.desc = "Standard PC, qemu 0.10",
|
1493 |
.init = pc_init_pci, |
1494 |
.max_cpus = 255,
|
1495 |
.compat_props = (CompatProperty[]) { |
1496 |
{ |
1497 |
.driver = "virtio-blk-pci",
|
1498 |
.property = "class",
|
1499 |
.value = stringify(PCI_CLASS_STORAGE_OTHER), |
1500 |
},{ |
1501 |
.driver = "virtio-console-pci",
|
1502 |
.property = "class",
|
1503 |
.value = stringify(PCI_CLASS_DISPLAY_OTHER), |
1504 |
},{ |
1505 |
.driver = "virtio-net-pci",
|
1506 |
.property = "vectors",
|
1507 |
.value = stringify(0),
|
1508 |
}, |
1509 |
{ /* end of list */ }
|
1510 |
}, |
1511 |
}; |
1512 |
|
1513 |
static QEMUMachine isapc_machine = {
|
1514 |
.name = "isapc",
|
1515 |
.desc = "ISA-only PC",
|
1516 |
.init = pc_init_isa, |
1517 |
.max_cpus = 1,
|
1518 |
}; |
1519 |
|
1520 |
static void pc_machine_init(void) |
1521 |
{ |
1522 |
qemu_register_machine(&pc_machine); |
1523 |
qemu_register_machine(&pc_machine_v0_10); |
1524 |
qemu_register_machine(&isapc_machine); |
1525 |
} |
1526 |
|
1527 |
machine_init(pc_machine_init); |