Archipelago » qemu

/*

 * Intel XScale PXA255/270 processor support.

 *

 * Copyright (c) 2006 Openedhand Ltd.

 * Written by Andrzej Zaborowski <balrog@zabor.org>

 *

 * This code is licensed under the GPL.

 */

#include "sysbus.h"

#include "pxa.h"

#include "sysemu.h"

#include "pc.h"

#include "i2c.h"

#include "ssi.h"

#include "qemu-char.h"

#include "blockdev.h"

static struct {

    target_phys_addr_t io_base;

    int irqn;

} pxa255_serial[] = {

    { 0x40100000, PXA2XX_PIC_FFUART },

    { 0x40200000, PXA2XX_PIC_BTUART },

    { 0x40700000, PXA2XX_PIC_STUART },

    { 0x41600000, PXA25X_PIC_HWUART },

    { 0, 0 }

}, pxa270_serial[] = {

    { 0x40100000, PXA2XX_PIC_FFUART },

    { 0x40200000, PXA2XX_PIC_BTUART },

    { 0x40700000, PXA2XX_PIC_STUART },

    { 0, 0 }

};

typedef struct PXASSPDef {

    target_phys_addr_t io_base;

    int irqn;

} PXASSPDef;

#if 0

static PXASSPDef pxa250_ssp[] = {

    { 0x41000000, PXA2XX_PIC_SSP },

    { 0, 0 }

};

#endif

static PXASSPDef pxa255_ssp[] = {

    { 0x41000000, PXA2XX_PIC_SSP },

    { 0x41400000, PXA25X_PIC_NSSP },

    { 0, 0 }

};

#if 0

static PXASSPDef pxa26x_ssp[] = {

    { 0x41000000, PXA2XX_PIC_SSP },

    { 0x41400000, PXA25X_PIC_NSSP },

    { 0x41500000, PXA26X_PIC_ASSP },

    { 0, 0 }

};

#endif

static PXASSPDef pxa27x_ssp[] = {

    { 0x41000000, PXA2XX_PIC_SSP },

    { 0x41700000, PXA27X_PIC_SSP2 },

    { 0x41900000, PXA2XX_PIC_SSP3 },

    { 0, 0 }

};

#define PMCR        0x00        /* Power Manager Control register */

#define PSSR        0x04        /* Power Manager Sleep Status register */

#define PSPR        0x08        /* Power Manager Scratch-Pad register */

#define PWER        0x0c        /* Power Manager Wake-Up Enable register */

#define PRER        0x10        /* Power Manager Rising-Edge Detect Enable register */

#define PFER        0x14        /* Power Manager Falling-Edge Detect Enable register */

#define PEDR        0x18        /* Power Manager Edge-Detect Status register */

#define PCFR        0x1c        /* Power Manager General Configuration register */

#define PGSR0        0x20        /* Power Manager GPIO Sleep-State register 0 */

#define PGSR1        0x24        /* Power Manager GPIO Sleep-State register 1 */

#define PGSR2        0x28        /* Power Manager GPIO Sleep-State register 2 */

#define PGSR3        0x2c        /* Power Manager GPIO Sleep-State register 3 */

#define RCSR        0x30        /* Reset Controller Status register */

#define PSLR        0x34        /* Power Manager Sleep Configuration register */

#define PTSR        0x38        /* Power Manager Standby Configuration register */

#define PVCR        0x40        /* Power Manager Voltage Change Control register */

#define PUCR        0x4c        /* Power Manager USIM Card Control/Status register */

#define PKWR        0x50        /* Power Manager Keyboard Wake-Up Enable register */

#define PKSR        0x54        /* Power Manager Keyboard Level-Detect Status */

#define PCMD0        0x80        /* Power Manager I2C Command register File 0 */

#define PCMD31        0xfc        /* Power Manager I2C Command register File 31 */

static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (addr) {

    case PMCR ... PCMD31:

        if (addr & 3)

            goto fail;

        return s->pm_regs[addr >> 2];

    default:

    fail:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

    return 0;

}

static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (addr) {

    case PMCR:

        s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);

        s->pm_regs[addr >> 2] |= value & 0x15;

        break;

    case PSSR:        /* Read-clean registers */

    case RCSR:

    case PKSR:

        s->pm_regs[addr >> 2] &= ~value;

        break;

    default:        /* Read-write registers */

        if (!(addr & 3)) {

            s->pm_regs[addr >> 2] = value;

            break;

        }

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

}

static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {

    pxa2xx_pm_read,

    pxa2xx_pm_read,

    pxa2xx_pm_read,

};

static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {

    pxa2xx_pm_write,

    pxa2xx_pm_write,

    pxa2xx_pm_write,

};

static const VMStateDescription vmstate_pxa2xx_pm = {

    .name = "pxa2xx_pm",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),

        VMSTATE_END_OF_LIST()

    }

};

#define CCCR        0x00        /* Core Clock Configuration register */

#define CKEN        0x04        /* Clock Enable register */

#define OSCC        0x08        /* Oscillator Configuration register */

#define CCSR        0x0c        /* Core Clock Status register */

static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (addr) {

    case CCCR:

    case CKEN:

    case OSCC:

        return s->cm_regs[addr >> 2];

    case CCSR:

        return s->cm_regs[CCCR >> 2] | (3 << 28);

    default:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

    return 0;

}

static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (addr) {

    case CCCR:

    case CKEN:

        s->cm_regs[addr >> 2] = value;

        break;

    case OSCC:

        s->cm_regs[addr >> 2] &= ~0x6c;

        s->cm_regs[addr >> 2] |= value & 0x6e;

        if ((value >> 1) & 1)                        /* OON */

            s->cm_regs[addr >> 2] |= 1 << 0;        /* Oscillator is now stable */

        break;

    default:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

}

static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {

    pxa2xx_cm_read,

    pxa2xx_cm_read,

    pxa2xx_cm_read,

};

static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {

    pxa2xx_cm_write,

    pxa2xx_cm_write,

    pxa2xx_cm_write,

};

static const VMStateDescription vmstate_pxa2xx_cm = {

    .name = "pxa2xx_cm",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),

        VMSTATE_UINT32(clkcfg, PXA2xxState),

        VMSTATE_UINT32(pmnc, PXA2xxState),

        VMSTATE_END_OF_LIST()

    }

};

static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (reg) {

    case 6:        /* Clock Configuration register */

        return s->clkcfg;

    case 7:        /* Power Mode register */

        return 0;

    default:

        printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

        break;

    }

    return 0;

}

static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,

                uint32_t value)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    static const char *pwrmode[8] = {

        "Normal", "Idle", "Deep-idle", "Standby",

        "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",

    };

    switch (reg) {

    case 6:        /* Clock Configuration register */

        s->clkcfg = value & 0xf;

        if (value & 2)

            printf("%s: CPU frequency change attempt\n", __FUNCTION__);

        break;

    case 7:        /* Power Mode register */

        if (value & 8)

            printf("%s: CPU voltage change attempt\n", __FUNCTION__);

        switch (value & 7) {

        case 0:

            /* Do nothing */

            break;

        case 1:

            /* Idle */

            if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) {        /* CPDIS */

                cpu_interrupt(s->env, CPU_INTERRUPT_HALT);

                break;

            }

            /* Fall through.  */

        case 2:

            /* Deep-Idle */

            cpu_interrupt(s->env, CPU_INTERRUPT_HALT);

            s->pm_regs[RCSR >> 2] |= 0x8;        /* Set GPR */

            goto message;

        case 3:

            s->env->uncached_cpsr =

                    ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;

            s->env->cp15.c1_sys = 0;

            s->env->cp15.c1_coproc = 0;

            s->env->cp15.c2_base0 = 0;

            s->env->cp15.c3 = 0;

            s->pm_regs[PSSR >> 2] |= 0x8;        /* Set STS */

            s->pm_regs[RCSR >> 2] |= 0x8;        /* Set GPR */

            /*

             * The scratch-pad register is almost universally used

             * for storing the return address on suspend.  For the

             * lack of a resuming bootloader, perform a jump

             * directly to that address.

             */

            memset(s->env->regs, 0, 4 * 15);

            s->env->regs[15] = s->pm_regs[PSPR >> 2];

#if 0

            buffer = 0xe59ff000;        /* ldr     pc, [pc, #0] */

            cpu_physical_memory_write(0, &buffer, 4);

            buffer = s->pm_regs[PSPR >> 2];

            cpu_physical_memory_write(8, &buffer, 4);

#endif

            /* Suspend */

            cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);

            goto message;

        default:

        message:

            printf("%s: machine entered %s mode\n", __FUNCTION__,

                            pwrmode[value & 7]);

        }

        break;

    default:

        printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

        break;

    }

}

/* Performace Monitoring Registers */

#define CPPMNC                0        /* Performance Monitor Control register */

#define CPCCNT                1        /* Clock Counter register */

#define CPINTEN                4        /* Interrupt Enable register */

#define CPFLAG                5        /* Overflow Flag register */

#define CPEVTSEL        8        /* Event Selection register */

#define CPPMN0                0        /* Performance Count register 0 */

#define CPPMN1                1        /* Performance Count register 1 */

#define CPPMN2                2        /* Performance Count register 2 */

#define CPPMN3                3        /* Performance Count register 3 */

static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (reg) {

    case CPPMNC:

        return s->pmnc;

    case CPCCNT:

        if (s->pmnc & 1)

            return qemu_get_clock_ns(vm_clock);

        else

            return 0;

    case CPINTEN:

    case CPFLAG:

    case CPEVTSEL:

        return 0;

    default:

        printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

        break;

    }

    return 0;

}

static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,

                uint32_t value)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (reg) {

    case CPPMNC:

        s->pmnc = value;

        break;

    case CPCCNT:

    case CPINTEN:

    case CPFLAG:

    case CPEVTSEL:

        break;

    default:

        printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

        break;

    }

}

static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)

{

    switch (crm) {

    case 0:

        return pxa2xx_clkpwr_read(opaque, op2, reg, crm);

    case 1:

        return pxa2xx_perf_read(opaque, op2, reg, crm);

    case 2:

        switch (reg) {

        case CPPMN0:

        case CPPMN1:

        case CPPMN2:

        case CPPMN3:

            return 0;

        }

        /* Fall through */

    default:

        printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

        break;

    }

    return 0;

}

static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,

                uint32_t value)

{

    switch (crm) {

    case 0:

        pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);

        break;

    case 1:

        pxa2xx_perf_write(opaque, op2, reg, crm, value);

        break;

    case 2:

        switch (reg) {

        case CPPMN0:

        case CPPMN1:

        case CPPMN2:

        case CPPMN3:

            return;

        }

        /* Fall through */

    default:

        printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);

        break;

    }

}

#define MDCNFG                0x00        /* SDRAM Configuration register */

#define MDREFR                0x04        /* SDRAM Refresh Control register */

#define MSC0                0x08        /* Static Memory Control register 0 */

#define MSC1                0x0c        /* Static Memory Control register 1 */

#define MSC2                0x10        /* Static Memory Control register 2 */

#define MECR                0x14        /* Expansion Memory Bus Config register */

#define SXCNFG                0x1c        /* Synchronous Static Memory Config register */

#define MCMEM0                0x28        /* PC Card Memory Socket 0 Timing register */

#define MCMEM1                0x2c        /* PC Card Memory Socket 1 Timing register */

#define MCATT0                0x30        /* PC Card Attribute Socket 0 register */

#define MCATT1                0x34        /* PC Card Attribute Socket 1 register */

#define MCIO0                0x38        /* PC Card I/O Socket 0 Timing register */

#define MCIO1                0x3c        /* PC Card I/O Socket 1 Timing register */

#define MDMRS                0x40        /* SDRAM Mode Register Set Config register */

#define BOOT_DEF        0x44        /* Boot-time Default Configuration register */

#define ARB_CNTL        0x48        /* Arbiter Control register */

#define BSCNTR0                0x4c        /* Memory Buffer Strength Control register 0 */

#define BSCNTR1                0x50        /* Memory Buffer Strength Control register 1 */

#define LCDBSCNTR        0x54        /* LCD Buffer Strength Control register */

#define MDMRSLP                0x58        /* Low Power SDRAM Mode Set Config register */

#define BSCNTR2                0x5c        /* Memory Buffer Strength Control register 2 */

#define BSCNTR3                0x60        /* Memory Buffer Strength Control register 3 */

#define SA1110                0x64        /* SA-1110 Memory Compatibility register */

static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (addr) {

    case MDCNFG ... SA1110:

        if ((addr & 3) == 0)

            return s->mm_regs[addr >> 2];

    default:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

    return 0;

}

static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    PXA2xxState *s = (PXA2xxState *) opaque;

    switch (addr) {

    case MDCNFG ... SA1110:

        if ((addr & 3) == 0) {

            s->mm_regs[addr >> 2] = value;

            break;

        }

    default:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

}

static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {

    pxa2xx_mm_read,

    pxa2xx_mm_read,

    pxa2xx_mm_read,

};

static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {

    pxa2xx_mm_write,

    pxa2xx_mm_write,

    pxa2xx_mm_write,

};

static const VMStateDescription vmstate_pxa2xx_mm = {

    .name = "pxa2xx_mm",

    .version_id = 0,

    .minimum_version_id = 0,

    .minimum_version_id_old = 0,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),

        VMSTATE_END_OF_LIST()

    }

};

/* Synchronous Serial Ports */

typedef struct {

    SysBusDevice busdev;

    qemu_irq irq;

    int enable;

    SSIBus *bus;

    uint32_t sscr[2];

    uint32_t sspsp;

    uint32_t ssto;

    uint32_t ssitr;

    uint32_t sssr;

    uint8_t sstsa;

    uint8_t ssrsa;

    uint8_t ssacd;

    uint32_t rx_fifo[16];

    int rx_level;

    int rx_start;

} PXA2xxSSPState;

#define SSCR0        0x00        /* SSP Control register 0 */

#define SSCR1        0x04        /* SSP Control register 1 */

#define SSSR        0x08        /* SSP Status register */

#define SSITR        0x0c        /* SSP Interrupt Test register */

#define SSDR        0x10        /* SSP Data register */

#define SSTO        0x28        /* SSP Time-Out register */

#define SSPSP        0x2c        /* SSP Programmable Serial Protocol register */

#define SSTSA        0x30        /* SSP TX Time Slot Active register */

#define SSRSA        0x34        /* SSP RX Time Slot Active register */

#define SSTSS        0x38        /* SSP Time Slot Status register */

#define SSACD        0x3c        /* SSP Audio Clock Divider register */

/* Bitfields for above registers */

#define SSCR0_SPI(x)        (((x) & 0x30) == 0x00)

#define SSCR0_SSP(x)        (((x) & 0x30) == 0x10)

#define SSCR0_UWIRE(x)        (((x) & 0x30) == 0x20)

#define SSCR0_PSP(x)        (((x) & 0x30) == 0x30)

#define SSCR0_SSE        (1 << 7)

#define SSCR0_RIM        (1 << 22)

#define SSCR0_TIM        (1 << 23)

#define SSCR0_MOD        (1 << 31)

#define SSCR0_DSS(x)        (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)

#define SSCR1_RIE        (1 << 0)

#define SSCR1_TIE        (1 << 1)

#define SSCR1_LBM        (1 << 2)

#define SSCR1_MWDS        (1 << 5)

#define SSCR1_TFT(x)        ((((x) >> 6) & 0xf) + 1)

#define SSCR1_RFT(x)        ((((x) >> 10) & 0xf) + 1)

#define SSCR1_EFWR        (1 << 14)

#define SSCR1_PINTE        (1 << 18)

#define SSCR1_TINTE        (1 << 19)

#define SSCR1_RSRE        (1 << 20)

#define SSCR1_TSRE        (1 << 21)

#define SSCR1_EBCEI        (1 << 29)

#define SSITR_INT        (7 << 5)

#define SSSR_TNF        (1 << 2)

#define SSSR_RNE        (1 << 3)

#define SSSR_TFS        (1 << 5)

#define SSSR_RFS        (1 << 6)

#define SSSR_ROR        (1 << 7)

#define SSSR_PINT        (1 << 18)

#define SSSR_TINT        (1 << 19)

#define SSSR_EOC        (1 << 20)

#define SSSR_TUR        (1 << 21)

#define SSSR_BCE        (1 << 23)

#define SSSR_RW                0x00bc0080

static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)

{

    int level = 0;

    level |= s->ssitr & SSITR_INT;

    level |= (s->sssr & SSSR_BCE)  &&  (s->sscr[1] & SSCR1_EBCEI);

    level |= (s->sssr & SSSR_TUR)  && !(s->sscr[0] & SSCR0_TIM);

    level |= (s->sssr & SSSR_EOC)  &&  (s->sssr & (SSSR_TINT | SSSR_PINT));

    level |= (s->sssr & SSSR_TINT) &&  (s->sscr[1] & SSCR1_TINTE);

    level |= (s->sssr & SSSR_PINT) &&  (s->sscr[1] & SSCR1_PINTE);

    level |= (s->sssr & SSSR_ROR)  && !(s->sscr[0] & SSCR0_RIM);

    level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);

    level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);

    qemu_set_irq(s->irq, !!level);

}

static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)

{

    s->sssr &= ~(0xf << 12);        /* Clear RFL */

    s->sssr &= ~(0xf << 8);        /* Clear TFL */

    s->sssr &= ~SSSR_TFS;

    s->sssr &= ~SSSR_TNF;

    if (s->enable) {

        s->sssr |= ((s->rx_level - 1) & 0xf) << 12;

        if (s->rx_level >= SSCR1_RFT(s->sscr[1]))

            s->sssr |= SSSR_RFS;

        else

            s->sssr &= ~SSSR_RFS;

        if (s->rx_level)

            s->sssr |= SSSR_RNE;

        else

            s->sssr &= ~SSSR_RNE;

        /* TX FIFO is never filled, so it is always in underrun

           condition if SSP is enabled */

        s->sssr |= SSSR_TFS;

        s->sssr |= SSSR_TNF;

    }

    pxa2xx_ssp_int_update(s);

}

static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)

{

    PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;

    uint32_t retval;

    switch (addr) {

    case SSCR0:

        return s->sscr[0];

    case SSCR1:

        return s->sscr[1];

    case SSPSP:

        return s->sspsp;

    case SSTO:

        return s->ssto;

    case SSITR:

        return s->ssitr;

    case SSSR:

        return s->sssr | s->ssitr;

    case SSDR:

        if (!s->enable)

            return 0xffffffff;

        if (s->rx_level < 1) {

            printf("%s: SSP Rx Underrun\n", __FUNCTION__);

            return 0xffffffff;

        }

        s->rx_level --;

        retval = s->rx_fifo[s->rx_start ++];

        s->rx_start &= 0xf;

        pxa2xx_ssp_fifo_update(s);

        return retval;

    case SSTSA:

        return s->sstsa;

    case SSRSA:

        return s->ssrsa;

    case SSTSS:

        return 0;

    case SSACD:

        return s->ssacd;

    default:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

    return 0;

}

static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,

                uint32_t value)

{

    PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;

    switch (addr) {

    case SSCR0:

        s->sscr[0] = value & 0xc7ffffff;

        s->enable = value & SSCR0_SSE;

        if (value & SSCR0_MOD)

            printf("%s: Attempt to use network mode\n", __FUNCTION__);

        if (s->enable && SSCR0_DSS(value) < 4)

            printf("%s: Wrong data size: %i bits\n", __FUNCTION__,

                            SSCR0_DSS(value));

        if (!(value & SSCR0_SSE)) {

            s->sssr = 0;

            s->ssitr = 0;

            s->rx_level = 0;

        }

        pxa2xx_ssp_fifo_update(s);

        break;

    case SSCR1:

        s->sscr[1] = value;

        if (value & (SSCR1_LBM | SSCR1_EFWR))

            printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);

        pxa2xx_ssp_fifo_update(s);

        break;

    case SSPSP:

        s->sspsp = value;

        break;

    case SSTO:

        s->ssto = value;

        break;

    case SSITR:

        s->ssitr = value & SSITR_INT;

        pxa2xx_ssp_int_update(s);

        break;

    case SSSR:

        s->sssr &= ~(value & SSSR_RW);

        pxa2xx_ssp_int_update(s);

        break;

    case SSDR:

        if (SSCR0_UWIRE(s->sscr[0])) {

            if (s->sscr[1] & SSCR1_MWDS)

                value &= 0xffff;

            else

                value &= 0xff;

        } else

            /* Note how 32bits overflow does no harm here */

            value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;

        /* Data goes from here to the Tx FIFO and is shifted out from

         * there directly to the slave, no need to buffer it.

         */

        if (s->enable) {

            uint32_t readval;

            readval = ssi_transfer(s->bus, value);

            if (s->rx_level < 0x10) {

                s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;

            } else {

                s->sssr |= SSSR_ROR;

            }

        }

        pxa2xx_ssp_fifo_update(s);

        break;

    case SSTSA:

        s->sstsa = value;

        break;

    case SSRSA:

        s->ssrsa = value;

        break;

    case SSACD:

        s->ssacd = value;

        break;

    default:

        printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);

        break;

    }

}

static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {

    pxa2xx_ssp_read,

    pxa2xx_ssp_read,

    pxa2xx_ssp_read,

};

static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {

    pxa2xx_ssp_write,

    pxa2xx_ssp_write,

    pxa2xx_ssp_write,

};

static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)

{

    PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;

    int i;

    qemu_put_be32(f, s->enable);

    qemu_put_be32s(f, &s->sscr[0]);

    qemu_put_be32s(f, &s->sscr[1]);

    qemu_put_be32s(f, &s->sspsp);

    qemu_put_be32s(f, &s->ssto);

    qemu_put_be32s(f, &s->ssitr);

    qemu_put_be32s(f, &s->sssr);

    qemu_put_8s(f, &s->sstsa);

    qemu_put_8s(f, &s->ssrsa);

    qemu_put_8s(f, &s->ssacd);

    qemu_put_byte(f, s->rx_level);

    for (i = 0; i < s->rx_level; i ++)

        qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);

}

static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)

{

    PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;

    int i;

    s->enable = qemu_get_be32(f);

    qemu_get_be32s(f, &s->sscr[0]);

    qemu_get_be32s(f, &s->sscr[1]);

    qemu_get_be32s(f, &s->sspsp);

    qemu_get_be32s(f, &s->ssto);

    qemu_get_be32s(f, &s->ssitr);

    qemu_get_be32s(f, &s->sssr);

    qemu_get_8s(f, &s->sstsa);

    qemu_get_8s(f, &s->ssrsa);

    qemu_get_8s(f, &s->ssacd);

    s->rx_level = qemu_get_byte(f);

    s->rx_start = 0;

    for (i = 0; i < s->rx_level; i ++)

        s->rx_fifo[i] = qemu_get_byte(f);

    return 0;

}

static int pxa2xx_ssp_init(SysBusDevice *dev)

{

    int iomemtype;

    PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);

    sysbus_init_irq(dev, &s->irq);

    iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,

                                       pxa2xx_ssp_writefn, s,

                                       DEVICE_NATIVE_ENDIAN);

    sysbus_init_mmio(dev, 0x1000, iomemtype);

    register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,

                    pxa2xx_ssp_save, pxa2xx_ssp_load, s);

    s->bus = ssi_create_bus(&dev->qdev, "ssi");

    return 0;

}

/* Real-Time Clock */

#define RCNR                0x00        /* RTC Counter register */

#define RTAR                0x04        /* RTC Alarm register */

#define RTSR                0x08        /* RTC Status register */

#define RTTR                0x0c        /* RTC Timer Trim register */

#define RDCR                0x10        /* RTC Day Counter register */

#define RYCR                0x14        /* RTC Year Counter register */

#define RDAR1                0x18        /* RTC Wristwatch Day Alarm register 1 */

#define RYAR1                0x1c        /* RTC Wristwatch Year Alarm register 1 */

#define RDAR2                0x20        /* RTC Wristwatch Day Alarm register 2 */

#define RYAR2                0x24        /* RTC Wristwatch Year Alarm register 2 */

#define SWCR                0x28        /* RTC Stopwatch Counter register */

#define SWAR1                0x2c        /* RTC Stopwatch Alarm register 1 */

#define SWAR2                0x30        /* RTC Stopwatch Alarm register 2 */