Revision 14a10fc3
| b/qom/cpu.c | ||
|---|---|---|
| 228 | 228 |
{
|
| 229 | 229 |
CPUState *cpu = CPU(dev); |
| 230 | 230 |
|
| 231 |
qemu_init_vcpu(cpu); |
|
| 232 |
|
|
| 233 | 231 |
if (dev->hotplugged) {
|
| 234 | 232 |
cpu_synchronize_post_init(cpu); |
| 235 | 233 |
notifier_list_notify(&cpu_added_notifiers, dev); |
| b/target-alpha/cpu.c | ||
|---|---|---|
| 33 | 33 |
|
| 34 | 34 |
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) |
| 35 | 35 |
{
|
| 36 |
CPUState *cs = CPU(dev); |
|
| 36 | 37 |
AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); |
| 37 | 38 |
|
| 39 |
qemu_init_vcpu(cs); |
|
| 40 |
|
|
| 38 | 41 |
acc->parent_realize(dev, errp); |
| 39 | 42 |
} |
| 40 | 43 |
|
| b/target-arm/cpu.c | ||
|---|---|---|
| 159 | 159 |
|
| 160 | 160 |
static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
| 161 | 161 |
{
|
| 162 |
CPUState *cs = CPU(dev); |
|
| 162 | 163 |
ARMCPU *cpu = ARM_CPU(dev); |
| 163 | 164 |
ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); |
| 164 | 165 |
CPUARMState *env = &cpu->env; |
| ... | ... | |
| 214 | 215 |
|
| 215 | 216 |
init_cpreg_list(cpu); |
| 216 | 217 |
|
| 217 |
cpu_reset(CPU(cpu)); |
|
| 218 |
cpu_reset(cs); |
|
| 219 |
qemu_init_vcpu(cs); |
|
| 218 | 220 |
|
| 219 | 221 |
acc->parent_realize(dev, errp); |
| 220 | 222 |
} |
| b/target-cris/cpu.c | ||
|---|---|---|
| 137 | 137 |
|
| 138 | 138 |
static void cris_cpu_realizefn(DeviceState *dev, Error **errp) |
| 139 | 139 |
{
|
| 140 |
CRISCPU *cpu = CRIS_CPU(dev);
|
|
| 140 |
CPUState *cs = CPU(dev);
|
|
| 141 | 141 |
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); |
| 142 | 142 |
|
| 143 |
cpu_reset(CPU(cpu)); |
|
| 143 |
cpu_reset(cs); |
|
| 144 |
qemu_init_vcpu(cs); |
|
| 144 | 145 |
|
| 145 | 146 |
ccc->parent_realize(dev, errp); |
| 146 | 147 |
} |
| b/target-i386/cpu.c | ||
|---|---|---|
| 2333 | 2333 |
|
| 2334 | 2334 |
static void x86_cpu_realizefn(DeviceState *dev, Error **errp) |
| 2335 | 2335 |
{
|
| 2336 |
CPUState *cs = CPU(dev); |
|
| 2336 | 2337 |
X86CPU *cpu = X86_CPU(dev); |
| 2337 | 2338 |
X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); |
| 2338 | 2339 |
CPUX86State *env = &cpu->env; |
| ... | ... | |
| 2387 | 2388 |
#endif |
| 2388 | 2389 |
|
| 2389 | 2390 |
mce_init(cpu); |
| 2391 |
qemu_init_vcpu(cs); |
|
| 2390 | 2392 |
|
| 2391 | 2393 |
x86_cpu_apic_realize(cpu, &local_err); |
| 2392 | 2394 |
if (local_err != NULL) {
|
| 2393 | 2395 |
goto out; |
| 2394 | 2396 |
} |
| 2395 |
cpu_reset(CPU(cpu));
|
|
| 2397 |
cpu_reset(cs);
|
|
| 2396 | 2398 |
|
| 2397 | 2399 |
xcc->parent_realize(dev, &local_err); |
| 2398 | 2400 |
out: |
| b/target-lm32/cpu.c | ||
|---|---|---|
| 46 | 46 |
|
| 47 | 47 |
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp) |
| 48 | 48 |
{
|
| 49 |
LM32CPU *cpu = LM32_CPU(dev);
|
|
| 49 |
CPUState *cs = CPU(dev);
|
|
| 50 | 50 |
LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev); |
| 51 | 51 |
|
| 52 |
cpu_reset(CPU(cpu)); |
|
| 52 |
cpu_reset(cs); |
|
| 53 |
|
|
| 54 |
qemu_init_vcpu(cs); |
|
| 53 | 55 |
|
| 54 | 56 |
lcc->parent_realize(dev, errp); |
| 55 | 57 |
} |
| b/target-m68k/cpu.c | ||
|---|---|---|
| 143 | 143 |
|
| 144 | 144 |
static void m68k_cpu_realizefn(DeviceState *dev, Error **errp) |
| 145 | 145 |
{
|
| 146 |
CPUState *cs = CPU(dev); |
|
| 146 | 147 |
M68kCPU *cpu = M68K_CPU(dev); |
| 147 | 148 |
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev); |
| 148 | 149 |
|
| 149 | 150 |
m68k_cpu_init_gdb(cpu); |
| 150 | 151 |
|
| 151 |
cpu_reset(CPU(cpu)); |
|
| 152 |
cpu_reset(cs); |
|
| 153 |
qemu_init_vcpu(cs); |
|
| 152 | 154 |
|
| 153 | 155 |
mcc->parent_realize(dev, errp); |
| 154 | 156 |
} |
| b/target-microblaze/cpu.c | ||
|---|---|---|
| 90 | 90 |
|
| 91 | 91 |
static void mb_cpu_realizefn(DeviceState *dev, Error **errp) |
| 92 | 92 |
{
|
| 93 |
MicroBlazeCPU *cpu = MICROBLAZE_CPU(dev);
|
|
| 93 |
CPUState *cs = CPU(dev);
|
|
| 94 | 94 |
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); |
| 95 | 95 |
|
| 96 |
cpu_reset(CPU(cpu)); |
|
| 96 |
cpu_reset(cs); |
|
| 97 |
qemu_init_vcpu(cs); |
|
| 97 | 98 |
|
| 98 | 99 |
mcc->parent_realize(dev, errp); |
| 99 | 100 |
} |
| b/target-mips/cpu.c | ||
|---|---|---|
| 62 | 62 |
|
| 63 | 63 |
static void mips_cpu_realizefn(DeviceState *dev, Error **errp) |
| 64 | 64 |
{
|
| 65 |
MIPSCPU *cpu = MIPS_CPU(dev);
|
|
| 65 |
CPUState *cs = CPU(dev);
|
|
| 66 | 66 |
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); |
| 67 | 67 |
|
| 68 |
cpu_reset(CPU(cpu)); |
|
| 68 |
cpu_reset(cs); |
|
| 69 |
qemu_init_vcpu(cs); |
|
| 69 | 70 |
|
| 70 | 71 |
mcc->parent_realize(dev, errp); |
| 71 | 72 |
} |
| b/target-moxie/cpu.c | ||
|---|---|---|
| 45 | 45 |
|
| 46 | 46 |
static void moxie_cpu_realizefn(DeviceState *dev, Error **errp) |
| 47 | 47 |
{
|
| 48 |
MoxieCPU *cpu = MOXIE_CPU(dev);
|
|
| 48 |
CPUState *cs = CPU(dev);
|
|
| 49 | 49 |
MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(dev); |
| 50 | 50 |
|
| 51 |
cpu_reset(CPU(cpu)); |
|
| 51 |
qemu_init_vcpu(cs); |
|
| 52 |
cpu_reset(cs); |
|
| 52 | 53 |
|
| 53 | 54 |
mcc->parent_realize(dev, errp); |
| 54 | 55 |
} |
| b/target-openrisc/cpu.c | ||
|---|---|---|
| 66 | 66 |
|
| 67 | 67 |
static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) |
| 68 | 68 |
{
|
| 69 |
OpenRISCCPU *cpu = OPENRISC_CPU(dev);
|
|
| 69 |
CPUState *cs = CPU(dev);
|
|
| 70 | 70 |
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); |
| 71 | 71 |
|
| 72 |
cpu_reset(CPU(cpu)); |
|
| 72 |
qemu_init_vcpu(cs); |
|
| 73 |
cpu_reset(cs); |
|
| 73 | 74 |
|
| 74 | 75 |
occ->parent_realize(dev, errp); |
| 75 | 76 |
} |
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 7861 | 7861 |
34, "power-spe.xml", 0); |
| 7862 | 7862 |
} |
| 7863 | 7863 |
|
| 7864 |
qemu_init_vcpu(cs); |
|
| 7865 |
|
|
| 7864 | 7866 |
pcc->parent_realize(dev, errp); |
| 7865 | 7867 |
|
| 7866 | 7868 |
#if defined(PPC_DUMP_CPU) |
| b/target-s390x/cpu.c | ||
|---|---|---|
| 101 | 101 |
|
| 102 | 102 |
static void s390_cpu_realizefn(DeviceState *dev, Error **errp) |
| 103 | 103 |
{
|
| 104 |
S390CPU *cpu = S390_CPU(dev);
|
|
| 104 |
CPUState *cs = CPU(dev);
|
|
| 105 | 105 |
S390CPUClass *scc = S390_CPU_GET_CLASS(dev); |
| 106 | 106 |
|
| 107 |
cpu_reset(CPU(cpu)); |
|
| 107 |
qemu_init_vcpu(cs); |
|
| 108 |
cpu_reset(cs); |
|
| 108 | 109 |
|
| 109 | 110 |
scc->parent_realize(dev, errp); |
| 110 | 111 |
} |
| b/target-sh4/cpu.c | ||
|---|---|---|
| 240 | 240 |
|
| 241 | 241 |
static void superh_cpu_realizefn(DeviceState *dev, Error **errp) |
| 242 | 242 |
{
|
| 243 |
SuperHCPU *cpu = SUPERH_CPU(dev);
|
|
| 243 |
CPUState *cs = CPU(dev);
|
|
| 244 | 244 |
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); |
| 245 | 245 |
|
| 246 |
cpu_reset(CPU(cpu)); |
|
| 246 |
cpu_reset(cs); |
|
| 247 |
qemu_init_vcpu(cs); |
|
| 247 | 248 |
|
| 248 | 249 |
scc->parent_realize(dev, errp); |
| 249 | 250 |
} |
| b/target-sparc/cpu.c | ||
|---|---|---|
| 743 | 743 |
{
|
| 744 | 744 |
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); |
| 745 | 745 |
|
| 746 |
qemu_init_vcpu(CPU(dev)); |
|
| 747 |
|
|
| 746 | 748 |
scc->parent_realize(dev, errp); |
| 747 | 749 |
} |
| 748 | 750 |
|
| b/target-unicore32/cpu.c | ||
|---|---|---|
| 92 | 92 |
{
|
| 93 | 93 |
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev); |
| 94 | 94 |
|
| 95 |
qemu_init_vcpu(CPU(dev)); |
|
| 96 |
|
|
| 95 | 97 |
ucc->parent_realize(dev, errp); |
| 96 | 98 |
} |
| 97 | 99 |
|
| b/target-xtensa/cpu.c | ||
|---|---|---|
| 90 | 90 |
|
| 91 | 91 |
cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; |
| 92 | 92 |
|
| 93 |
qemu_init_vcpu(cs); |
|
| 94 |
|
|
| 93 | 95 |
xcc->parent_realize(dev, errp); |
| 94 | 96 |
} |
| 95 | 97 |
|
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