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/*
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* QEMU 16550A UART emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2008 Citrix Systems, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-char.h" |
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#include "isa.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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//#define DEBUG_SERIAL
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
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|
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
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|
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
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#define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
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#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ |
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#define UART_IIR_FE 0xC0 /* Fifo enabled */ |
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
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#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
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#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
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#define UART_MCR_RTS 0x02 /* RTS complement */ |
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#define UART_MCR_DTR 0x01 /* DTR complement */ |
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
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#define UART_MSR_RI 0x40 /* Ring Indicator */ |
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#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
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#define UART_MSR_CTS 0x10 /* Clear to Send */ |
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#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
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#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
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#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
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#define UART_LSR_FE 0x08 /* Frame error indicator */ |
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#define UART_LSR_PE 0x04 /* Parity error indicator */ |
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#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
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#define UART_LSR_DR 0x01 /* Receiver data ready */ |
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#define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
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#define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ |
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#define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ |
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#define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ |
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#define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ |
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#define UART_FCR_DMS 0x08 /* DMA Mode Select */ |
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#define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ |
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#define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ |
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#define UART_FCR_FE 0x01 /* FIFO Enable */ |
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#define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ |
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#define XMIT_FIFO 0 |
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#define RECV_FIFO 1 |
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#define MAX_XMIT_RETRY 4 |
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typedef struct SerialFIFO { |
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uint8_t data[UART_FIFO_LENGTH]; |
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uint8_t count; |
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uint8_t itl; /* Interrupt Trigger Level */
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uint8_t tail; |
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uint8_t head; |
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} SerialFIFO; |
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struct SerialState {
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uint16_t divider; |
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uint8_t rbr; /* receive register */
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uint8_t thr; /* transmit holding register */
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uint8_t tsr; /* transmit shift register */
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uint8_t ier; |
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uint8_t iir; /* read only */
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uint8_t lcr; |
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uint8_t mcr; |
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uint8_t lsr; /* read only */
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uint8_t msr; /* read only */
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uint8_t scr; |
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uint8_t fcr; |
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uint8_t fcr_vmstate; /* we can't write directly this value
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it has side effects */
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/* NOTE: this hidden state is necessary for tx irq generation as
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it can be reset while reading iir */
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int thr_ipending;
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qemu_irq irq; |
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CharDriverState *chr; |
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int last_break_enable;
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int it_shift;
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int baudbase;
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int tsr_retry;
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uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
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SerialFIFO recv_fifo; |
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SerialFIFO xmit_fifo; |
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struct QEMUTimer *fifo_timeout_timer;
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int timeout_ipending; /* timeout interrupt pending state */ |
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struct QEMUTimer *transmit_timer;
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uint64_t char_transmit_time; /* time to transmit a char in ticks*/
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int poll_msl;
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struct QEMUTimer *modem_status_poll;
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}; |
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typedef struct ISASerialState { |
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ISADevice dev; |
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uint32_t index; |
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uint32_t iobase; |
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uint32_t isairq; |
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SerialState state; |
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} ISASerialState; |
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static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
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static void fifo_clear(SerialState *s, int fifo) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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memset(f->data, 0, UART_FIFO_LENGTH);
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f->count = 0;
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f->head = 0;
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f->tail = 0;
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} |
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static int fifo_put(SerialState *s, int fifo, uint8_t chr) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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f->data[f->head++] = chr; |
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if (f->head == UART_FIFO_LENGTH)
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f->head = 0;
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f->count++; |
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return 1; |
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} |
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static uint8_t fifo_get(SerialState *s, int fifo) |
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{ |
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SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo; |
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uint8_t c; |
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if(f->count == 0) |
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return 0; |
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c = f->data[f->tail++]; |
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if (f->tail == UART_FIFO_LENGTH)
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f->tail = 0;
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f->count--; |
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return c;
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} |
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static void serial_update_irq(SerialState *s) |
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{ |
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uint8_t tmp_iir = UART_IIR_NO_INT; |
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if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
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tmp_iir = UART_IIR_RLSI; |
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} else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
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/* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
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* this is not in the specification but is observed on existing
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* hardware. */
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tmp_iir = UART_IIR_CTI; |
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} else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
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(!(s->fcr & UART_FCR_FE) || |
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s->recv_fifo.count >= s->recv_fifo.itl)) { |
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tmp_iir = UART_IIR_RDI; |
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} else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
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tmp_iir = UART_IIR_THRI; |
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} else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { |
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tmp_iir = UART_IIR_MSI; |
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} |
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s->iir = tmp_iir | (s->iir & 0xF0);
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if (tmp_iir != UART_IIR_NO_INT) {
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qemu_irq_raise(s->irq); |
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} else {
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qemu_irq_lower(s->irq); |
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} |
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} |
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static void serial_update_parameters(SerialState *s) |
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{ |
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int speed, parity, data_bits, stop_bits, frame_size;
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QEMUSerialSetParams ssp; |
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if (s->divider == 0) |
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return;
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frame_size = 1;
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if (s->lcr & 0x08) { |
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if (s->lcr & 0x10) |
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parity = 'E';
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else
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parity = 'O';
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} else {
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parity = 'N';
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frame_size = 0;
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} |
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if (s->lcr & 0x04) |
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stop_bits = 2;
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else
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stop_bits = 1;
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data_bits = (s->lcr & 0x03) + 5; |
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frame_size += data_bits + stop_bits; |
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speed = s->baudbase / s->divider; |
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ssp.speed = speed; |
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ssp.parity = parity; |
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ssp.data_bits = data_bits; |
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ssp.stop_bits = stop_bits; |
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s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; |
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qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
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#if 0
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printf("speed=%d parity=%c data=%d stop=%d\n",
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speed, parity, data_bits, stop_bits);
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#endif
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} |
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static void serial_update_msl(SerialState *s) |
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{ |
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uint8_t omsr; |
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int flags;
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qemu_del_timer(s->modem_status_poll); |
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if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
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s->poll_msl = -1;
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return;
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} |
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omsr = s->msr; |
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s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; |
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s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; |
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s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; |
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s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; |
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if (s->msr != omsr) {
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/* Set delta bits */
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s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); |
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/* UART_MSR_TERI only if change was from 1 -> 0 */
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if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
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s->msr &= ~UART_MSR_TERI; |
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serial_update_irq(s); |
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} |
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/* The real 16550A apparently has a 250ns response latency to line status changes.
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We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
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if (s->poll_msl)
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qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + get_ticks_per_sec() / 100);
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} |
299 |
|
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static void serial_xmit(void *opaque) |
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{ |
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SerialState *s = opaque; |
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uint64_t new_xmit_ts = qemu_get_clock(vm_clock); |
304 |
|
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if (s->tsr_retry <= 0) { |
306 |
if (s->fcr & UART_FCR_FE) {
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s->tsr = fifo_get(s,XMIT_FIFO); |
308 |
if (!s->xmit_fifo.count)
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s->lsr |= UART_LSR_THRE; |
310 |
} else {
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s->tsr = s->thr; |
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s->lsr |= UART_LSR_THRE; |
313 |
} |
314 |
} |
315 |
|
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if (s->mcr & UART_MCR_LOOP) {
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/* in loopback mode, say that we just received a char */
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serial_receive1(s, &s->tsr, 1);
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} else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) { |
320 |
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) { |
321 |
s->tsr_retry++; |
322 |
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time); |
323 |
return;
|
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} else if (s->poll_msl < 0) { |
325 |
/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
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drop any further failed writes instantly, until we get one that goes through.
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This is to prevent guests that log to unconnected pipes or pty's from stalling. */
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s->tsr_retry = -1;
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} |
330 |
} |
331 |
else {
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s->tsr_retry = 0;
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} |
334 |
|
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s->last_xmit_ts = qemu_get_clock(vm_clock); |
336 |
if (!(s->lsr & UART_LSR_THRE))
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qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time); |
338 |
|
339 |
if (s->lsr & UART_LSR_THRE) {
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340 |
s->lsr |= UART_LSR_TEMT; |
341 |
s->thr_ipending = 1;
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serial_update_irq(s); |
343 |
} |
344 |
} |
345 |
|
346 |
|
347 |
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
348 |
{ |
349 |
SerialState *s = opaque; |
350 |
|
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addr &= 7;
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#ifdef DEBUG_SERIAL
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printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
|
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default:
|
357 |
case 0: |
358 |
if (s->lcr & UART_LCR_DLAB) {
|
359 |
s->divider = (s->divider & 0xff00) | val;
|
360 |
serial_update_parameters(s); |
361 |
} else {
|
362 |
s->thr = (uint8_t) val; |
363 |
if(s->fcr & UART_FCR_FE) {
|
364 |
fifo_put(s, XMIT_FIFO, s->thr); |
365 |
s->thr_ipending = 0;
|
366 |
s->lsr &= ~UART_LSR_TEMT; |
367 |
s->lsr &= ~UART_LSR_THRE; |
368 |
serial_update_irq(s); |
369 |
} else {
|
370 |
s->thr_ipending = 0;
|
371 |
s->lsr &= ~UART_LSR_THRE; |
372 |
serial_update_irq(s); |
373 |
} |
374 |
serial_xmit(s); |
375 |
} |
376 |
break;
|
377 |
case 1: |
378 |
if (s->lcr & UART_LCR_DLAB) {
|
379 |
s->divider = (s->divider & 0x00ff) | (val << 8); |
380 |
serial_update_parameters(s); |
381 |
} else {
|
382 |
s->ier = val & 0x0f;
|
383 |
/* If the backend device is a real serial port, turn polling of the modem
|
384 |
status lines on physical port on or off depending on UART_IER_MSI state */
|
385 |
if (s->poll_msl >= 0) { |
386 |
if (s->ier & UART_IER_MSI) {
|
387 |
s->poll_msl = 1;
|
388 |
serial_update_msl(s); |
389 |
} else {
|
390 |
qemu_del_timer(s->modem_status_poll); |
391 |
s->poll_msl = 0;
|
392 |
} |
393 |
} |
394 |
if (s->lsr & UART_LSR_THRE) {
|
395 |
s->thr_ipending = 1;
|
396 |
serial_update_irq(s); |
397 |
} |
398 |
} |
399 |
break;
|
400 |
case 2: |
401 |
val = val & 0xFF;
|
402 |
|
403 |
if (s->fcr == val)
|
404 |
break;
|
405 |
|
406 |
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
|
407 |
if ((val ^ s->fcr) & UART_FCR_FE)
|
408 |
val |= UART_FCR_XFR | UART_FCR_RFR; |
409 |
|
410 |
/* FIFO clear */
|
411 |
|
412 |
if (val & UART_FCR_RFR) {
|
413 |
qemu_del_timer(s->fifo_timeout_timer); |
414 |
s->timeout_ipending=0;
|
415 |
fifo_clear(s,RECV_FIFO); |
416 |
} |
417 |
|
418 |
if (val & UART_FCR_XFR) {
|
419 |
fifo_clear(s,XMIT_FIFO); |
420 |
} |
421 |
|
422 |
if (val & UART_FCR_FE) {
|
423 |
s->iir |= UART_IIR_FE; |
424 |
/* Set RECV_FIFO trigger Level */
|
425 |
switch (val & 0xC0) { |
426 |
case UART_FCR_ITL_1:
|
427 |
s->recv_fifo.itl = 1;
|
428 |
break;
|
429 |
case UART_FCR_ITL_2:
|
430 |
s->recv_fifo.itl = 4;
|
431 |
break;
|
432 |
case UART_FCR_ITL_3:
|
433 |
s->recv_fifo.itl = 8;
|
434 |
break;
|
435 |
case UART_FCR_ITL_4:
|
436 |
s->recv_fifo.itl = 14;
|
437 |
break;
|
438 |
} |
439 |
} else
|
440 |
s->iir &= ~UART_IIR_FE; |
441 |
|
442 |
/* Set fcr - or at least the bits in it that are supposed to "stick" */
|
443 |
s->fcr = val & 0xC9;
|
444 |
serial_update_irq(s); |
445 |
break;
|
446 |
case 3: |
447 |
{ |
448 |
int break_enable;
|
449 |
s->lcr = val; |
450 |
serial_update_parameters(s); |
451 |
break_enable = (val >> 6) & 1; |
452 |
if (break_enable != s->last_break_enable) {
|
453 |
s->last_break_enable = break_enable; |
454 |
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
455 |
&break_enable); |
456 |
} |
457 |
} |
458 |
break;
|
459 |
case 4: |
460 |
{ |
461 |
int flags;
|
462 |
int old_mcr = s->mcr;
|
463 |
s->mcr = val & 0x1f;
|
464 |
if (val & UART_MCR_LOOP)
|
465 |
break;
|
466 |
|
467 |
if (s->poll_msl >= 0 && old_mcr != s->mcr) { |
468 |
|
469 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
470 |
|
471 |
flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); |
472 |
|
473 |
if (val & UART_MCR_RTS)
|
474 |
flags |= CHR_TIOCM_RTS; |
475 |
if (val & UART_MCR_DTR)
|
476 |
flags |= CHR_TIOCM_DTR; |
477 |
|
478 |
qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
479 |
/* Update the modem status after a one-character-send wait-time, since there may be a response
|
480 |
from the device/computer at the other end of the serial line */
|
481 |
qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time); |
482 |
} |
483 |
} |
484 |
break;
|
485 |
case 5: |
486 |
break;
|
487 |
case 6: |
488 |
break;
|
489 |
case 7: |
490 |
s->scr = val; |
491 |
break;
|
492 |
} |
493 |
} |
494 |
|
495 |
static uint32_t serial_ioport_read(void *opaque, uint32_t addr) |
496 |
{ |
497 |
SerialState *s = opaque; |
498 |
uint32_t ret; |
499 |
|
500 |
addr &= 7;
|
501 |
switch(addr) {
|
502 |
default:
|
503 |
case 0: |
504 |
if (s->lcr & UART_LCR_DLAB) {
|
505 |
ret = s->divider & 0xff;
|
506 |
} else {
|
507 |
if(s->fcr & UART_FCR_FE) {
|
508 |
ret = fifo_get(s,RECV_FIFO); |
509 |
if (s->recv_fifo.count == 0) |
510 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
511 |
else
|
512 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
513 |
s->timeout_ipending = 0;
|
514 |
} else {
|
515 |
ret = s->rbr; |
516 |
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
517 |
} |
518 |
serial_update_irq(s); |
519 |
if (!(s->mcr & UART_MCR_LOOP)) {
|
520 |
/* in loopback mode, don't receive any data */
|
521 |
qemu_chr_accept_input(s->chr); |
522 |
} |
523 |
} |
524 |
break;
|
525 |
case 1: |
526 |
if (s->lcr & UART_LCR_DLAB) {
|
527 |
ret = (s->divider >> 8) & 0xff; |
528 |
} else {
|
529 |
ret = s->ier; |
530 |
} |
531 |
break;
|
532 |
case 2: |
533 |
ret = s->iir; |
534 |
s->thr_ipending = 0;
|
535 |
serial_update_irq(s); |
536 |
break;
|
537 |
case 3: |
538 |
ret = s->lcr; |
539 |
break;
|
540 |
case 4: |
541 |
ret = s->mcr; |
542 |
break;
|
543 |
case 5: |
544 |
ret = s->lsr; |
545 |
/* Clear break interrupt */
|
546 |
if (s->lsr & UART_LSR_BI) {
|
547 |
s->lsr &= ~UART_LSR_BI; |
548 |
serial_update_irq(s); |
549 |
} |
550 |
break;
|
551 |
case 6: |
552 |
if (s->mcr & UART_MCR_LOOP) {
|
553 |
/* in loopback, the modem output pins are connected to the
|
554 |
inputs */
|
555 |
ret = (s->mcr & 0x0c) << 4; |
556 |
ret |= (s->mcr & 0x02) << 3; |
557 |
ret |= (s->mcr & 0x01) << 5; |
558 |
} else {
|
559 |
if (s->poll_msl >= 0) |
560 |
serial_update_msl(s); |
561 |
ret = s->msr; |
562 |
/* Clear delta bits & msr int after read, if they were set */
|
563 |
if (s->msr & UART_MSR_ANY_DELTA) {
|
564 |
s->msr &= 0xF0;
|
565 |
serial_update_irq(s); |
566 |
} |
567 |
} |
568 |
break;
|
569 |
case 7: |
570 |
ret = s->scr; |
571 |
break;
|
572 |
} |
573 |
#ifdef DEBUG_SERIAL
|
574 |
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
575 |
#endif
|
576 |
return ret;
|
577 |
} |
578 |
|
579 |
static int serial_can_receive(SerialState *s) |
580 |
{ |
581 |
if(s->fcr & UART_FCR_FE) {
|
582 |
if(s->recv_fifo.count < UART_FIFO_LENGTH)
|
583 |
/* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
|
584 |
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
|
585 |
effectively overriding the ITL that the guest has set. */
|
586 |
return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1; |
587 |
else
|
588 |
return 0; |
589 |
} else {
|
590 |
return !(s->lsr & UART_LSR_DR);
|
591 |
} |
592 |
} |
593 |
|
594 |
static void serial_receive_break(SerialState *s) |
595 |
{ |
596 |
s->rbr = 0;
|
597 |
/* When the LSR_DR is set a null byte is pushed into the fifo */
|
598 |
fifo_put(s, RECV_FIFO, '\0');
|
599 |
s->lsr |= UART_LSR_BI | UART_LSR_DR; |
600 |
serial_update_irq(s); |
601 |
} |
602 |
|
603 |
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
|
604 |
static void fifo_timeout_int (void *opaque) { |
605 |
SerialState *s = opaque; |
606 |
if (s->recv_fifo.count) {
|
607 |
s->timeout_ipending = 1;
|
608 |
serial_update_irq(s); |
609 |
} |
610 |
} |
611 |
|
612 |
static int serial_can_receive1(void *opaque) |
613 |
{ |
614 |
SerialState *s = opaque; |
615 |
return serial_can_receive(s);
|
616 |
} |
617 |
|
618 |
static void serial_receive1(void *opaque, const uint8_t *buf, int size) |
619 |
{ |
620 |
SerialState *s = opaque; |
621 |
if(s->fcr & UART_FCR_FE) {
|
622 |
int i;
|
623 |
for (i = 0; i < size; i++) { |
624 |
fifo_put(s, RECV_FIFO, buf[i]); |
625 |
} |
626 |
s->lsr |= UART_LSR_DR; |
627 |
/* call the timeout receive callback in 4 char transmit time */
|
628 |
qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
|
629 |
} else {
|
630 |
s->rbr = buf[0];
|
631 |
s->lsr |= UART_LSR_DR; |
632 |
} |
633 |
serial_update_irq(s); |
634 |
} |
635 |
|
636 |
static void serial_event(void *opaque, int event) |
637 |
{ |
638 |
SerialState *s = opaque; |
639 |
#ifdef DEBUG_SERIAL
|
640 |
printf("serial: event %x\n", event);
|
641 |
#endif
|
642 |
if (event == CHR_EVENT_BREAK)
|
643 |
serial_receive_break(s); |
644 |
} |
645 |
|
646 |
static void serial_pre_save(void *opaque) |
647 |
{ |
648 |
SerialState *s = opaque; |
649 |
s->fcr_vmstate = s->fcr; |
650 |
} |
651 |
|
652 |
static int serial_post_load(void *opaque, int version_id) |
653 |
{ |
654 |
SerialState *s = opaque; |
655 |
|
656 |
if (version_id < 3) { |
657 |
s->fcr_vmstate = 0;
|
658 |
} |
659 |
/* Initialize fcr via setter to perform essential side-effects */
|
660 |
serial_ioport_write(s, 0x02, s->fcr_vmstate);
|
661 |
return 0; |
662 |
} |
663 |
|
664 |
static const VMStateDescription vmstate_serial = { |
665 |
.name = "serial",
|
666 |
.version_id = 3,
|
667 |
.minimum_version_id = 2,
|
668 |
.pre_save = serial_pre_save, |
669 |
.post_load = serial_post_load, |
670 |
.fields = (VMStateField []) { |
671 |
VMSTATE_UINT16_V(divider, SerialState, 2),
|
672 |
VMSTATE_UINT8(rbr, SerialState), |
673 |
VMSTATE_UINT8(ier, SerialState), |
674 |
VMSTATE_UINT8(iir, SerialState), |
675 |
VMSTATE_UINT8(lcr, SerialState), |
676 |
VMSTATE_UINT8(mcr, SerialState), |
677 |
VMSTATE_UINT8(lsr, SerialState), |
678 |
VMSTATE_UINT8(msr, SerialState), |
679 |
VMSTATE_UINT8(scr, SerialState), |
680 |
VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
|
681 |
VMSTATE_END_OF_LIST() |
682 |
} |
683 |
}; |
684 |
|
685 |
static void serial_reset(void *opaque) |
686 |
{ |
687 |
SerialState *s = opaque; |
688 |
|
689 |
s->rbr = 0;
|
690 |
s->ier = 0;
|
691 |
s->iir = UART_IIR_NO_INT; |
692 |
s->lcr = 0;
|
693 |
s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
694 |
s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; |
695 |
/* Default to 9600 baud, no parity, one stop bit */
|
696 |
s->divider = 0x0C;
|
697 |
s->mcr = UART_MCR_OUT2; |
698 |
s->scr = 0;
|
699 |
s->tsr_retry = 0;
|
700 |
s->char_transmit_time = (get_ticks_per_sec() / 9600) * 9; |
701 |
s->poll_msl = 0;
|
702 |
|
703 |
fifo_clear(s,RECV_FIFO); |
704 |
fifo_clear(s,XMIT_FIFO); |
705 |
|
706 |
s->last_xmit_ts = qemu_get_clock(vm_clock); |
707 |
|
708 |
s->thr_ipending = 0;
|
709 |
s->last_break_enable = 0;
|
710 |
qemu_irq_lower(s->irq); |
711 |
} |
712 |
|
713 |
static void serial_init_core(SerialState *s) |
714 |
{ |
715 |
if (!s->chr) {
|
716 |
fprintf(stderr, "Can't create serial device, empty char device\n");
|
717 |
exit(1);
|
718 |
} |
719 |
|
720 |
s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s); |
721 |
|
722 |
s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s); |
723 |
s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s); |
724 |
|
725 |
qemu_register_reset(serial_reset, s); |
726 |
serial_reset(s); |
727 |
|
728 |
qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, |
729 |
serial_event, s); |
730 |
} |
731 |
|
732 |
static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
733 |
static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
734 |
|
735 |
static int serial_isa_initfn(ISADevice *dev) |
736 |
{ |
737 |
static int index; |
738 |
ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev); |
739 |
SerialState *s = &isa->state; |
740 |
|
741 |
if (isa->index == -1) |
742 |
isa->index = index; |
743 |
if (isa->index >= MAX_SERIAL_PORTS)
|
744 |
return -1; |
745 |
if (isa->iobase == -1) |
746 |
isa->iobase = isa_serial_io[isa->index]; |
747 |
if (isa->isairq == -1) |
748 |
isa->isairq = isa_serial_irq[isa->index]; |
749 |
index++; |
750 |
|
751 |
s->baudbase = 115200;
|
752 |
isa_init_irq(dev, &s->irq, isa->isairq); |
753 |
serial_init_core(s); |
754 |
vmstate_register(isa->iobase, &vmstate_serial, s); |
755 |
|
756 |
register_ioport_write(isa->iobase, 8, 1, serial_ioport_write, s); |
757 |
register_ioport_read(isa->iobase, 8, 1, serial_ioport_read, s); |
758 |
return 0; |
759 |
} |
760 |
|
761 |
SerialState *serial_isa_init(int index, CharDriverState *chr)
|
762 |
{ |
763 |
ISADevice *dev; |
764 |
|
765 |
dev = isa_create("isa-serial");
|
766 |
qdev_prop_set_uint32(&dev->qdev, "index", index);
|
767 |
qdev_prop_set_chr(&dev->qdev, "chardev", chr);
|
768 |
if (qdev_init(&dev->qdev) < 0) |
769 |
return NULL; |
770 |
return &DO_UPCAST(ISASerialState, dev, dev)->state;
|
771 |
} |
772 |
|
773 |
SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
774 |
CharDriverState *chr) |
775 |
{ |
776 |
SerialState *s; |
777 |
|
778 |
s = qemu_mallocz(sizeof(SerialState));
|
779 |
|
780 |
s->irq = irq; |
781 |
s->baudbase = baudbase; |
782 |
s->chr = chr; |
783 |
serial_init_core(s); |
784 |
|
785 |
vmstate_register(base, &vmstate_serial, s); |
786 |
|
787 |
register_ioport_write(base, 8, 1, serial_ioport_write, s); |
788 |
register_ioport_read(base, 8, 1, serial_ioport_read, s); |
789 |
return s;
|
790 |
} |
791 |
|
792 |
/* Memory mapped interface */
|
793 |
static uint32_t serial_mm_readb(void *opaque, target_phys_addr_t addr) |
794 |
{ |
795 |
SerialState *s = opaque; |
796 |
|
797 |
return serial_ioport_read(s, addr >> s->it_shift) & 0xFF; |
798 |
} |
799 |
|
800 |
static void serial_mm_writeb(void *opaque, target_phys_addr_t addr, |
801 |
uint32_t value) |
802 |
{ |
803 |
SerialState *s = opaque; |
804 |
|
805 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
|
806 |
} |
807 |
|
808 |
static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr) |
809 |
{ |
810 |
SerialState *s = opaque; |
811 |
uint32_t val; |
812 |
|
813 |
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
|
814 |
#ifdef TARGET_WORDS_BIGENDIAN
|
815 |
val = bswap16(val); |
816 |
#endif
|
817 |
return val;
|
818 |
} |
819 |
|
820 |
static void serial_mm_writew(void *opaque, target_phys_addr_t addr, |
821 |
uint32_t value) |
822 |
{ |
823 |
SerialState *s = opaque; |
824 |
#ifdef TARGET_WORDS_BIGENDIAN
|
825 |
value = bswap16(value); |
826 |
#endif
|
827 |
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
|
828 |
} |
829 |
|
830 |
static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr) |
831 |
{ |
832 |
SerialState *s = opaque; |
833 |
uint32_t val; |
834 |
|
835 |
val = serial_ioport_read(s, addr >> s->it_shift); |
836 |
#ifdef TARGET_WORDS_BIGENDIAN
|
837 |
val = bswap32(val); |
838 |
#endif
|
839 |
return val;
|
840 |
} |
841 |
|
842 |
static void serial_mm_writel(void *opaque, target_phys_addr_t addr, |
843 |
uint32_t value) |
844 |
{ |
845 |
SerialState *s = opaque; |
846 |
#ifdef TARGET_WORDS_BIGENDIAN
|
847 |
value = bswap32(value); |
848 |
#endif
|
849 |
serial_ioport_write(s, addr >> s->it_shift, value); |
850 |
} |
851 |
|
852 |
static CPUReadMemoryFunc * const serial_mm_read[] = { |
853 |
&serial_mm_readb, |
854 |
&serial_mm_readw, |
855 |
&serial_mm_readl, |
856 |
}; |
857 |
|
858 |
static CPUWriteMemoryFunc * const serial_mm_write[] = { |
859 |
&serial_mm_writeb, |
860 |
&serial_mm_writew, |
861 |
&serial_mm_writel, |
862 |
}; |
863 |
|
864 |
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
865 |
qemu_irq irq, int baudbase,
|
866 |
CharDriverState *chr, int ioregister)
|
867 |
{ |
868 |
SerialState *s; |
869 |
int s_io_memory;
|
870 |
|
871 |
s = qemu_mallocz(sizeof(SerialState));
|
872 |
|
873 |
s->it_shift = it_shift; |
874 |
s->irq = irq; |
875 |
s->baudbase = baudbase; |
876 |
s->chr = chr; |
877 |
|
878 |
serial_init_core(s); |
879 |
vmstate_register(base, &vmstate_serial, s); |
880 |
|
881 |
if (ioregister) {
|
882 |
s_io_memory = cpu_register_io_memory(serial_mm_read, |
883 |
serial_mm_write, s); |
884 |
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
|
885 |
} |
886 |
serial_update_msl(s); |
887 |
return s;
|
888 |
} |
889 |
|
890 |
static ISADeviceInfo serial_isa_info = {
|
891 |
.qdev.name = "isa-serial",
|
892 |
.qdev.size = sizeof(ISASerialState),
|
893 |
.init = serial_isa_initfn, |
894 |
.qdev.props = (Property[]) { |
895 |
DEFINE_PROP_HEX32("index", ISASerialState, index, -1), |
896 |
DEFINE_PROP_HEX32("iobase", ISASerialState, iobase, -1), |
897 |
DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1), |
898 |
DEFINE_PROP_CHR("chardev", ISASerialState, state.chr),
|
899 |
DEFINE_PROP_END_OF_LIST(), |
900 |
}, |
901 |
}; |
902 |
|
903 |
static void serial_register_devices(void) |
904 |
{ |
905 |
isa_qdev_register(&serial_isa_info); |
906 |
} |
907 |
|
908 |
device_init(serial_register_devices) |