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1 | 5a9fdfec | bellard | /*
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2 | 5a9fdfec | bellard | * defines common to all virtual CPUs
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3 | 5a9fdfec | bellard | *
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4 | 5a9fdfec | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 5a9fdfec | bellard | *
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6 | 5a9fdfec | bellard | * This library is free software; you can redistribute it and/or
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7 | 5a9fdfec | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 5a9fdfec | bellard | * License as published by the Free Software Foundation; either
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9 | 5a9fdfec | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 5a9fdfec | bellard | *
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11 | 5a9fdfec | bellard | * This library is distributed in the hope that it will be useful,
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12 | 5a9fdfec | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 5a9fdfec | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 5a9fdfec | bellard | * Lesser General Public License for more details.
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15 | 5a9fdfec | bellard | *
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16 | 5a9fdfec | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 5a9fdfec | bellard | * License along with this library; if not, write to the Free Software
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18 | 5a9fdfec | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 5a9fdfec | bellard | */
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20 | 5a9fdfec | bellard | #ifndef CPU_ALL_H
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21 | 5a9fdfec | bellard | #define CPU_ALL_H
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22 | 5a9fdfec | bellard | |
23 | 0ac4bd56 | bellard | #if defined(__arm__) || defined(__sparc__)
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24 | 0ac4bd56 | bellard | #define WORDS_ALIGNED
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25 | 0ac4bd56 | bellard | #endif
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26 | 0ac4bd56 | bellard | |
27 | 0ac4bd56 | bellard | /* some important defines:
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28 | 0ac4bd56 | bellard | *
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29 | 0ac4bd56 | bellard | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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30 | 0ac4bd56 | bellard | * memory accesses.
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31 | 0ac4bd56 | bellard | *
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32 | 0ac4bd56 | bellard | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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33 | 0ac4bd56 | bellard | * otherwise little endian.
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34 | 0ac4bd56 | bellard | *
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35 | 0ac4bd56 | bellard | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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36 | 0ac4bd56 | bellard | *
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37 | 0ac4bd56 | bellard | * TARGET_WORDS_BIGENDIAN : same for target cpu
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38 | 0ac4bd56 | bellard | */
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39 | 0ac4bd56 | bellard | |
40 | f193c797 | bellard | #include "bswap.h" |
41 | f193c797 | bellard | |
42 | f193c797 | bellard | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
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43 | f193c797 | bellard | #define BSWAP_NEEDED
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44 | f193c797 | bellard | #endif
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45 | f193c797 | bellard | |
46 | f193c797 | bellard | #ifdef BSWAP_NEEDED
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47 | f193c797 | bellard | |
48 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
49 | f193c797 | bellard | { |
50 | f193c797 | bellard | return bswap16(s);
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51 | f193c797 | bellard | } |
52 | f193c797 | bellard | |
53 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
54 | f193c797 | bellard | { |
55 | f193c797 | bellard | return bswap32(s);
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56 | f193c797 | bellard | } |
57 | f193c797 | bellard | |
58 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
59 | f193c797 | bellard | { |
60 | f193c797 | bellard | return bswap64(s);
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61 | f193c797 | bellard | } |
62 | f193c797 | bellard | |
63 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
64 | f193c797 | bellard | { |
65 | f193c797 | bellard | *s = bswap16(*s); |
66 | f193c797 | bellard | } |
67 | f193c797 | bellard | |
68 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
69 | f193c797 | bellard | { |
70 | f193c797 | bellard | *s = bswap32(*s); |
71 | f193c797 | bellard | } |
72 | f193c797 | bellard | |
73 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
74 | f193c797 | bellard | { |
75 | f193c797 | bellard | *s = bswap64(*s); |
76 | f193c797 | bellard | } |
77 | f193c797 | bellard | |
78 | f193c797 | bellard | #else
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79 | f193c797 | bellard | |
80 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
81 | f193c797 | bellard | { |
82 | f193c797 | bellard | return s;
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83 | f193c797 | bellard | } |
84 | f193c797 | bellard | |
85 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
86 | f193c797 | bellard | { |
87 | f193c797 | bellard | return s;
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88 | f193c797 | bellard | } |
89 | f193c797 | bellard | |
90 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
91 | f193c797 | bellard | { |
92 | f193c797 | bellard | return s;
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93 | f193c797 | bellard | } |
94 | f193c797 | bellard | |
95 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
96 | f193c797 | bellard | { |
97 | f193c797 | bellard | } |
98 | f193c797 | bellard | |
99 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
100 | f193c797 | bellard | { |
101 | f193c797 | bellard | } |
102 | f193c797 | bellard | |
103 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
104 | f193c797 | bellard | { |
105 | f193c797 | bellard | } |
106 | f193c797 | bellard | |
107 | f193c797 | bellard | #endif
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108 | f193c797 | bellard | |
109 | f193c797 | bellard | #if TARGET_LONG_SIZE == 4 |
110 | f193c797 | bellard | #define tswapl(s) tswap32(s)
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111 | f193c797 | bellard | #define tswapls(s) tswap32s((uint32_t *)(s))
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112 | 0a962c02 | bellard | #define bswaptls(s) bswap32s(s)
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113 | f193c797 | bellard | #else
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114 | f193c797 | bellard | #define tswapl(s) tswap64(s)
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115 | f193c797 | bellard | #define tswapls(s) tswap64s((uint64_t *)(s))
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116 | 0a962c02 | bellard | #define bswaptls(s) bswap64s(s)
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117 | f193c797 | bellard | #endif
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118 | f193c797 | bellard | |
119 | 832ed0fa | bellard | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
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120 | 832ed0fa | bellard | endian ! */
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121 | 0ac4bd56 | bellard | typedef union { |
122 | 0ac4bd56 | bellard | double d;
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123 | 832ed0fa | bellard | #if defined(WORDS_BIGENDIAN) || (defined(__arm__) && !defined(__VFP_FP__))
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124 | 0ac4bd56 | bellard | struct {
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125 | 0ac4bd56 | bellard | uint32_t upper; |
126 | 832ed0fa | bellard | uint32_t lower; |
127 | 0ac4bd56 | bellard | } l; |
128 | 0ac4bd56 | bellard | #else
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129 | 0ac4bd56 | bellard | struct {
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130 | 0ac4bd56 | bellard | uint32_t lower; |
131 | 832ed0fa | bellard | uint32_t upper; |
132 | 0ac4bd56 | bellard | } l; |
133 | 0ac4bd56 | bellard | #endif
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134 | 0ac4bd56 | bellard | uint64_t ll; |
135 | 0ac4bd56 | bellard | } CPU_DoubleU; |
136 | 0ac4bd56 | bellard | |
137 | 61382a50 | bellard | /* CPU memory access without any memory or io remapping */
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138 | 61382a50 | bellard | |
139 | 83d73968 | bellard | /*
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140 | 83d73968 | bellard | * the generic syntax for the memory accesses is:
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141 | 83d73968 | bellard | *
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142 | 83d73968 | bellard | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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143 | 83d73968 | bellard | *
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144 | 83d73968 | bellard | * store: st{type}{size}{endian}_{access_type}(ptr, val)
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145 | 83d73968 | bellard | *
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146 | 83d73968 | bellard | * type is:
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147 | 83d73968 | bellard | * (empty): integer access
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148 | 83d73968 | bellard | * f : float access
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149 | 83d73968 | bellard | *
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150 | 83d73968 | bellard | * sign is:
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151 | 83d73968 | bellard | * (empty): for floats or 32 bit size
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152 | 83d73968 | bellard | * u : unsigned
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153 | 83d73968 | bellard | * s : signed
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154 | 83d73968 | bellard | *
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155 | 83d73968 | bellard | * size is:
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156 | 83d73968 | bellard | * b: 8 bits
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157 | 83d73968 | bellard | * w: 16 bits
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158 | 83d73968 | bellard | * l: 32 bits
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159 | 83d73968 | bellard | * q: 64 bits
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160 | 83d73968 | bellard | *
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161 | 83d73968 | bellard | * endian is:
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162 | 83d73968 | bellard | * (empty): target cpu endianness or 8 bit access
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163 | 83d73968 | bellard | * r : reversed target cpu endianness (not implemented yet)
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164 | 83d73968 | bellard | * be : big endian (not implemented yet)
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165 | 83d73968 | bellard | * le : little endian (not implemented yet)
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166 | 83d73968 | bellard | *
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167 | 83d73968 | bellard | * access_type is:
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168 | 83d73968 | bellard | * raw : host memory access
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169 | 83d73968 | bellard | * user : user mode access using soft MMU
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170 | 83d73968 | bellard | * kernel : kernel mode access using soft MMU
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171 | 83d73968 | bellard | */
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172 | c27004ec | bellard | static inline int ldub_p(void *ptr) |
173 | 5a9fdfec | bellard | { |
174 | 5a9fdfec | bellard | return *(uint8_t *)ptr;
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175 | 5a9fdfec | bellard | } |
176 | 5a9fdfec | bellard | |
177 | c27004ec | bellard | static inline int ldsb_p(void *ptr) |
178 | 5a9fdfec | bellard | { |
179 | 5a9fdfec | bellard | return *(int8_t *)ptr;
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180 | 5a9fdfec | bellard | } |
181 | 5a9fdfec | bellard | |
182 | c27004ec | bellard | static inline void stb_p(void *ptr, int v) |
183 | 5a9fdfec | bellard | { |
184 | 5a9fdfec | bellard | *(uint8_t *)ptr = v; |
185 | 5a9fdfec | bellard | } |
186 | 5a9fdfec | bellard | |
187 | 5a9fdfec | bellard | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
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188 | 5a9fdfec | bellard | kernel handles unaligned load/stores may give better results, but
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189 | 5a9fdfec | bellard | it is a system wide setting : bad */
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190 | 0ac4bd56 | bellard | #if !defined(TARGET_WORDS_BIGENDIAN) && (defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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191 | 5a9fdfec | bellard | |
192 | 5a9fdfec | bellard | /* conservative code for little endian unaligned accesses */
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193 | c27004ec | bellard | static inline int lduw_p(void *ptr) |
194 | 5a9fdfec | bellard | { |
195 | 5a9fdfec | bellard | #ifdef __powerpc__
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196 | 5a9fdfec | bellard | int val;
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197 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
198 | 5a9fdfec | bellard | return val;
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199 | 5a9fdfec | bellard | #else
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200 | 5a9fdfec | bellard | uint8_t *p = ptr; |
201 | 5a9fdfec | bellard | return p[0] | (p[1] << 8); |
202 | 5a9fdfec | bellard | #endif
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203 | 5a9fdfec | bellard | } |
204 | 5a9fdfec | bellard | |
205 | c27004ec | bellard | static inline int ldsw_p(void *ptr) |
206 | 5a9fdfec | bellard | { |
207 | 5a9fdfec | bellard | #ifdef __powerpc__
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208 | 5a9fdfec | bellard | int val;
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209 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
210 | 5a9fdfec | bellard | return (int16_t)val;
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211 | 5a9fdfec | bellard | #else
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212 | 5a9fdfec | bellard | uint8_t *p = ptr; |
213 | 5a9fdfec | bellard | return (int16_t)(p[0] | (p[1] << 8)); |
214 | 5a9fdfec | bellard | #endif
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215 | 5a9fdfec | bellard | } |
216 | 5a9fdfec | bellard | |
217 | c27004ec | bellard | static inline int ldl_p(void *ptr) |
218 | 5a9fdfec | bellard | { |
219 | 5a9fdfec | bellard | #ifdef __powerpc__
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220 | 5a9fdfec | bellard | int val;
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221 | 5a9fdfec | bellard | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
222 | 5a9fdfec | bellard | return val;
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223 | 5a9fdfec | bellard | #else
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224 | 5a9fdfec | bellard | uint8_t *p = ptr; |
225 | 5a9fdfec | bellard | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
226 | 5a9fdfec | bellard | #endif
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227 | 5a9fdfec | bellard | } |
228 | 5a9fdfec | bellard | |
229 | c27004ec | bellard | static inline uint64_t ldq_p(void *ptr) |
230 | 5a9fdfec | bellard | { |
231 | 5a9fdfec | bellard | uint8_t *p = ptr; |
232 | 5a9fdfec | bellard | uint32_t v1, v2; |
233 | c27004ec | bellard | v1 = ldl_p(p); |
234 | c27004ec | bellard | v2 = ldl_p(p + 4);
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235 | 5a9fdfec | bellard | return v1 | ((uint64_t)v2 << 32); |
236 | 5a9fdfec | bellard | } |
237 | 5a9fdfec | bellard | |
238 | c27004ec | bellard | static inline void stw_p(void *ptr, int v) |
239 | 5a9fdfec | bellard | { |
240 | 5a9fdfec | bellard | #ifdef __powerpc__
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241 | 5a9fdfec | bellard | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
242 | 5a9fdfec | bellard | #else
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243 | 5a9fdfec | bellard | uint8_t *p = ptr; |
244 | 5a9fdfec | bellard | p[0] = v;
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245 | 5a9fdfec | bellard | p[1] = v >> 8; |
246 | 5a9fdfec | bellard | #endif
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247 | 5a9fdfec | bellard | } |
248 | 5a9fdfec | bellard | |
249 | c27004ec | bellard | static inline void stl_p(void *ptr, int v) |
250 | 5a9fdfec | bellard | { |
251 | 5a9fdfec | bellard | #ifdef __powerpc__
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252 | 5a9fdfec | bellard | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
253 | 5a9fdfec | bellard | #else
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254 | 5a9fdfec | bellard | uint8_t *p = ptr; |
255 | 5a9fdfec | bellard | p[0] = v;
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256 | 5a9fdfec | bellard | p[1] = v >> 8; |
257 | 5a9fdfec | bellard | p[2] = v >> 16; |
258 | 5a9fdfec | bellard | p[3] = v >> 24; |
259 | 5a9fdfec | bellard | #endif
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260 | 5a9fdfec | bellard | } |
261 | 5a9fdfec | bellard | |
262 | c27004ec | bellard | static inline void stq_p(void *ptr, uint64_t v) |
263 | 5a9fdfec | bellard | { |
264 | 5a9fdfec | bellard | uint8_t *p = ptr; |
265 | c27004ec | bellard | stl_p(p, (uint32_t)v); |
266 | c27004ec | bellard | stl_p(p + 4, v >> 32); |
267 | 5a9fdfec | bellard | } |
268 | 5a9fdfec | bellard | |
269 | 5a9fdfec | bellard | /* float access */
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270 | 5a9fdfec | bellard | |
271 | c27004ec | bellard | static inline float ldfl_p(void *ptr) |
272 | 5a9fdfec | bellard | { |
273 | 5a9fdfec | bellard | union {
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274 | 5a9fdfec | bellard | float f;
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275 | 5a9fdfec | bellard | uint32_t i; |
276 | 5a9fdfec | bellard | } u; |
277 | c27004ec | bellard | u.i = ldl_p(ptr); |
278 | 5a9fdfec | bellard | return u.f;
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279 | 5a9fdfec | bellard | } |
280 | 5a9fdfec | bellard | |
281 | c27004ec | bellard | static inline void stfl_p(void *ptr, float v) |
282 | 5a9fdfec | bellard | { |
283 | 5a9fdfec | bellard | union {
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284 | 5a9fdfec | bellard | float f;
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285 | 5a9fdfec | bellard | uint32_t i; |
286 | 5a9fdfec | bellard | } u; |
287 | 5a9fdfec | bellard | u.f = v; |
288 | c27004ec | bellard | stl_p(ptr, u.i); |
289 | 5a9fdfec | bellard | } |
290 | 5a9fdfec | bellard | |
291 | c27004ec | bellard | static inline double ldfq_p(void *ptr) |
292 | 5a9fdfec | bellard | { |
293 | 0ac4bd56 | bellard | CPU_DoubleU u; |
294 | c27004ec | bellard | u.l.lower = ldl_p(ptr); |
295 | c27004ec | bellard | u.l.upper = ldl_p(ptr + 4);
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296 | 5a9fdfec | bellard | return u.d;
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297 | 5a9fdfec | bellard | } |
298 | 5a9fdfec | bellard | |
299 | c27004ec | bellard | static inline void stfq_p(void *ptr, double v) |
300 | 5a9fdfec | bellard | { |
301 | 0ac4bd56 | bellard | CPU_DoubleU u; |
302 | 5a9fdfec | bellard | u.d = v; |
303 | c27004ec | bellard | stl_p(ptr, u.l.lower); |
304 | c27004ec | bellard | stl_p(ptr + 4, u.l.upper);
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305 | 5a9fdfec | bellard | } |
306 | 5a9fdfec | bellard | |
307 | 0ac4bd56 | bellard | #elif defined(TARGET_WORDS_BIGENDIAN) && (!defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
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308 | 93ac68bc | bellard | |
309 | c27004ec | bellard | static inline int lduw_p(void *ptr) |
310 | 93ac68bc | bellard | { |
311 | 83d73968 | bellard | #if defined(__i386__)
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312 | 83d73968 | bellard | int val;
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313 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
314 | 83d73968 | bellard | "xchgb %b0, %h0\n"
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315 | 83d73968 | bellard | : "=q" (val)
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316 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
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317 | 83d73968 | bellard | return val;
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318 | 83d73968 | bellard | #else
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319 | 93ac68bc | bellard | uint8_t *b = (uint8_t *) ptr; |
320 | 83d73968 | bellard | return ((b[0] << 8) | b[1]); |
321 | 83d73968 | bellard | #endif
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322 | 93ac68bc | bellard | } |
323 | 93ac68bc | bellard | |
324 | c27004ec | bellard | static inline int ldsw_p(void *ptr) |
325 | 93ac68bc | bellard | { |
326 | 83d73968 | bellard | #if defined(__i386__)
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327 | 83d73968 | bellard | int val;
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328 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
329 | 83d73968 | bellard | "xchgb %b0, %h0\n"
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330 | 83d73968 | bellard | : "=q" (val)
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331 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
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332 | 83d73968 | bellard | return (int16_t)val;
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333 | 83d73968 | bellard | #else
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334 | 83d73968 | bellard | uint8_t *b = (uint8_t *) ptr; |
335 | 83d73968 | bellard | return (int16_t)((b[0] << 8) | b[1]); |
336 | 83d73968 | bellard | #endif
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337 | 93ac68bc | bellard | } |
338 | 93ac68bc | bellard | |
339 | c27004ec | bellard | static inline int ldl_p(void *ptr) |
340 | 93ac68bc | bellard | { |
341 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
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342 | 83d73968 | bellard | int val;
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343 | 83d73968 | bellard | asm volatile ("movl %1, %0\n" |
344 | 83d73968 | bellard | "bswap %0\n"
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345 | 83d73968 | bellard | : "=r" (val)
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346 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr));
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347 | 83d73968 | bellard | return val;
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348 | 83d73968 | bellard | #else
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349 | 93ac68bc | bellard | uint8_t *b = (uint8_t *) ptr; |
350 | 83d73968 | bellard | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
351 | 83d73968 | bellard | #endif
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352 | 93ac68bc | bellard | } |
353 | 93ac68bc | bellard | |
354 | c27004ec | bellard | static inline uint64_t ldq_p(void *ptr) |
355 | 93ac68bc | bellard | { |
356 | 93ac68bc | bellard | uint32_t a,b; |
357 | c27004ec | bellard | a = ldl_p(ptr); |
358 | c27004ec | bellard | b = ldl_p(ptr+4);
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359 | 93ac68bc | bellard | return (((uint64_t)a<<32)|b); |
360 | 93ac68bc | bellard | } |
361 | 93ac68bc | bellard | |
362 | c27004ec | bellard | static inline void stw_p(void *ptr, int v) |
363 | 93ac68bc | bellard | { |
364 | 83d73968 | bellard | #if defined(__i386__)
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365 | 83d73968 | bellard | asm volatile ("xchgb %b0, %h0\n" |
366 | 83d73968 | bellard | "movw %w0, %1\n"
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367 | 83d73968 | bellard | : "=q" (v)
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368 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr), "0" (v)); |
369 | 83d73968 | bellard | #else
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370 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
371 | 93ac68bc | bellard | d[0] = v >> 8; |
372 | 93ac68bc | bellard | d[1] = v;
|
373 | 83d73968 | bellard | #endif
|
374 | 93ac68bc | bellard | } |
375 | 93ac68bc | bellard | |
376 | c27004ec | bellard | static inline void stl_p(void *ptr, int v) |
377 | 93ac68bc | bellard | { |
378 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
379 | 83d73968 | bellard | asm volatile ("bswap %0\n" |
380 | 83d73968 | bellard | "movl %0, %1\n"
|
381 | 83d73968 | bellard | : "=r" (v)
|
382 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr), "0" (v)); |
383 | 83d73968 | bellard | #else
|
384 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
385 | 93ac68bc | bellard | d[0] = v >> 24; |
386 | 93ac68bc | bellard | d[1] = v >> 16; |
387 | 93ac68bc | bellard | d[2] = v >> 8; |
388 | 93ac68bc | bellard | d[3] = v;
|
389 | 83d73968 | bellard | #endif
|
390 | 93ac68bc | bellard | } |
391 | 93ac68bc | bellard | |
392 | c27004ec | bellard | static inline void stq_p(void *ptr, uint64_t v) |
393 | 93ac68bc | bellard | { |
394 | c27004ec | bellard | stl_p(ptr, v >> 32);
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395 | c27004ec | bellard | stl_p(ptr + 4, v);
|
396 | 0ac4bd56 | bellard | } |
397 | 0ac4bd56 | bellard | |
398 | 0ac4bd56 | bellard | /* float access */
|
399 | 0ac4bd56 | bellard | |
400 | c27004ec | bellard | static inline float ldfl_p(void *ptr) |
401 | 0ac4bd56 | bellard | { |
402 | 0ac4bd56 | bellard | union {
|
403 | 0ac4bd56 | bellard | float f;
|
404 | 0ac4bd56 | bellard | uint32_t i; |
405 | 0ac4bd56 | bellard | } u; |
406 | c27004ec | bellard | u.i = ldl_p(ptr); |
407 | 0ac4bd56 | bellard | return u.f;
|
408 | 0ac4bd56 | bellard | } |
409 | 0ac4bd56 | bellard | |
410 | c27004ec | bellard | static inline void stfl_p(void *ptr, float v) |
411 | 0ac4bd56 | bellard | { |
412 | 0ac4bd56 | bellard | union {
|
413 | 0ac4bd56 | bellard | float f;
|
414 | 0ac4bd56 | bellard | uint32_t i; |
415 | 0ac4bd56 | bellard | } u; |
416 | 0ac4bd56 | bellard | u.f = v; |
417 | c27004ec | bellard | stl_p(ptr, u.i); |
418 | 0ac4bd56 | bellard | } |
419 | 0ac4bd56 | bellard | |
420 | c27004ec | bellard | static inline double ldfq_p(void *ptr) |
421 | 0ac4bd56 | bellard | { |
422 | 0ac4bd56 | bellard | CPU_DoubleU u; |
423 | c27004ec | bellard | u.l.upper = ldl_p(ptr); |
424 | c27004ec | bellard | u.l.lower = ldl_p(ptr + 4);
|
425 | 0ac4bd56 | bellard | return u.d;
|
426 | 0ac4bd56 | bellard | } |
427 | 0ac4bd56 | bellard | |
428 | c27004ec | bellard | static inline void stfq_p(void *ptr, double v) |
429 | 0ac4bd56 | bellard | { |
430 | 0ac4bd56 | bellard | CPU_DoubleU u; |
431 | 0ac4bd56 | bellard | u.d = v; |
432 | c27004ec | bellard | stl_p(ptr, u.l.upper); |
433 | c27004ec | bellard | stl_p(ptr + 4, u.l.lower);
|
434 | 93ac68bc | bellard | } |
435 | 93ac68bc | bellard | |
436 | 5a9fdfec | bellard | #else
|
437 | 5a9fdfec | bellard | |
438 | c27004ec | bellard | static inline int lduw_p(void *ptr) |
439 | 5a9fdfec | bellard | { |
440 | 5a9fdfec | bellard | return *(uint16_t *)ptr;
|
441 | 5a9fdfec | bellard | } |
442 | 5a9fdfec | bellard | |
443 | c27004ec | bellard | static inline int ldsw_p(void *ptr) |
444 | 5a9fdfec | bellard | { |
445 | 5a9fdfec | bellard | return *(int16_t *)ptr;
|
446 | 5a9fdfec | bellard | } |
447 | 5a9fdfec | bellard | |
448 | c27004ec | bellard | static inline int ldl_p(void *ptr) |
449 | 5a9fdfec | bellard | { |
450 | 5a9fdfec | bellard | return *(uint32_t *)ptr;
|
451 | 5a9fdfec | bellard | } |
452 | 5a9fdfec | bellard | |
453 | c27004ec | bellard | static inline uint64_t ldq_p(void *ptr) |
454 | 5a9fdfec | bellard | { |
455 | 5a9fdfec | bellard | return *(uint64_t *)ptr;
|
456 | 5a9fdfec | bellard | } |
457 | 5a9fdfec | bellard | |
458 | c27004ec | bellard | static inline void stw_p(void *ptr, int v) |
459 | 5a9fdfec | bellard | { |
460 | 5a9fdfec | bellard | *(uint16_t *)ptr = v; |
461 | 5a9fdfec | bellard | } |
462 | 5a9fdfec | bellard | |
463 | c27004ec | bellard | static inline void stl_p(void *ptr, int v) |
464 | 5a9fdfec | bellard | { |
465 | 5a9fdfec | bellard | *(uint32_t *)ptr = v; |
466 | 5a9fdfec | bellard | } |
467 | 5a9fdfec | bellard | |
468 | c27004ec | bellard | static inline void stq_p(void *ptr, uint64_t v) |
469 | 5a9fdfec | bellard | { |
470 | 5a9fdfec | bellard | *(uint64_t *)ptr = v; |
471 | 5a9fdfec | bellard | } |
472 | 5a9fdfec | bellard | |
473 | 5a9fdfec | bellard | /* float access */
|
474 | 5a9fdfec | bellard | |
475 | c27004ec | bellard | static inline float ldfl_p(void *ptr) |
476 | 5a9fdfec | bellard | { |
477 | 5a9fdfec | bellard | return *(float *)ptr; |
478 | 5a9fdfec | bellard | } |
479 | 5a9fdfec | bellard | |
480 | c27004ec | bellard | static inline double ldfq_p(void *ptr) |
481 | 5a9fdfec | bellard | { |
482 | 5a9fdfec | bellard | return *(double *)ptr; |
483 | 5a9fdfec | bellard | } |
484 | 5a9fdfec | bellard | |
485 | c27004ec | bellard | static inline void stfl_p(void *ptr, float v) |
486 | 5a9fdfec | bellard | { |
487 | 5a9fdfec | bellard | *(float *)ptr = v;
|
488 | 5a9fdfec | bellard | } |
489 | 5a9fdfec | bellard | |
490 | c27004ec | bellard | static inline void stfq_p(void *ptr, double v) |
491 | 5a9fdfec | bellard | { |
492 | 5a9fdfec | bellard | *(double *)ptr = v;
|
493 | 5a9fdfec | bellard | } |
494 | 5a9fdfec | bellard | #endif
|
495 | 5a9fdfec | bellard | |
496 | 61382a50 | bellard | /* MMU memory access macros */
|
497 | 61382a50 | bellard | |
498 | c27004ec | bellard | /* NOTE: we use double casts if pointers and target_ulong have
|
499 | c27004ec | bellard | different sizes */
|
500 | c27004ec | bellard | #define ldub_raw(p) ldub_p((uint8_t *)(long)(p)) |
501 | c27004ec | bellard | #define ldsb_raw(p) ldsb_p((uint8_t *)(long)(p)) |
502 | c27004ec | bellard | #define lduw_raw(p) lduw_p((uint8_t *)(long)(p)) |
503 | c27004ec | bellard | #define ldsw_raw(p) ldsw_p((uint8_t *)(long)(p)) |
504 | c27004ec | bellard | #define ldl_raw(p) ldl_p((uint8_t *)(long)(p)) |
505 | c27004ec | bellard | #define ldq_raw(p) ldq_p((uint8_t *)(long)(p)) |
506 | c27004ec | bellard | #define ldfl_raw(p) ldfl_p((uint8_t *)(long)(p)) |
507 | c27004ec | bellard | #define ldfq_raw(p) ldfq_p((uint8_t *)(long)(p)) |
508 | c27004ec | bellard | #define stb_raw(p, v) stb_p((uint8_t *)(long)(p), v) |
509 | c27004ec | bellard | #define stw_raw(p, v) stw_p((uint8_t *)(long)(p), v) |
510 | c27004ec | bellard | #define stl_raw(p, v) stl_p((uint8_t *)(long)(p), v) |
511 | c27004ec | bellard | #define stq_raw(p, v) stq_p((uint8_t *)(long)(p), v) |
512 | c27004ec | bellard | #define stfl_raw(p, v) stfl_p((uint8_t *)(long)(p), v) |
513 | c27004ec | bellard | #define stfq_raw(p, v) stfq_p((uint8_t *)(long)(p), v) |
514 | c27004ec | bellard | |
515 | c27004ec | bellard | |
516 | 61382a50 | bellard | #if defined(CONFIG_USER_ONLY)
|
517 | 61382a50 | bellard | |
518 | 61382a50 | bellard | /* if user mode, no other memory access functions */
|
519 | 61382a50 | bellard | #define ldub(p) ldub_raw(p)
|
520 | 61382a50 | bellard | #define ldsb(p) ldsb_raw(p)
|
521 | 61382a50 | bellard | #define lduw(p) lduw_raw(p)
|
522 | 61382a50 | bellard | #define ldsw(p) ldsw_raw(p)
|
523 | 61382a50 | bellard | #define ldl(p) ldl_raw(p)
|
524 | 61382a50 | bellard | #define ldq(p) ldq_raw(p)
|
525 | 61382a50 | bellard | #define ldfl(p) ldfl_raw(p)
|
526 | 61382a50 | bellard | #define ldfq(p) ldfq_raw(p)
|
527 | 61382a50 | bellard | #define stb(p, v) stb_raw(p, v)
|
528 | 61382a50 | bellard | #define stw(p, v) stw_raw(p, v)
|
529 | 61382a50 | bellard | #define stl(p, v) stl_raw(p, v)
|
530 | 61382a50 | bellard | #define stq(p, v) stq_raw(p, v)
|
531 | 61382a50 | bellard | #define stfl(p, v) stfl_raw(p, v)
|
532 | 61382a50 | bellard | #define stfq(p, v) stfq_raw(p, v)
|
533 | 61382a50 | bellard | |
534 | 61382a50 | bellard | #define ldub_code(p) ldub_raw(p)
|
535 | 61382a50 | bellard | #define ldsb_code(p) ldsb_raw(p)
|
536 | 61382a50 | bellard | #define lduw_code(p) lduw_raw(p)
|
537 | 61382a50 | bellard | #define ldsw_code(p) ldsw_raw(p)
|
538 | 61382a50 | bellard | #define ldl_code(p) ldl_raw(p)
|
539 | 61382a50 | bellard | |
540 | 61382a50 | bellard | #define ldub_kernel(p) ldub_raw(p)
|
541 | 61382a50 | bellard | #define ldsb_kernel(p) ldsb_raw(p)
|
542 | 61382a50 | bellard | #define lduw_kernel(p) lduw_raw(p)
|
543 | 61382a50 | bellard | #define ldsw_kernel(p) ldsw_raw(p)
|
544 | 61382a50 | bellard | #define ldl_kernel(p) ldl_raw(p)
|
545 | 0ac4bd56 | bellard | #define ldfl_kernel(p) ldfl_raw(p)
|
546 | 0ac4bd56 | bellard | #define ldfq_kernel(p) ldfq_raw(p)
|
547 | 61382a50 | bellard | #define stb_kernel(p, v) stb_raw(p, v)
|
548 | 61382a50 | bellard | #define stw_kernel(p, v) stw_raw(p, v)
|
549 | 61382a50 | bellard | #define stl_kernel(p, v) stl_raw(p, v)
|
550 | 61382a50 | bellard | #define stq_kernel(p, v) stq_raw(p, v)
|
551 | 0ac4bd56 | bellard | #define stfl_kernel(p, v) stfl_raw(p, v)
|
552 | 0ac4bd56 | bellard | #define stfq_kernel(p, vt) stfq_raw(p, v)
|
553 | 61382a50 | bellard | |
554 | 61382a50 | bellard | #endif /* defined(CONFIG_USER_ONLY) */ |
555 | 61382a50 | bellard | |
556 | 5a9fdfec | bellard | /* page related stuff */
|
557 | 5a9fdfec | bellard | |
558 | 5a9fdfec | bellard | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
559 | 5a9fdfec | bellard | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
560 | 5a9fdfec | bellard | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
561 | 5a9fdfec | bellard | |
562 | 83fb7adf | bellard | extern unsigned long qemu_real_host_page_size; |
563 | 83fb7adf | bellard | extern unsigned long qemu_host_page_bits; |
564 | 83fb7adf | bellard | extern unsigned long qemu_host_page_size; |
565 | 83fb7adf | bellard | extern unsigned long qemu_host_page_mask; |
566 | 5a9fdfec | bellard | |
567 | 83fb7adf | bellard | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
568 | 5a9fdfec | bellard | |
569 | 5a9fdfec | bellard | /* same as PROT_xxx */
|
570 | 5a9fdfec | bellard | #define PAGE_READ 0x0001 |
571 | 5a9fdfec | bellard | #define PAGE_WRITE 0x0002 |
572 | 5a9fdfec | bellard | #define PAGE_EXEC 0x0004 |
573 | 5a9fdfec | bellard | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
574 | 5a9fdfec | bellard | #define PAGE_VALID 0x0008 |
575 | 5a9fdfec | bellard | /* original state of the write flag (used when tracking self-modifying
|
576 | 5a9fdfec | bellard | code */
|
577 | 5a9fdfec | bellard | #define PAGE_WRITE_ORG 0x0010 |
578 | 5a9fdfec | bellard | |
579 | 5a9fdfec | bellard | void page_dump(FILE *f);
|
580 | 5a9fdfec | bellard | int page_get_flags(unsigned long address); |
581 | 5a9fdfec | bellard | void page_set_flags(unsigned long start, unsigned long end, int flags); |
582 | 5a9fdfec | bellard | void page_unprotect_range(uint8_t *data, unsigned long data_size); |
583 | 5a9fdfec | bellard | |
584 | 5a9fdfec | bellard | #define SINGLE_CPU_DEFINES
|
585 | 5a9fdfec | bellard | #ifdef SINGLE_CPU_DEFINES
|
586 | 5a9fdfec | bellard | |
587 | 5a9fdfec | bellard | #if defined(TARGET_I386)
|
588 | 5a9fdfec | bellard | |
589 | 5a9fdfec | bellard | #define CPUState CPUX86State
|
590 | 5a9fdfec | bellard | #define cpu_init cpu_x86_init
|
591 | 5a9fdfec | bellard | #define cpu_exec cpu_x86_exec
|
592 | 5a9fdfec | bellard | #define cpu_gen_code cpu_x86_gen_code
|
593 | 5a9fdfec | bellard | #define cpu_signal_handler cpu_x86_signal_handler
|
594 | 5a9fdfec | bellard | |
595 | 5a9fdfec | bellard | #elif defined(TARGET_ARM)
|
596 | 5a9fdfec | bellard | |
597 | 5a9fdfec | bellard | #define CPUState CPUARMState
|
598 | 5a9fdfec | bellard | #define cpu_init cpu_arm_init
|
599 | 5a9fdfec | bellard | #define cpu_exec cpu_arm_exec
|
600 | 5a9fdfec | bellard | #define cpu_gen_code cpu_arm_gen_code
|
601 | 5a9fdfec | bellard | #define cpu_signal_handler cpu_arm_signal_handler
|
602 | 5a9fdfec | bellard | |
603 | 93ac68bc | bellard | #elif defined(TARGET_SPARC)
|
604 | 93ac68bc | bellard | |
605 | 93ac68bc | bellard | #define CPUState CPUSPARCState
|
606 | 93ac68bc | bellard | #define cpu_init cpu_sparc_init
|
607 | 93ac68bc | bellard | #define cpu_exec cpu_sparc_exec
|
608 | 93ac68bc | bellard | #define cpu_gen_code cpu_sparc_gen_code
|
609 | 93ac68bc | bellard | #define cpu_signal_handler cpu_sparc_signal_handler
|
610 | 93ac68bc | bellard | |
611 | 67867308 | bellard | #elif defined(TARGET_PPC)
|
612 | 67867308 | bellard | |
613 | 67867308 | bellard | #define CPUState CPUPPCState
|
614 | 67867308 | bellard | #define cpu_init cpu_ppc_init
|
615 | 67867308 | bellard | #define cpu_exec cpu_ppc_exec
|
616 | 67867308 | bellard | #define cpu_gen_code cpu_ppc_gen_code
|
617 | 67867308 | bellard | #define cpu_signal_handler cpu_ppc_signal_handler
|
618 | 67867308 | bellard | |
619 | 5a9fdfec | bellard | #else
|
620 | 5a9fdfec | bellard | |
621 | 5a9fdfec | bellard | #error unsupported target CPU
|
622 | 5a9fdfec | bellard | |
623 | 5a9fdfec | bellard | #endif
|
624 | 5a9fdfec | bellard | |
625 | 972ddf78 | bellard | #endif /* SINGLE_CPU_DEFINES */ |
626 | 972ddf78 | bellard | |
627 | 7fe48483 | bellard | void cpu_dump_state(CPUState *env, FILE *f,
|
628 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
629 | 7fe48483 | bellard | int flags);
|
630 | 7fe48483 | bellard | |
631 | 972ddf78 | bellard | void cpu_abort(CPUState *env, const char *fmt, ...); |
632 | e2f22898 | bellard | extern CPUState *cpu_single_env;
|
633 | 9acbed06 | bellard | extern int code_copy_enabled; |
634 | 5a9fdfec | bellard | |
635 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ |
636 | 9acbed06 | bellard | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
637 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
638 | ef792f9d | bellard | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
639 | 4690764b | bellard | void cpu_interrupt(CPUState *s, int mask); |
640 | b54ad049 | bellard | void cpu_reset_interrupt(CPUState *env, int mask); |
641 | 68a79315 | bellard | |
642 | 2e12669a | bellard | int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
|
643 | 2e12669a | bellard | int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
|
644 | c33a346e | bellard | void cpu_single_step(CPUState *env, int enabled); |
645 | d95dc32d | bellard | void cpu_reset(CPUState *s);
|
646 | 4c3a88a2 | bellard | |
647 | 13eb76e0 | bellard | /* Return the physical page corresponding to a virtual one. Use it
|
648 | 13eb76e0 | bellard | only for debugging because no protection checks are done. Return -1
|
649 | 13eb76e0 | bellard | if no page found. */
|
650 | 13eb76e0 | bellard | target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
651 | 13eb76e0 | bellard | |
652 | 9fddaa0c | bellard | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
653 | 9fddaa0c | bellard | #define CPU_LOG_TB_IN_ASM (1 << 1) |
654 | f193c797 | bellard | #define CPU_LOG_TB_OP (1 << 2) |
655 | f193c797 | bellard | #define CPU_LOG_TB_OP_OPT (1 << 3) |
656 | f193c797 | bellard | #define CPU_LOG_INT (1 << 4) |
657 | f193c797 | bellard | #define CPU_LOG_EXEC (1 << 5) |
658 | f193c797 | bellard | #define CPU_LOG_PCALL (1 << 6) |
659 | fd872598 | bellard | #define CPU_LOG_IOPORT (1 << 7) |
660 | 9fddaa0c | bellard | #define CPU_LOG_TB_CPU (1 << 8) |
661 | f193c797 | bellard | |
662 | f193c797 | bellard | /* define log items */
|
663 | f193c797 | bellard | typedef struct CPULogItem { |
664 | f193c797 | bellard | int mask;
|
665 | f193c797 | bellard | const char *name; |
666 | f193c797 | bellard | const char *help; |
667 | f193c797 | bellard | } CPULogItem; |
668 | f193c797 | bellard | |
669 | f193c797 | bellard | extern CPULogItem cpu_log_items[];
|
670 | f193c797 | bellard | |
671 | 34865134 | bellard | void cpu_set_log(int log_flags); |
672 | 34865134 | bellard | void cpu_set_log_filename(const char *filename); |
673 | f193c797 | bellard | int cpu_str_to_log_mask(const char *str); |
674 | 34865134 | bellard | |
675 | 09683d35 | bellard | /* IO ports API */
|
676 | 09683d35 | bellard | |
677 | 09683d35 | bellard | /* NOTE: as these functions may be even used when there is an isa
|
678 | 09683d35 | bellard | brige on non x86 targets, we always defined them */
|
679 | 09683d35 | bellard | #ifndef NO_CPU_IO_DEFS
|
680 | 09683d35 | bellard | void cpu_outb(CPUState *env, int addr, int val); |
681 | 09683d35 | bellard | void cpu_outw(CPUState *env, int addr, int val); |
682 | 09683d35 | bellard | void cpu_outl(CPUState *env, int addr, int val); |
683 | 09683d35 | bellard | int cpu_inb(CPUState *env, int addr); |
684 | 09683d35 | bellard | int cpu_inw(CPUState *env, int addr); |
685 | 09683d35 | bellard | int cpu_inl(CPUState *env, int addr); |
686 | 09683d35 | bellard | #endif
|
687 | 09683d35 | bellard | |
688 | 33417e70 | bellard | /* memory API */
|
689 | 33417e70 | bellard | |
690 | edf75d59 | bellard | extern int phys_ram_size; |
691 | edf75d59 | bellard | extern int phys_ram_fd; |
692 | edf75d59 | bellard | extern uint8_t *phys_ram_base;
|
693 | 1ccde1cb | bellard | extern uint8_t *phys_ram_dirty;
|
694 | edf75d59 | bellard | |
695 | edf75d59 | bellard | /* physical memory access */
|
696 | edf75d59 | bellard | #define IO_MEM_NB_ENTRIES 256 |
697 | edf75d59 | bellard | #define TLB_INVALID_MASK (1 << 3) |
698 | edf75d59 | bellard | #define IO_MEM_SHIFT 4 |
699 | edf75d59 | bellard | |
700 | edf75d59 | bellard | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ |
701 | edf75d59 | bellard | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ |
702 | edf75d59 | bellard | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) |
703 | 1ccde1cb | bellard | #define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */ |
704 | 1ccde1cb | bellard | #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ |
705 | edf75d59 | bellard | |
706 | 7727994d | bellard | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
707 | 7727994d | bellard | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
708 | 33417e70 | bellard | |
709 | 2e12669a | bellard | void cpu_register_physical_memory(target_phys_addr_t start_addr,
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710 | 2e12669a | bellard | unsigned long size, |
711 | 2e12669a | bellard | unsigned long phys_offset); |
712 | 33417e70 | bellard | int cpu_register_io_memory(int io_index, |
713 | 33417e70 | bellard | CPUReadMemoryFunc **mem_read, |
714 | 7727994d | bellard | CPUWriteMemoryFunc **mem_write, |
715 | 7727994d | bellard | void *opaque);
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716 | 8926b517 | bellard | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
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717 | 8926b517 | bellard | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
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718 | 33417e70 | bellard | |
719 | 2e12669a | bellard | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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720 | 13eb76e0 | bellard | int len, int is_write); |
721 | 2e12669a | bellard | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
722 | 2e12669a | bellard | uint8_t *buf, int len)
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723 | 8b1f24b0 | bellard | { |
724 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, buf, len, 0);
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725 | 8b1f24b0 | bellard | } |
726 | 2e12669a | bellard | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
727 | 2e12669a | bellard | const uint8_t *buf, int len) |
728 | 8b1f24b0 | bellard | { |
729 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
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730 | 8b1f24b0 | bellard | } |
731 | 8df1cd07 | bellard | uint32_t ldl_phys(target_phys_addr_t addr); |
732 | 8df1cd07 | bellard | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
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733 | 8df1cd07 | bellard | void stl_phys(target_phys_addr_t addr, uint32_t val);
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734 | 8b1f24b0 | bellard | |
735 | 8b1f24b0 | bellard | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
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736 | 8b1f24b0 | bellard | uint8_t *buf, int len, int is_write); |
737 | 13eb76e0 | bellard | |
738 | 0a962c02 | bellard | #define VGA_DIRTY_FLAG 0x01 |
739 | 0a962c02 | bellard | |
740 | 1ccde1cb | bellard | /* read dirty bit (return 0 or 1) */
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741 | 1ccde1cb | bellard | static inline int cpu_physical_memory_is_dirty(target_ulong addr) |
742 | 1ccde1cb | bellard | { |
743 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
744 | 0a962c02 | bellard | } |
745 | 0a962c02 | bellard | |
746 | 0a962c02 | bellard | static inline int cpu_physical_memory_get_dirty(target_ulong addr, |
747 | 0a962c02 | bellard | int dirty_flags)
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748 | 0a962c02 | bellard | { |
749 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
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750 | 1ccde1cb | bellard | } |
751 | 1ccde1cb | bellard | |
752 | 1ccde1cb | bellard | static inline void cpu_physical_memory_set_dirty(target_ulong addr) |
753 | 1ccde1cb | bellard | { |
754 | 0a962c02 | bellard | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
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755 | 1ccde1cb | bellard | } |
756 | 1ccde1cb | bellard | |
757 | 0a962c02 | bellard | void cpu_physical_memory_reset_dirty(target_ulong start, target_ulong end,
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758 | 0a962c02 | bellard | int dirty_flags);
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759 | 1ccde1cb | bellard | |
760 | e3db7226 | bellard | void dump_exec_info(FILE *f,
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761 | e3db7226 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
762 | e3db7226 | bellard | |
763 | 5a9fdfec | bellard | #endif /* CPU_ALL_H */ |