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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM virtual CPU header
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #ifndef CPU_ARM_H
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21 | 2c0262af | bellard | #define CPU_ARM_H
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22 | 2c0262af | bellard | |
23 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
24 | 3cf1e035 | bellard | |
25 | 2c0262af | bellard | #include "cpu-defs.h" |
26 | 2c0262af | bellard | |
27 | b8a9e8f1 | bellard | #define EXCP_UDEF 1 /* undefined instruction */ |
28 | b8a9e8f1 | bellard | #define EXCP_SWI 2 /* software interrupt */ |
29 | b8a9e8f1 | bellard | #define EXCP_PREFETCH_ABORT 3 |
30 | b8a9e8f1 | bellard | #define EXCP_DATA_ABORT 4 |
31 | 2c0262af | bellard | |
32 | b7bcbe95 | bellard | /* We currently assume float and double are IEEE single and double
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33 | b7bcbe95 | bellard | precision respectively.
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34 | b7bcbe95 | bellard | Doing runtime conversions is tricky because VFP registers may contain
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35 | b7bcbe95 | bellard | integer values (eg. as the result of a FTOSI instruction).
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36 | b7bcbe95 | bellard | A double precision register load/store must also load/store the
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37 | b7bcbe95 | bellard | corresponding single precision pair, although it is undefined how
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38 | b7bcbe95 | bellard | these overlap. */
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39 | b7bcbe95 | bellard | |
40 | 2c0262af | bellard | typedef struct CPUARMState { |
41 | 2c0262af | bellard | uint32_t regs[16];
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42 | 2c0262af | bellard | uint32_t cpsr; |
43 | 2c0262af | bellard | |
44 | 2c0262af | bellard | /* cpsr flag cache for faster execution */
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45 | 2c0262af | bellard | uint32_t CF; /* 0 or 1 */
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46 | 2c0262af | bellard | uint32_t VF; /* V is the bit 31. All other bits are undefined */
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47 | 2c0262af | bellard | uint32_t NZF; /* N is bit 31. Z is computed from NZF */
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48 | 99c475ab | bellard | uint32_t QF; /* 0 or 1 */
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49 | 99c475ab | bellard | |
50 | 99c475ab | bellard | int thumb; /* 0 = arm mode, 1 = thumb mode */ |
51 | 2c0262af | bellard | |
52 | b8a9e8f1 | bellard | /* coprocessor 15 (MMU) status */
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53 | b8a9e8f1 | bellard | uint32_t cp15_6; |
54 | b8a9e8f1 | bellard | |
55 | 2c0262af | bellard | /* exception/interrupt handling */
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56 | 2c0262af | bellard | jmp_buf jmp_env; |
57 | 2c0262af | bellard | int exception_index;
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58 | 2c0262af | bellard | int interrupt_request;
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59 | 2c0262af | bellard | struct TranslationBlock *current_tb;
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60 | 2c0262af | bellard | int user_mode_only;
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61 | b7bcbe95 | bellard | uint32_t address; |
62 | 2c0262af | bellard | |
63 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
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64 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
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65 | d720b93d | bellard | context) */
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66 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
67 | d720b93d | bellard | written */
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68 | d720b93d | bellard | unsigned long mem_write_vaddr; /* target virtual addr at which the |
69 | d720b93d | bellard | memory was written */
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70 | b7bcbe95 | bellard | /* VFP coprocessor state. */
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71 | b7bcbe95 | bellard | struct {
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72 | b7bcbe95 | bellard | union {
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73 | b7bcbe95 | bellard | float s[32]; |
74 | b7bcbe95 | bellard | double d[16]; |
75 | b7bcbe95 | bellard | } regs; |
76 | b7bcbe95 | bellard | |
77 | b7bcbe95 | bellard | /* We store these fpcsr fields separately for convenience. */
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78 | b7bcbe95 | bellard | int vec_len;
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79 | b7bcbe95 | bellard | int vec_stride;
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80 | b7bcbe95 | bellard | |
81 | b7bcbe95 | bellard | uint32_t fpscr; |
82 | b7bcbe95 | bellard | |
83 | b7bcbe95 | bellard | /* Temporary variables if we don't have spare fp regs. */
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84 | b7bcbe95 | bellard | float tmp0s, tmp1s;
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85 | b7bcbe95 | bellard | double tmp0d, tmp1d;
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86 | b7bcbe95 | bellard | |
87 | b7bcbe95 | bellard | } vfp; |
88 | b7bcbe95 | bellard | |
89 | 2c0262af | bellard | /* user data */
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90 | 2c0262af | bellard | void *opaque;
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91 | 2c0262af | bellard | } CPUARMState; |
92 | 2c0262af | bellard | |
93 | 2c0262af | bellard | CPUARMState *cpu_arm_init(void);
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94 | 2c0262af | bellard | int cpu_arm_exec(CPUARMState *s);
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95 | 2c0262af | bellard | void cpu_arm_close(CPUARMState *s);
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96 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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97 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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98 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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99 | 2c0262af | bellard | struct siginfo;
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100 | 2c0262af | bellard | int cpu_arm_signal_handler(int host_signum, struct siginfo *info, |
101 | 2c0262af | bellard | void *puc);
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102 | 2c0262af | bellard | |
103 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
104 | 2c0262af | bellard | #include "cpu-all.h" |
105 | 2c0262af | bellard | |
106 | 2c0262af | bellard | #endif |