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/*
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 *  ARM micro operations
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 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *  Copyright (c) 2005 CodeSourcery, LLC
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "exec.h"
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#define REGNAME r0
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#define REG (env->regs[0])
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#include "op_template.h"
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#define REGNAME r1
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#define REG (env->regs[1])
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#include "op_template.h"
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#define REGNAME r2
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#define REG (env->regs[2])
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#include "op_template.h"
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#define REGNAME r3
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#define REG (env->regs[3])
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#include "op_template.h"
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#define REGNAME r4
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#define REG (env->regs[4])
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#include "op_template.h"
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#define REGNAME r5
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#define REG (env->regs[5])
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#include "op_template.h"
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#define REGNAME r6
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#define REG (env->regs[6])
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#include "op_template.h"
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#define REGNAME r7
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#define REG (env->regs[7])
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#include "op_template.h"
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#define REGNAME r8
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#define REG (env->regs[8])
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#include "op_template.h"
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#define REGNAME r9
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#define REG (env->regs[9])
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#include "op_template.h"
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#define REGNAME r10
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#define REG (env->regs[10])
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#include "op_template.h"
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#define REGNAME r11
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#define REG (env->regs[11])
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#include "op_template.h"
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#define REGNAME r12
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#define REG (env->regs[12])
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#include "op_template.h"
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#define REGNAME r13
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#define REG (env->regs[13])
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#include "op_template.h"
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#define REGNAME r14
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#define REG (env->regs[14])
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#include "op_template.h"
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#define REGNAME r15
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#define REG (env->regs[15])
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#define SET_REG(x) REG = x & ~(uint32_t)1
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#include "op_template.h"
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void OPPROTO op_bx_T0(void)
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{
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  env->regs[15] = T0 & ~(uint32_t)1;
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  env->thumb = (T0 & 1) != 0;
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}
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void OPPROTO op_movl_T0_0(void)
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{
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    T0 = 0;
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}
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void OPPROTO op_movl_T0_im(void)
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{
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    T0 = PARAM1;
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}
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void OPPROTO op_movl_T1_im(void)
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{
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    T1 = PARAM1;
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}
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void OPPROTO op_mov_CF_T1(void)
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{
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    env->CF = ((uint32_t)T1) >> 31;
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}
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void OPPROTO op_movl_T2_im(void)
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{
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    T2 = PARAM1;
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}
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void OPPROTO op_addl_T1_im(void)
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{
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    T1 += PARAM1;
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}
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void OPPROTO op_addl_T1_T2(void)
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{
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    T1 += T2;
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}
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void OPPROTO op_subl_T1_T2(void)
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{
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    T1 -= T2;
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}
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void OPPROTO op_addl_T0_T1(void)
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{
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    T0 += T1;
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}
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void OPPROTO op_addl_T0_T1_cc(void)
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{
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    unsigned int src1;
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    src1 = T0;
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    T0 += T1;
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    env->NZF = T0;
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    env->CF = T0 < src1;
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    env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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}
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void OPPROTO op_adcl_T0_T1(void)
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{
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    T0 += T1 + env->CF;
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}
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void OPPROTO op_adcl_T0_T1_cc(void)
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{
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    unsigned int src1;
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    src1 = T0;
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    if (!env->CF) {
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        T0 += T1;
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        env->CF = T0 < src1;
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    } else {
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        T0 += T1 + 1;
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        env->CF = T0 <= src1;
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    }
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    env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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    env->NZF = T0;
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    FORCE_RET();
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}
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#define OPSUB(sub, sbc, res, T0, T1)            \
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                                                \
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void OPPROTO op_ ## sub ## l_T0_T1(void)        \
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{                                               \
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    res = T0 - T1;                              \
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}                                               \
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                                                \
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void)     \
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{                                               \
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    unsigned int src1;                          \
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    src1 = T0;                                  \
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    T0 -= T1;                                   \
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    env->NZF = T0;                              \
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    env->CF = src1 >= T1;                       \
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    env->VF = (src1 ^ T1) & (src1 ^ T0);        \
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    res = T0;                                   \
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}                                               \
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                                                \
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void OPPROTO op_ ## sbc ## l_T0_T1(void)        \
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{                                               \
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    res = T0 - T1 + env->CF - 1;                \
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}                                               \
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                                                \
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void)     \
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{                                               \
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    unsigned int src1;                          \
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    src1 = T0;                                  \
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    if (!env->CF) {                             \
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        T0 = T0 - T1 - 1;                       \
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        env->CF = src1 > T1;                    \
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    } else {                                    \
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        T0 = T0 - T1;                           \
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        env->CF = src1 >= T1;                   \
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    }                                           \
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    env->VF = (src1 ^ T1) & (src1 ^ T0);        \
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    env->NZF = T0;                              \
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    res = T0;                                   \
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    FORCE_RET();                                \
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}
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OPSUB(sub, sbc, T0, T0, T1)
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OPSUB(rsb, rsc, T0, T1, T0)
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void OPPROTO op_andl_T0_T1(void)
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{
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    T0 &= T1;
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}
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void OPPROTO op_xorl_T0_T1(void)
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{
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    T0 ^= T1;
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}
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void OPPROTO op_orl_T0_T1(void)
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{
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    T0 |= T1;
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}
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void OPPROTO op_bicl_T0_T1(void)
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{
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    T0 &= ~T1;
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}
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void OPPROTO op_notl_T1(void)
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{
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    T1 = ~T1;
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}
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void OPPROTO op_logic_T0_cc(void)
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{
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    env->NZF = T0;
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}
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void OPPROTO op_logic_T1_cc(void)
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{
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    env->NZF = T1;
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}
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#define EIP (env->regs[15])
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void OPPROTO op_test_eq(void)
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{
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    if (env->NZF == 0)
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        JUMP_TB(op_test_eq, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_ne(void)
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{
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    if (env->NZF != 0)
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        JUMP_TB(op_test_ne, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_cs(void)
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{
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    if (env->CF != 0)
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        JUMP_TB(op_test_cs, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_cc(void)
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{
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    if (env->CF == 0)
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        JUMP_TB(op_test_cc, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_mi(void)
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{
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    if ((env->NZF & 0x80000000) != 0)
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        JUMP_TB(op_test_mi, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_pl(void)
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{
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    if ((env->NZF & 0x80000000) == 0)
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        JUMP_TB(op_test_pl, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_vs(void)
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{
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    if ((env->VF & 0x80000000) != 0)
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        JUMP_TB(op_test_vs, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_vc(void)
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{
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    if ((env->VF & 0x80000000) == 0)
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        JUMP_TB(op_test_vc, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_hi(void)
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{
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    if (env->CF != 0 && env->NZF != 0)
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        JUMP_TB(op_test_hi, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_ls(void)
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{
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    if (env->CF == 0 || env->NZF == 0)
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        JUMP_TB(op_test_ls, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_ge(void)
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{
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    if (((env->VF ^ env->NZF) & 0x80000000) == 0)
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        JUMP_TB(op_test_ge, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_lt(void)
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{
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    if (((env->VF ^ env->NZF) & 0x80000000) != 0)
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        JUMP_TB(op_test_lt, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_gt(void)
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{
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    if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0)
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        JUMP_TB(op_test_gt, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_test_le(void)
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{
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    if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0)
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        JUMP_TB(op_test_le, PARAM1, 0, PARAM2);
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    FORCE_RET();
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}
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void OPPROTO op_jmp(void)
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{
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    JUMP_TB(op_jmp, PARAM1, 1, PARAM2);
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}
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void OPPROTO op_exit_tb(void)
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{
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    EXIT_TB();
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}
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void OPPROTO op_movl_T0_psr(void)
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{
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    T0 = compute_cpsr();
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}
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/* NOTE: N = 1 and Z = 1 cannot be stored currently */
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void OPPROTO op_movl_psr_T0(void)
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{
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    unsigned int psr;
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    psr = T0;
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    env->CF = (psr >> 29) & 1;
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    env->NZF = (psr & 0xc0000000) ^ 0x40000000;
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    env->VF = (psr << 3) & 0x80000000;
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    /* for user mode we do not update other state info */
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}
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void OPPROTO op_mul_T0_T1(void)
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{
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    T0 = T0 * T1;
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}
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/* 64 bit unsigned mul */
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void OPPROTO op_mull_T0_T1(void)
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{
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    uint64_t res;
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    res = (uint64_t)T0 * (uint64_t)T1;
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    T1 = res >> 32;
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    T0 = res;
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}
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/* 64 bit signed mul */
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void OPPROTO op_imull_T0_T1(void)
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{
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    uint64_t res;
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    res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
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    T1 = res >> 32;
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    T0 = res;
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}
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/* 48 bit signed mul, top 32 bits */
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void OPPROTO op_imulw_T0_T1(void)
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{
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  uint64_t res;
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  res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1);
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  T0 = res >> 16;
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}
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void OPPROTO op_addq_T0_T1(void)
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{
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    uint64_t res;
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    res = ((uint64_t)T1 << 32) | T0;
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    res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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    T1 = res >> 32;
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    T0 = res;
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}
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void OPPROTO op_addq_lo_T0_T1(void)
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{
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    uint64_t res;
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    res = ((uint64_t)T1 << 32) | T0;
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    res += (uint64_t)(env->regs[PARAM1]);
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    T1 = res >> 32;
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    T0 = res;
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}
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void OPPROTO op_logicq_cc(void)
425 2c0262af bellard
{
426 2c0262af bellard
    env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0);
427 2c0262af bellard
}
428 2c0262af bellard
429 2c0262af bellard
/* memory access */
430 2c0262af bellard
431 2c0262af bellard
void OPPROTO op_ldub_T0_T1(void)
432 2c0262af bellard
{
433 2c0262af bellard
    T0 = ldub((void *)T1);
434 2c0262af bellard
}
435 2c0262af bellard
436 2c0262af bellard
void OPPROTO op_ldsb_T0_T1(void)
437 2c0262af bellard
{
438 2c0262af bellard
    T0 = ldsb((void *)T1);
439 2c0262af bellard
}
440 2c0262af bellard
441 2c0262af bellard
void OPPROTO op_lduw_T0_T1(void)
442 2c0262af bellard
{
443 2c0262af bellard
    T0 = lduw((void *)T1);
444 2c0262af bellard
}
445 2c0262af bellard
446 2c0262af bellard
void OPPROTO op_ldsw_T0_T1(void)
447 2c0262af bellard
{
448 2c0262af bellard
    T0 = ldsw((void *)T1);
449 2c0262af bellard
}
450 2c0262af bellard
451 2c0262af bellard
void OPPROTO op_ldl_T0_T1(void)
452 2c0262af bellard
{
453 2c0262af bellard
    T0 = ldl((void *)T1);
454 2c0262af bellard
}
455 2c0262af bellard
456 2c0262af bellard
void OPPROTO op_stb_T0_T1(void)
457 2c0262af bellard
{
458 2c0262af bellard
    stb((void *)T1, T0);
459 2c0262af bellard
}
460 2c0262af bellard
461 2c0262af bellard
void OPPROTO op_stw_T0_T1(void)
462 2c0262af bellard
{
463 2c0262af bellard
    stw((void *)T1, T0);
464 2c0262af bellard
}
465 2c0262af bellard
466 2c0262af bellard
void OPPROTO op_stl_T0_T1(void)
467 2c0262af bellard
{
468 2c0262af bellard
    stl((void *)T1, T0);
469 2c0262af bellard
}
470 2c0262af bellard
471 2c0262af bellard
void OPPROTO op_swpb_T0_T1(void)
472 2c0262af bellard
{
473 2c0262af bellard
    int tmp;
474 2c0262af bellard
475 2c0262af bellard
    cpu_lock();
476 2c0262af bellard
    tmp = ldub((void *)T1);
477 2c0262af bellard
    stb((void *)T1, T0);
478 2c0262af bellard
    T0 = tmp;
479 2c0262af bellard
    cpu_unlock();
480 2c0262af bellard
}
481 2c0262af bellard
482 2c0262af bellard
void OPPROTO op_swpl_T0_T1(void)
483 2c0262af bellard
{
484 2c0262af bellard
    int tmp;
485 2c0262af bellard
486 2c0262af bellard
    cpu_lock();
487 2c0262af bellard
    tmp = ldl((void *)T1);
488 2c0262af bellard
    stl((void *)T1, T0);
489 2c0262af bellard
    T0 = tmp;
490 2c0262af bellard
    cpu_unlock();
491 2c0262af bellard
}
492 2c0262af bellard
493 2c0262af bellard
/* shifts */
494 2c0262af bellard
495 2c0262af bellard
/* T1 based */
496 1e8d4eec bellard
497 2c0262af bellard
void OPPROTO op_shll_T1_im(void)
498 2c0262af bellard
{
499 2c0262af bellard
    T1 = T1 << PARAM1;
500 2c0262af bellard
}
501 2c0262af bellard
502 2c0262af bellard
void OPPROTO op_shrl_T1_im(void)
503 2c0262af bellard
{
504 2c0262af bellard
    T1 = (uint32_t)T1 >> PARAM1;
505 2c0262af bellard
}
506 2c0262af bellard
507 1e8d4eec bellard
void OPPROTO op_shrl_T1_0(void)
508 1e8d4eec bellard
{
509 1e8d4eec bellard
    T1 = 0;
510 1e8d4eec bellard
}
511 1e8d4eec bellard
512 2c0262af bellard
void OPPROTO op_sarl_T1_im(void)
513 2c0262af bellard
{
514 2c0262af bellard
    T1 = (int32_t)T1 >> PARAM1;
515 2c0262af bellard
}
516 2c0262af bellard
517 1e8d4eec bellard
void OPPROTO op_sarl_T1_0(void)
518 1e8d4eec bellard
{
519 1e8d4eec bellard
    T1 = (int32_t)T1 >> 31;
520 1e8d4eec bellard
}
521 1e8d4eec bellard
522 2c0262af bellard
void OPPROTO op_rorl_T1_im(void)
523 2c0262af bellard
{
524 2c0262af bellard
    int shift;
525 2c0262af bellard
    shift = PARAM1;
526 2c0262af bellard
    T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
527 2c0262af bellard
}
528 2c0262af bellard
529 88920f34 bellard
void OPPROTO op_rrxl_T1(void)
530 88920f34 bellard
{
531 88920f34 bellard
    T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
532 88920f34 bellard
}
533 88920f34 bellard
534 2c0262af bellard
/* T1 based, set C flag */
535 2c0262af bellard
void OPPROTO op_shll_T1_im_cc(void)
536 2c0262af bellard
{
537 2c0262af bellard
    env->CF = (T1 >> (32 - PARAM1)) & 1;
538 2c0262af bellard
    T1 = T1 << PARAM1;
539 2c0262af bellard
}
540 2c0262af bellard
541 2c0262af bellard
void OPPROTO op_shrl_T1_im_cc(void)
542 2c0262af bellard
{
543 2c0262af bellard
    env->CF = (T1 >> (PARAM1 - 1)) & 1;
544 2c0262af bellard
    T1 = (uint32_t)T1 >> PARAM1;
545 2c0262af bellard
}
546 2c0262af bellard
547 1e8d4eec bellard
void OPPROTO op_shrl_T1_0_cc(void)
548 1e8d4eec bellard
{
549 1e8d4eec bellard
    env->CF = (T1 >> 31) & 1;
550 1e8d4eec bellard
    T1 = 0;
551 1e8d4eec bellard
}
552 1e8d4eec bellard
553 2c0262af bellard
void OPPROTO op_sarl_T1_im_cc(void)
554 2c0262af bellard
{
555 2c0262af bellard
    env->CF = (T1 >> (PARAM1 - 1)) & 1;
556 2c0262af bellard
    T1 = (int32_t)T1 >> PARAM1;
557 2c0262af bellard
}
558 2c0262af bellard
559 1e8d4eec bellard
void OPPROTO op_sarl_T1_0_cc(void)
560 1e8d4eec bellard
{
561 1e8d4eec bellard
    env->CF = (T1 >> 31) & 1;
562 1e8d4eec bellard
    T1 = (int32_t)T1 >> 31;
563 1e8d4eec bellard
}
564 1e8d4eec bellard
565 2c0262af bellard
void OPPROTO op_rorl_T1_im_cc(void)
566 2c0262af bellard
{
567 2c0262af bellard
    int shift;
568 2c0262af bellard
    shift = PARAM1;
569 2c0262af bellard
    env->CF = (T1 >> (shift - 1)) & 1;
570 2c0262af bellard
    T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
571 2c0262af bellard
}
572 2c0262af bellard
573 88920f34 bellard
void OPPROTO op_rrxl_T1_cc(void)
574 88920f34 bellard
{
575 88920f34 bellard
    uint32_t c;
576 88920f34 bellard
    c = T1 & 1;
577 88920f34 bellard
    T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
578 88920f34 bellard
    env->CF = c;
579 88920f34 bellard
}
580 88920f34 bellard
581 2c0262af bellard
/* T2 based */
582 2c0262af bellard
void OPPROTO op_shll_T2_im(void)
583 2c0262af bellard
{
584 2c0262af bellard
    T2 = T2 << PARAM1;
585 2c0262af bellard
}
586 2c0262af bellard
587 2c0262af bellard
void OPPROTO op_shrl_T2_im(void)
588 2c0262af bellard
{
589 2c0262af bellard
    T2 = (uint32_t)T2 >> PARAM1;
590 2c0262af bellard
}
591 2c0262af bellard
592 1e8d4eec bellard
void OPPROTO op_shrl_T2_0(void)
593 1e8d4eec bellard
{
594 1e8d4eec bellard
    T2 = 0;
595 1e8d4eec bellard
}
596 1e8d4eec bellard
597 2c0262af bellard
void OPPROTO op_sarl_T2_im(void)
598 2c0262af bellard
{
599 2c0262af bellard
    T2 = (int32_t)T2 >> PARAM1;
600 2c0262af bellard
}
601 2c0262af bellard
602 1e8d4eec bellard
void OPPROTO op_sarl_T2_0(void)
603 1e8d4eec bellard
{
604 1e8d4eec bellard
    T2 = (int32_t)T2 >> 31;
605 1e8d4eec bellard
}
606 1e8d4eec bellard
607 2c0262af bellard
void OPPROTO op_rorl_T2_im(void)
608 2c0262af bellard
{
609 2c0262af bellard
    int shift;
610 2c0262af bellard
    shift = PARAM1;
611 2c0262af bellard
    T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
612 2c0262af bellard
}
613 2c0262af bellard
614 1e8d4eec bellard
void OPPROTO op_rrxl_T2(void)
615 1e8d4eec bellard
{
616 1e8d4eec bellard
    T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31);
617 1e8d4eec bellard
}
618 1e8d4eec bellard
619 2c0262af bellard
/* T1 based, use T0 as shift count */
620 2c0262af bellard
621 2c0262af bellard
void OPPROTO op_shll_T1_T0(void)
622 2c0262af bellard
{
623 2c0262af bellard
    int shift;
624 2c0262af bellard
    shift = T0 & 0xff;
625 2c0262af bellard
    if (shift >= 32)
626 2c0262af bellard
        T1 = 0;
627 2c0262af bellard
    else
628 2c0262af bellard
        T1 = T1 << shift;
629 2c0262af bellard
    FORCE_RET();
630 2c0262af bellard
}
631 2c0262af bellard
632 2c0262af bellard
void OPPROTO op_shrl_T1_T0(void)
633 2c0262af bellard
{
634 2c0262af bellard
    int shift;
635 2c0262af bellard
    shift = T0 & 0xff;
636 2c0262af bellard
    if (shift >= 32)
637 2c0262af bellard
        T1 = 0;
638 2c0262af bellard
    else
639 2c0262af bellard
        T1 = (uint32_t)T1 >> shift;
640 2c0262af bellard
    FORCE_RET();
641 2c0262af bellard
}
642 2c0262af bellard
643 2c0262af bellard
void OPPROTO op_sarl_T1_T0(void)
644 2c0262af bellard
{
645 2c0262af bellard
    int shift;
646 2c0262af bellard
    shift = T0 & 0xff;
647 2c0262af bellard
    if (shift >= 32)
648 2c0262af bellard
        shift = 31;
649 2c0262af bellard
    T1 = (int32_t)T1 >> shift;
650 2c0262af bellard
}
651 2c0262af bellard
652 2c0262af bellard
void OPPROTO op_rorl_T1_T0(void)
653 2c0262af bellard
{
654 2c0262af bellard
    int shift;
655 2c0262af bellard
    shift = T0 & 0x1f;
656 2c0262af bellard
    if (shift) {
657 2c0262af bellard
        T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
658 2c0262af bellard
    }
659 2c0262af bellard
    FORCE_RET();
660 2c0262af bellard
}
661 2c0262af bellard
662 2c0262af bellard
/* T1 based, use T0 as shift count and compute CF */
663 2c0262af bellard
664 2c0262af bellard
void OPPROTO op_shll_T1_T0_cc(void)
665 2c0262af bellard
{
666 2c0262af bellard
    int shift;
667 2c0262af bellard
    shift = T0 & 0xff;
668 2c0262af bellard
    if (shift >= 32) {
669 2c0262af bellard
        if (shift == 32)
670 2c0262af bellard
            env->CF = T1 & 1;
671 2c0262af bellard
        else
672 2c0262af bellard
            env->CF = 0;
673 2c0262af bellard
        T1 = 0;
674 2c0262af bellard
    } else if (shift != 0) {
675 2c0262af bellard
        env->CF = (T1 >> (32 - shift)) & 1;
676 2c0262af bellard
        T1 = T1 << shift;
677 2c0262af bellard
    }
678 2c0262af bellard
    FORCE_RET();
679 2c0262af bellard
}
680 2c0262af bellard
681 2c0262af bellard
void OPPROTO op_shrl_T1_T0_cc(void)
682 2c0262af bellard
{
683 2c0262af bellard
    int shift;
684 2c0262af bellard
    shift = T0 & 0xff;
685 2c0262af bellard
    if (shift >= 32) {
686 2c0262af bellard
        if (shift == 32)
687 2c0262af bellard
            env->CF = (T1 >> 31) & 1;
688 2c0262af bellard
        else
689 2c0262af bellard
            env->CF = 0;
690 2c0262af bellard
        T1 = 0;
691 2c0262af bellard
    } else if (shift != 0) {
692 2c0262af bellard
        env->CF = (T1 >> (shift - 1)) & 1;
693 2c0262af bellard
        T1 = (uint32_t)T1 >> shift;
694 2c0262af bellard
    }
695 2c0262af bellard
    FORCE_RET();
696 2c0262af bellard
}
697 2c0262af bellard
698 2c0262af bellard
void OPPROTO op_sarl_T1_T0_cc(void)
699 2c0262af bellard
{
700 2c0262af bellard
    int shift;
701 2c0262af bellard
    shift = T0 & 0xff;
702 2c0262af bellard
    if (shift >= 32) {
703 2c0262af bellard
        env->CF = (T1 >> 31) & 1;
704 2c0262af bellard
        T1 = (int32_t)T1 >> 31;
705 2c0262af bellard
    } else {
706 2c0262af bellard
        env->CF = (T1 >> (shift - 1)) & 1;
707 2c0262af bellard
        T1 = (int32_t)T1 >> shift;
708 2c0262af bellard
    }
709 2c0262af bellard
    FORCE_RET();
710 2c0262af bellard
}
711 2c0262af bellard
712 2c0262af bellard
void OPPROTO op_rorl_T1_T0_cc(void)
713 2c0262af bellard
{
714 2c0262af bellard
    int shift1, shift;
715 2c0262af bellard
    shift1 = T0 & 0xff;
716 2c0262af bellard
    shift = shift1 & 0x1f;
717 2c0262af bellard
    if (shift == 0) {
718 2c0262af bellard
        if (shift1 != 0)
719 2c0262af bellard
            env->CF = (T1 >> 31) & 1;
720 2c0262af bellard
    } else {
721 2c0262af bellard
        env->CF = (T1 >> (shift - 1)) & 1;
722 2c0262af bellard
        T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
723 2c0262af bellard
    }
724 2c0262af bellard
    FORCE_RET();
725 2c0262af bellard
}
726 2c0262af bellard
727 99c475ab bellard
/* misc */
728 99c475ab bellard
void OPPROTO op_clz_T0(void)
729 99c475ab bellard
{
730 99c475ab bellard
    int count;
731 99c475ab bellard
    for (count = 32; T0 > 0; count--)
732 99c475ab bellard
        T0 = T0 >> 1;
733 99c475ab bellard
    T0 = count;
734 99c475ab bellard
    FORCE_RET();
735 99c475ab bellard
}
736 99c475ab bellard
737 99c475ab bellard
void OPPROTO op_sarl_T0_im(void)
738 99c475ab bellard
{
739 99c475ab bellard
    T0 = (int32_t)T0 >> PARAM1;
740 99c475ab bellard
}
741 99c475ab bellard
742 99c475ab bellard
/* 16->32 Sign extend */
743 99c475ab bellard
void OPPROTO op_sxl_T0(void)
744 99c475ab bellard
{
745 99c475ab bellard
  T0 = (int16_t)T0;
746 99c475ab bellard
}
747 99c475ab bellard
748 99c475ab bellard
void OPPROTO op_sxl_T1(void)
749 99c475ab bellard
{
750 99c475ab bellard
  T1 = (int16_t)T1;
751 99c475ab bellard
}
752 99c475ab bellard
753 99c475ab bellard
#define SIGNBIT (uint32_t)0x80000000
754 99c475ab bellard
/* saturating arithmetic  */
755 99c475ab bellard
void OPPROTO op_addl_T0_T1_setq(void)
756 99c475ab bellard
{
757 99c475ab bellard
  uint32_t res;
758 99c475ab bellard
759 99c475ab bellard
  res = T0 + T1;
760 99c475ab bellard
  if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT))
761 99c475ab bellard
      env->QF = 1;
762 99c475ab bellard
763 99c475ab bellard
  T0 = res;
764 99c475ab bellard
  FORCE_RET();
765 99c475ab bellard
}
766 99c475ab bellard
767 99c475ab bellard
void OPPROTO op_addl_T0_T1_saturate(void)
768 99c475ab bellard
{
769 99c475ab bellard
  uint32_t res;
770 99c475ab bellard
771 99c475ab bellard
  res = T0 + T1;
772 99c475ab bellard
  if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT)) {
773 99c475ab bellard
      env->QF = 1;
774 99c475ab bellard
      if (T0 & SIGNBIT)
775 99c475ab bellard
          T0 = 0x80000000;
776 99c475ab bellard
      else
777 99c475ab bellard
          T0 = 0x7fffffff;
778 99c475ab bellard
  }
779 99c475ab bellard
  else
780 99c475ab bellard
    T0 = res;
781 99c475ab bellard
  
782 99c475ab bellard
  FORCE_RET();
783 99c475ab bellard
}
784 99c475ab bellard
785 99c475ab bellard
void OPPROTO op_subl_T0_T1_saturate(void)
786 99c475ab bellard
{
787 99c475ab bellard
  uint32_t res;
788 99c475ab bellard
789 99c475ab bellard
  res = T0 - T1;
790 99c475ab bellard
  if (((res ^ T0) & SIGNBIT) && ((T0 ^ T1) & SIGNBIT)) {
791 99c475ab bellard
      env->QF = 1;
792 99c475ab bellard
      if (T0 & SIGNBIT)
793 99c475ab bellard
          T0 = 0x8000000;
794 99c475ab bellard
      else
795 99c475ab bellard
          T0 = 0x7fffffff;
796 99c475ab bellard
  }
797 99c475ab bellard
  else
798 99c475ab bellard
    T0 = res;
799 99c475ab bellard
  
800 99c475ab bellard
  FORCE_RET();
801 99c475ab bellard
}
802 99c475ab bellard
803 99c475ab bellard
/* thumb shift by immediate */
804 99c475ab bellard
void OPPROTO op_shll_T0_im_thumb(void)
805 99c475ab bellard
{
806 99c475ab bellard
    int shift;
807 99c475ab bellard
    shift = PARAM1;
808 99c475ab bellard
    if (shift != 0) {
809 99c475ab bellard
        env->CF = (T1 >> (32 - shift)) & 1;
810 99c475ab bellard
        T0 = T0 << shift;
811 99c475ab bellard
    }
812 99c475ab bellard
    env->NZF = T0;
813 99c475ab bellard
    FORCE_RET();
814 99c475ab bellard
}
815 99c475ab bellard
816 99c475ab bellard
void OPPROTO op_shrl_T0_im_thumb(void)
817 99c475ab bellard
{
818 99c475ab bellard
    int shift;
819 99c475ab bellard
820 99c475ab bellard
    shift = PARAM1;
821 99c475ab bellard
    if (shift == 0) {
822 99c475ab bellard
        env->CF = 0;
823 99c475ab bellard
        T0 = 0;
824 99c475ab bellard
    } else {
825 99c475ab bellard
        env->CF = (T0 >> (shift - 1)) & 1;
826 99c475ab bellard
        T0 = T0 >> shift;
827 99c475ab bellard
    }
828 99c475ab bellard
    FORCE_RET();
829 99c475ab bellard
}
830 99c475ab bellard
831 99c475ab bellard
void OPPROTO op_sarl_T0_im_thumb(void)
832 99c475ab bellard
{
833 99c475ab bellard
    int shift;
834 99c475ab bellard
835 99c475ab bellard
    shift = PARAM1;
836 99c475ab bellard
    if (shift == 0) {
837 99c475ab bellard
        T0 = ((int32_t)T0) >> 31;
838 99c475ab bellard
        env->CF = T0 & 1;
839 99c475ab bellard
    } else {
840 99c475ab bellard
        env->CF = (T0 >> (shift - 1)) & 1;
841 99c475ab bellard
        T0 = ((int32_t)T0) >> shift;
842 99c475ab bellard
    }
843 99c475ab bellard
    env->NZF = T0;
844 99c475ab bellard
    FORCE_RET();
845 99c475ab bellard
}
846 99c475ab bellard
847 2c0262af bellard
/* exceptions */
848 2c0262af bellard
849 2c0262af bellard
void OPPROTO op_swi(void)
850 2c0262af bellard
{
851 2c0262af bellard
    env->exception_index = EXCP_SWI;
852 2c0262af bellard
    cpu_loop_exit();
853 2c0262af bellard
}
854 2c0262af bellard
855 2c0262af bellard
void OPPROTO op_undef_insn(void)
856 2c0262af bellard
{
857 2c0262af bellard
    env->exception_index = EXCP_UDEF;
858 2c0262af bellard
    cpu_loop_exit();
859 2c0262af bellard
}
860 2c0262af bellard
861 b7bcbe95 bellard
/* VFP support.  We follow the convention used for VFP instrunctions:
862 b7bcbe95 bellard
   Single precition routines have a "s" suffix, double precision a
863 b7bcbe95 bellard
   "d" suffix.  */
864 2c0262af bellard
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#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void)
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#define VFP_BINOP(name, op) \
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VFP_OP(name, s)             \
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{                           \
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    FT0s = FT0s op FT1s;    \
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}                           \
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VFP_OP(name, d)             \
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{                           \
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    FT0d = FT0d op FT1d;    \
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}
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VFP_BINOP(add, +)
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VFP_BINOP(sub, -)
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VFP_BINOP(mul, *)
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VFP_BINOP(div, /)
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#undef VFP_BINOP
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#define VFP_HELPER(name)  \
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VFP_OP(name, s)           \
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{                         \
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    do_vfp_##name##s();    \
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}                         \
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VFP_OP(name, d)           \
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{                         \
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    do_vfp_##name##d();    \
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}
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VFP_HELPER(abs)
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VFP_HELPER(sqrt)
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VFP_HELPER(cmp)
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VFP_HELPER(cmpe)
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#undef VFP_HELPER
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/* XXX: Will this do the right thing for NANs.  Should invert the signbit
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   without looking at the rest of the value.  */
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VFP_OP(neg, s)
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{
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    FT0s = -FT0s;
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}
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VFP_OP(neg, d)
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{
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    FT0d = -FT0d;
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}
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VFP_OP(F1_ld0, s)
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{
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    FT1s = 0.0f;
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}
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VFP_OP(F1_ld0, d)
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{
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    FT1d = 0.0;
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}
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/* Helper routines to perform bitwise copies between float and int.  */
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static inline float vfp_itos(uint32_t i)
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{
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    union {
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        uint32_t i;
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        float s;
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    } v;
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    v.i = i;
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    return v.s;
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}
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static inline uint32_t vfp_stoi(float s)
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{
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    union {
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        uint32_t i;
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        float s;
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    } v;
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    v.s = s;
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    return v.i;
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}
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/* Integer to float conversion.  */
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VFP_OP(uito, s)
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{
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    FT0s = (float)(uint32_t)vfp_stoi(FT0s);
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}
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VFP_OP(uito, d)
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{
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    FT0d = (double)(uint32_t)vfp_stoi(FT0s);
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}
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VFP_OP(sito, s)
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{
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    FT0s = (float)(int32_t)vfp_stoi(FT0s);
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}
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VFP_OP(sito, d)
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{
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    FT0d = (double)(int32_t)vfp_stoi(FT0s);
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}
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/* Float to integer conversion.  */
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VFP_OP(toui, s)
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{
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    FT0s = vfp_itos((uint32_t)FT0s);
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}
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VFP_OP(toui, d)
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{
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    FT0s = vfp_itos((uint32_t)FT0d);
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}
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VFP_OP(tosi, s)
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{
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    FT0s = vfp_itos((int32_t)FT0s);
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}
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VFP_OP(tosi, d)
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{
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    FT0s = vfp_itos((int32_t)FT0d);
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}
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/* TODO: Set rounding mode properly.  */
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VFP_OP(touiz, s)
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{
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    FT0s = vfp_itos((uint32_t)FT0s);
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}
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VFP_OP(touiz, d)
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{
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    FT0s = vfp_itos((uint32_t)FT0d);
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}
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VFP_OP(tosiz, s)
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{
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    FT0s = vfp_itos((int32_t)FT0s);
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}
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VFP_OP(tosiz, d)
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{
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    FT0s = vfp_itos((int32_t)FT0d);
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}
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/* floating point conversion */
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VFP_OP(fcvtd, s)
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{
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    FT0d = (double)FT0s;
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}
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VFP_OP(fcvts, d)
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{
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    FT0s = (float)FT0d;
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}
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/* Get and Put values from registers.  */
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VFP_OP(getreg_F0, d)
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{
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  FT0d = *(double *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F0, s)
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{
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  FT0s = *(float *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F1, d)
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{
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  FT1d = *(double *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F1, s)
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{
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  FT1s = *(float *)((char *) env + PARAM1);
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}
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VFP_OP(setreg_F0, d)
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{
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  *(double *)((char *) env + PARAM1) = FT0d;
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}
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VFP_OP(setreg_F0, s)
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{
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  *(float *)((char *) env + PARAM1) = FT0s;
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}
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VFP_OP(foobar, d)
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{
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  FT0d = env->vfp.regs.s[3];
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}
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void OPPROTO op_vfp_movl_T0_fpscr(void)
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{
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    do_vfp_get_fpscr ();
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}
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void OPPROTO op_vfp_movl_T0_fpscr_flags(void)
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{
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    T0 = env->vfp.fpscr & (0xf << 28);
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}
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void OPPROTO op_vfp_movl_fpscr_T0(void)
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{
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    do_vfp_set_fpscr();
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}
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/* Move between FT0s to T0  */
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void OPPROTO op_vfp_mrs(void)
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{
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    T0 = vfp_stoi(FT0s);
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}
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void OPPROTO op_vfp_msr(void)
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{
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    FT0s = vfp_itos(T0);
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}
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/* Move between FT0d and {T0,T1} */
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void OPPROTO op_vfp_mrrd(void)
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{
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    CPU_DoubleU u;
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    u.d = FT0d;
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    T0 = u.l.lower;
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    T1 = u.l.upper;
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}
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void OPPROTO op_vfp_mdrr(void)
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{
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    CPU_DoubleU u;
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    u.l.lower = T0;
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    u.l.upper = T1;
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    FT0d = u.d;
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}
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/* Floating point load/store.  Address is in T1 */
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void OPPROTO op_vfp_lds(void)
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{
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    FT0s = ldfl((void *)T1);
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}
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void OPPROTO op_vfp_ldd(void)
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{
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    FT0d = ldfq((void *)T1);
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}
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void OPPROTO op_vfp_sts(void)
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{
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    stfl((void *)T1, FT0s);
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}
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void OPPROTO op_vfp_std(void)
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{
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    stfq((void *)T1, FT0d);
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}