root / target-sparc / cpu.h @ 157777ef
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | af7bf89b | bellard | |
6 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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7 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
8 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
9 | af7bf89b | bellard | #define TARGET_FPREG_T float |
10 | af7bf89b | bellard | #else
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11 | af7bf89b | bellard | #define TARGET_LONG_BITS 64 |
12 | af7bf89b | bellard | #define TARGET_FPREGS 64 |
13 | af7bf89b | bellard | #define TARGET_FPREG_T double |
14 | af7bf89b | bellard | #endif
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15 | 3cf1e035 | bellard | |
16 | 7a3f1944 | bellard | #include "cpu-defs.h" |
17 | 7a3f1944 | bellard | |
18 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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19 | 7a3f1944 | bellard | |
20 | cf495bcf | bellard | /* trap definitions */
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21 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
22 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
23 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
24 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
25 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
26 | cf495bcf | bellard | #define TT_WIN_UNF 0x06 |
27 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
28 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
29 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
30 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
31 | cf495bcf | bellard | #define TT_TRAP 0x80 |
32 | 7a3f1944 | bellard | |
33 | 7a3f1944 | bellard | #define PSR_NEG (1<<23) |
34 | 7a3f1944 | bellard | #define PSR_ZERO (1<<22) |
35 | 7a3f1944 | bellard | #define PSR_OVF (1<<21) |
36 | 7a3f1944 | bellard | #define PSR_CARRY (1<<20) |
37 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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38 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
39 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
40 | e8af50a3 | bellard | #define PSR_S (1<<7) |
41 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
42 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
43 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
44 | e8af50a3 | bellard | |
45 | e8af50a3 | bellard | /* Trap base register */
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46 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
47 | e8af50a3 | bellard | |
48 | e8af50a3 | bellard | /* Fcc */
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49 | e8af50a3 | bellard | #define FSR_RD1 (1<<31) |
50 | e8af50a3 | bellard | #define FSR_RD0 (1<<30) |
51 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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52 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
53 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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54 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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55 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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56 | e8af50a3 | bellard | |
57 | e8af50a3 | bellard | #define FSR_NVM (1<<27) |
58 | e8af50a3 | bellard | #define FSR_OFM (1<<26) |
59 | e8af50a3 | bellard | #define FSR_UFM (1<<25) |
60 | e8af50a3 | bellard | #define FSR_DZM (1<<24) |
61 | e8af50a3 | bellard | #define FSR_NXM (1<<23) |
62 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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63 | e8af50a3 | bellard | |
64 | e8af50a3 | bellard | #define FSR_NVA (1<<9) |
65 | e8af50a3 | bellard | #define FSR_OFA (1<<8) |
66 | e8af50a3 | bellard | #define FSR_UFA (1<<7) |
67 | e8af50a3 | bellard | #define FSR_DZA (1<<6) |
68 | e8af50a3 | bellard | #define FSR_NXA (1<<5) |
69 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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70 | e8af50a3 | bellard | |
71 | e8af50a3 | bellard | #define FSR_NVC (1<<4) |
72 | e8af50a3 | bellard | #define FSR_OFC (1<<3) |
73 | e8af50a3 | bellard | #define FSR_UFC (1<<2) |
74 | e8af50a3 | bellard | #define FSR_DZC (1<<1) |
75 | e8af50a3 | bellard | #define FSR_NXC (1<<0) |
76 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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77 | e8af50a3 | bellard | |
78 | e8af50a3 | bellard | #define FSR_FTT2 (1<<16) |
79 | e8af50a3 | bellard | #define FSR_FTT1 (1<<15) |
80 | e8af50a3 | bellard | #define FSR_FTT0 (1<<14) |
81 | e8af50a3 | bellard | #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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82 | e80cfcfc | bellard | #define FSR_FTT_IEEE_EXCP (1 << 14) |
83 | e80cfcfc | bellard | #define FSR_FTT_UNIMPFPOP (3 << 14) |
84 | e80cfcfc | bellard | #define FSR_FTT_INVAL_FPR (6 << 14) |
85 | e8af50a3 | bellard | |
86 | e8af50a3 | bellard | #define FSR_FCC1 (1<<11) |
87 | e8af50a3 | bellard | #define FSR_FCC0 (1<<10) |
88 | e8af50a3 | bellard | |
89 | e8af50a3 | bellard | /* MMU */
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90 | e8af50a3 | bellard | #define MMU_E (1<<0) |
91 | e8af50a3 | bellard | #define MMU_NF (1<<1) |
92 | e8af50a3 | bellard | |
93 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
94 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
95 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
96 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
97 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
98 | e8af50a3 | bellard | |
99 | e8af50a3 | bellard | #define PG_ACCESSED_BIT 5 |
100 | e8af50a3 | bellard | #define PG_MODIFIED_BIT 6 |
101 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
102 | e8af50a3 | bellard | |
103 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
104 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
105 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
106 | e8af50a3 | bellard | |
107 | 1d6e34fd | bellard | /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
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108 | 1d6e34fd | bellard | #define NWINDOWS 8 |
109 | cf495bcf | bellard | |
110 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
111 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
112 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
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113 | af7bf89b | bellard | TARGET_FPREG_T fpr[TARGET_FPREGS]; /* floating point registers */
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114 | af7bf89b | bellard | target_ulong pc; /* program counter */
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115 | af7bf89b | bellard | target_ulong npc; /* next program counter */
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116 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
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117 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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118 | e8af50a3 | bellard | uint32_t fsr; /* FPU state register */
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119 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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120 | cf495bcf | bellard | from PSR) */
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121 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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122 | e8af50a3 | bellard | uint32_t tbr; /* trap base register */
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123 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
124 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
125 | e8af50a3 | bellard | int psret; /* enable traps */ |
126 | e80cfcfc | bellard | int psrpil; /* interrupt level */ |
127 | e80cfcfc | bellard | int psref; /* enable fpu */ |
128 | cf495bcf | bellard | jmp_buf jmp_env; |
129 | cf495bcf | bellard | int user_mode_only;
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130 | cf495bcf | bellard | int exception_index;
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131 | cf495bcf | bellard | int interrupt_index;
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132 | cf495bcf | bellard | int interrupt_request;
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133 | cf495bcf | bellard | struct TranslationBlock *current_tb;
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134 | cf495bcf | bellard | void *opaque;
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135 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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136 | af7bf89b | bellard | target_ulong regbase[NWINDOWS * 16 + 8]; |
137 | d720b93d | bellard | |
138 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
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139 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
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140 | d720b93d | bellard | context) */
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141 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
142 | d720b93d | bellard | written */
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143 | d720b93d | bellard | unsigned long mem_write_vaddr; /* target virtual addr at which the |
144 | d720b93d | bellard | memory was written */
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145 | e8af50a3 | bellard | /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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146 | e8af50a3 | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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147 | e8af50a3 | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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148 | e8af50a3 | bellard | /* MMU regs */
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149 | e8af50a3 | bellard | uint32_t mmuregs[16];
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150 | e8af50a3 | bellard | /* temporary float registers */
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151 | e8af50a3 | bellard | float ft0, ft1, ft2;
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152 | e8af50a3 | bellard | double dt0, dt1, dt2;
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153 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
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154 | af7bf89b | bellard | target_ulong t0, t1, t2; |
155 | af7bf89b | bellard | #endif
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156 | e8af50a3 | bellard | |
157 | e8af50a3 | bellard | /* ice debug support */
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158 | af7bf89b | bellard | target_ulong breakpoints[MAX_BREAKPOINTS]; |
159 | e8af50a3 | bellard | int nb_breakpoints;
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160 | e8af50a3 | bellard | int singlestep_enabled; /* XXX: should use CPU single step mode instead */ |
161 | e8af50a3 | bellard | |
162 | 7a3f1944 | bellard | } CPUSPARCState; |
163 | 7a3f1944 | bellard | |
164 | 7a3f1944 | bellard | CPUSPARCState *cpu_sparc_init(void);
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165 | 7a3f1944 | bellard | int cpu_sparc_exec(CPUSPARCState *s);
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166 | 7a3f1944 | bellard | int cpu_sparc_close(CPUSPARCState *s);
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167 | e80cfcfc | bellard | void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f); |
168 | e80cfcfc | bellard | double cpu_put_fp64(uint64_t mant, uint16_t exp);
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169 | 7a3f1944 | bellard | |
170 | b4ff5987 | bellard | /* Fake impl 0, version 4 */
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171 | af7bf89b | bellard | #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \ |
172 | b4ff5987 | bellard | (env->psref? PSR_EF : 0) | \
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173 | b4ff5987 | bellard | (env->psrpil << 8) | \
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174 | b4ff5987 | bellard | (env->psrs? PSR_S : 0) | \
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175 | afc7df11 | bellard | (env->psrps? PSR_PS : 0) | \
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176 | b4ff5987 | bellard | (env->psret? PSR_ET : 0) | env->cwp)
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177 | b4ff5987 | bellard | |
178 | b4ff5987 | bellard | #ifndef NO_CPU_IO_DEFS
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179 | b4ff5987 | bellard | void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); |
180 | b4ff5987 | bellard | #endif
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181 | b4ff5987 | bellard | |
182 | b4ff5987 | bellard | #define PUT_PSR(env, val) do { int _tmp = val; \ |
183 | af7bf89b | bellard | env->psr = _tmp & PSR_ICC; \ |
184 | b4ff5987 | bellard | env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
185 | b4ff5987 | bellard | env->psrpil = (_tmp & PSR_PIL) >> 8; \
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186 | b4ff5987 | bellard | env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
187 | b4ff5987 | bellard | env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
188 | b4ff5987 | bellard | env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
189 | b4ff5987 | bellard | cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
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190 | b4ff5987 | bellard | } while (0) |
191 | b4ff5987 | bellard | |
192 | 7a3f1944 | bellard | struct siginfo;
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193 | 7a3f1944 | bellard | int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); |
194 | 7a3f1944 | bellard | |
195 | e8af50a3 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
196 | 7a3f1944 | bellard | #include "cpu-all.h" |
197 | 7a3f1944 | bellard | |
198 | 7a3f1944 | bellard | #endif |