Revision 1579a72e target-mips/op.c
| b/target-mips/op.c | ||
|---|---|---|
| 336 | 336 |
T0 = (int32_t)T0 + (int32_t)T1; |
| 337 | 337 |
if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
|
| 338 | 338 |
/* operands of same sign, result different sign */ |
| 339 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
|
|
| 339 |
CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
|
| 340 | 340 |
} |
| 341 | 341 |
T0 = (int32_t)T0; |
| 342 | 342 |
RETURN(); |
| ... | ... | |
| 356 | 356 |
T0 = (int32_t)T0 - (int32_t)T1; |
| 357 | 357 |
if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
|
| 358 | 358 |
/* operands of different sign, first operand and result different sign */ |
| 359 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
|
|
| 359 |
CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
|
| 360 | 360 |
} |
| 361 | 361 |
T0 = (int32_t)T0; |
| 362 | 362 |
RETURN(); |
| ... | ... | |
| 402 | 402 |
T0 += T1; |
| 403 | 403 |
if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
|
| 404 | 404 |
/* operands of same sign, result different sign */ |
| 405 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
|
|
| 405 |
CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
|
| 406 | 406 |
} |
| 407 | 407 |
RETURN(); |
| 408 | 408 |
} |
| ... | ... | |
| 421 | 421 |
T0 = (int64_t)T0 - (int64_t)T1; |
| 422 | 422 |
if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
|
| 423 | 423 |
/* operands of different sign, first operand and result different sign */ |
| 424 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
|
|
| 424 |
CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
|
| 425 | 425 |
} |
| 426 | 426 |
RETURN(); |
| 427 | 427 |
} |
| ... | ... | |
| 1650 | 1650 |
{
|
| 1651 | 1651 |
if (!(env->CP0_Status & (1 << CP0St_CU0)) && |
| 1652 | 1652 |
(env->hflags & MIPS_HFLAG_UM)) {
|
| 1653 |
CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 0);
|
|
| 1653 |
CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0); |
|
| 1654 | 1654 |
} |
| 1655 | 1655 |
RETURN(); |
| 1656 | 1656 |
} |
| ... | ... | |
| 1658 | 1658 |
void op_cp1_enabled(void) |
| 1659 | 1659 |
{
|
| 1660 | 1660 |
if (!(env->CP0_Status & (1 << CP0St_CU1))) {
|
| 1661 |
CALL_FROM_TB2(do_raise_exception_direct_err, EXCP_CpU, 1);
|
|
| 1661 |
CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1); |
|
| 1662 | 1662 |
} |
| 1663 | 1663 |
RETURN(); |
| 1664 | 1664 |
} |
| ... | ... | |
| 2063 | 2063 |
void op_trap (void) |
| 2064 | 2064 |
{
|
| 2065 | 2065 |
if (T0) {
|
| 2066 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
|
|
| 2066 |
CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
|
| 2067 | 2067 |
} |
| 2068 | 2068 |
RETURN(); |
| 2069 | 2069 |
} |
| ... | ... | |
| 2116 | 2116 |
|
| 2117 | 2117 |
void op_rdhwr_cpunum(void) |
| 2118 | 2118 |
{
|
| 2119 |
if (env->CP0_HWREna & (1 << 0)) |
|
| 2120 |
T0 = env->CP0_EBase & 0x2ff; |
|
| 2119 |
if (!(env->hflags & MIPS_HFLAG_UM) || |
|
| 2120 |
(env->CP0_HWREna & (1 << 0)) || |
|
| 2121 |
(env->CP0_Status & (1 << CP0St_CU0))) |
|
| 2122 |
T0 = env->CP0_EBase & 0x3ff; |
|
| 2121 | 2123 |
else |
| 2122 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
|
|
| 2124 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI);
|
|
| 2123 | 2125 |
RETURN(); |
| 2124 | 2126 |
} |
| 2125 | 2127 |
|
| 2126 | 2128 |
void op_rdhwr_synci_step(void) |
| 2127 | 2129 |
{
|
| 2128 |
if (env->CP0_HWREna & (1 << 1)) |
|
| 2129 |
T0 = env->SYNCI_Step; |
|
| 2130 |
if (!(env->hflags & MIPS_HFLAG_UM) || |
|
| 2131 |
(env->CP0_HWREna & (1 << 1)) || |
|
| 2132 |
(env->CP0_Status & (1 << CP0St_CU0))) |
|
| 2133 |
T0 = env->SYNCI_Step; |
|
| 2130 | 2134 |
else |
| 2131 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
|
|
| 2135 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI);
|
|
| 2132 | 2136 |
RETURN(); |
| 2133 | 2137 |
} |
| 2134 | 2138 |
|
| 2135 | 2139 |
void op_rdhwr_cc(void) |
| 2136 | 2140 |
{
|
| 2137 |
if (env->CP0_HWREna & (1 << 2)) |
|
| 2138 |
T0 = env->CP0_Count; |
|
| 2141 |
if (!(env->hflags & MIPS_HFLAG_UM) || |
|
| 2142 |
(env->CP0_HWREna & (1 << 2)) || |
|
| 2143 |
(env->CP0_Status & (1 << CP0St_CU0))) |
|
| 2144 |
T0 = env->CP0_Count; |
|
| 2139 | 2145 |
else |
| 2140 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
|
|
| 2146 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI);
|
|
| 2141 | 2147 |
RETURN(); |
| 2142 | 2148 |
} |
| 2143 | 2149 |
|
| 2144 | 2150 |
void op_rdhwr_ccres(void) |
| 2145 | 2151 |
{
|
| 2146 |
if (env->CP0_HWREna & (1 << 3)) |
|
| 2147 |
T0 = env->CCRes; |
|
| 2152 |
if (!(env->hflags & MIPS_HFLAG_UM) || |
|
| 2153 |
(env->CP0_HWREna & (1 << 3)) || |
|
| 2154 |
(env->CP0_Status & (1 << CP0St_CU0))) |
|
| 2155 |
T0 = env->CCRes; |
|
| 2148 | 2156 |
else |
| 2149 |
CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); |
|
| 2157 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
|
| 2158 |
RETURN(); |
|
| 2159 |
} |
|
| 2160 |
|
|
| 2161 |
void op_rdhwr_unimpl30(void) |
|
| 2162 |
{
|
|
| 2163 |
if (!(env->hflags & MIPS_HFLAG_UM) || |
|
| 2164 |
(env->CP0_HWREna & (1 << 30)) || |
|
| 2165 |
(env->CP0_Status & (1 << CP0St_CU0))) |
|
| 2166 |
T0 = 0; |
|
| 2167 |
else |
|
| 2168 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
|
| 2169 |
RETURN(); |
|
| 2170 |
} |
|
| 2171 |
|
|
| 2172 |
void op_rdhwr_unimpl31(void) |
|
| 2173 |
{
|
|
| 2174 |
if (!(env->hflags & MIPS_HFLAG_UM) || |
|
| 2175 |
(env->CP0_HWREna & (1 << 31)) || |
|
| 2176 |
(env->CP0_Status & (1 << CP0St_CU0))) |
|
| 2177 |
T0 = 0; |
|
| 2178 |
else |
|
| 2179 |
CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
|
| 2150 | 2180 |
RETURN(); |
| 2151 | 2181 |
} |
| 2152 | 2182 |
|
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