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1 | 27503323 | bellard | /*
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2 | 27503323 | bellard | * QEMU DMA emulation
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3 | 85571bc7 | bellard | *
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4 | 85571bc7 | bellard | * Copyright (c) 2003-2004 Vassili Karpov (malc)
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5 | 85571bc7 | bellard | *
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6 | 27503323 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 27503323 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 27503323 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 27503323 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 27503323 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 27503323 | bellard | * furnished to do so, subject to the following conditions:
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12 | 27503323 | bellard | *
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13 | 27503323 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 27503323 | bellard | * all copies or substantial portions of the Software.
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15 | 27503323 | bellard | *
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16 | 27503323 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 27503323 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 27503323 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 27503323 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 27503323 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 27503323 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 27503323 | bellard | * THE SOFTWARE.
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23 | 27503323 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "isa.h" |
26 | 27503323 | bellard | |
27 | 85571bc7 | bellard | /* #define DEBUG_DMA */
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28 | 7ebb5e41 | bellard | |
29 | 85571bc7 | bellard | #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) |
30 | 27503323 | bellard | #ifdef DEBUG_DMA
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31 | 27503323 | bellard | #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 | 27503323 | bellard | #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 | 27503323 | bellard | #else
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34 | 27503323 | bellard | #define linfo(...)
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35 | 27503323 | bellard | #define ldebug(...)
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36 | 27503323 | bellard | #endif
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37 | 27503323 | bellard | |
38 | 27503323 | bellard | struct dma_regs {
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39 | 27503323 | bellard | int now[2]; |
40 | 27503323 | bellard | uint16_t base[2];
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41 | 27503323 | bellard | uint8_t mode; |
42 | 27503323 | bellard | uint8_t page; |
43 | b0bda528 | bellard | uint8_t pageh; |
44 | 27503323 | bellard | uint8_t dack; |
45 | 27503323 | bellard | uint8_t eop; |
46 | 16f62432 | bellard | DMA_transfer_handler transfer_handler; |
47 | 16f62432 | bellard | void *opaque;
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48 | 27503323 | bellard | }; |
49 | 27503323 | bellard | |
50 | 27503323 | bellard | #define ADDR 0 |
51 | 27503323 | bellard | #define COUNT 1 |
52 | 27503323 | bellard | |
53 | 27503323 | bellard | static struct dma_cont { |
54 | 27503323 | bellard | uint8_t status; |
55 | 27503323 | bellard | uint8_t command; |
56 | 27503323 | bellard | uint8_t mask; |
57 | 27503323 | bellard | uint8_t flip_flop; |
58 | 9eb153f1 | bellard | int dshift;
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59 | 27503323 | bellard | struct dma_regs regs[4]; |
60 | 27503323 | bellard | } dma_controllers[2];
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61 | 27503323 | bellard | |
62 | 27503323 | bellard | enum {
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63 | e875c40a | bellard | CMD_MEMORY_TO_MEMORY = 0x01,
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64 | e875c40a | bellard | CMD_FIXED_ADDRESS = 0x02,
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65 | e875c40a | bellard | CMD_BLOCK_CONTROLLER = 0x04,
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66 | e875c40a | bellard | CMD_COMPRESSED_TIME = 0x08,
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67 | e875c40a | bellard | CMD_CYCLIC_PRIORITY = 0x10,
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68 | e875c40a | bellard | CMD_EXTENDED_WRITE = 0x20,
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69 | e875c40a | bellard | CMD_LOW_DREQ = 0x40,
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70 | e875c40a | bellard | CMD_LOW_DACK = 0x80,
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71 | e875c40a | bellard | CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
72 | e875c40a | bellard | | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
73 | e875c40a | bellard | | CMD_LOW_DREQ | CMD_LOW_DACK |
74 | 27503323 | bellard | |
75 | 27503323 | bellard | }; |
76 | 27503323 | bellard | |
77 | 492c30af | aliguori | static void DMA_run (void); |
78 | 492c30af | aliguori | |
79 | 9eb153f1 | bellard | static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
80 | 9eb153f1 | bellard | |
81 | 7d977de7 | bellard | static void write_page (void *opaque, uint32_t nport, uint32_t data) |
82 | 27503323 | bellard | { |
83 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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84 | 27503323 | bellard | int ichan;
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85 | 27503323 | bellard | |
86 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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87 | 27503323 | bellard | if (-1 == ichan) { |
88 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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89 | 27503323 | bellard | return;
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90 | 27503323 | bellard | } |
91 | 9eb153f1 | bellard | d->regs[ichan].page = data; |
92 | 9eb153f1 | bellard | } |
93 | 9eb153f1 | bellard | |
94 | b0bda528 | bellard | static void write_pageh (void *opaque, uint32_t nport, uint32_t data) |
95 | 9eb153f1 | bellard | { |
96 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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97 | 9eb153f1 | bellard | int ichan;
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98 | 27503323 | bellard | |
99 | 9eb153f1 | bellard | ichan = channels[nport & 7];
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100 | b0bda528 | bellard | if (-1 == ichan) { |
101 | 85571bc7 | bellard | dolog ("invalid channel %#x %#x\n", nport, data);
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102 | b0bda528 | bellard | return;
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103 | b0bda528 | bellard | } |
104 | b0bda528 | bellard | d->regs[ichan].pageh = data; |
105 | b0bda528 | bellard | } |
106 | 9eb153f1 | bellard | |
107 | b0bda528 | bellard | static uint32_t read_page (void *opaque, uint32_t nport) |
108 | b0bda528 | bellard | { |
109 | b0bda528 | bellard | struct dma_cont *d = opaque;
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110 | b0bda528 | bellard | int ichan;
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111 | b0bda528 | bellard | |
112 | b0bda528 | bellard | ichan = channels[nport & 7];
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113 | 9eb153f1 | bellard | if (-1 == ichan) { |
114 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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115 | 9eb153f1 | bellard | return 0; |
116 | 9eb153f1 | bellard | } |
117 | 9eb153f1 | bellard | return d->regs[ichan].page;
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118 | 27503323 | bellard | } |
119 | 27503323 | bellard | |
120 | b0bda528 | bellard | static uint32_t read_pageh (void *opaque, uint32_t nport) |
121 | b0bda528 | bellard | { |
122 | b0bda528 | bellard | struct dma_cont *d = opaque;
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123 | b0bda528 | bellard | int ichan;
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124 | b0bda528 | bellard | |
125 | b0bda528 | bellard | ichan = channels[nport & 7];
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126 | b0bda528 | bellard | if (-1 == ichan) { |
127 | 85571bc7 | bellard | dolog ("invalid channel read %#x\n", nport);
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128 | b0bda528 | bellard | return 0; |
129 | b0bda528 | bellard | } |
130 | b0bda528 | bellard | return d->regs[ichan].pageh;
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131 | b0bda528 | bellard | } |
132 | b0bda528 | bellard | |
133 | 9eb153f1 | bellard | static inline void init_chan (struct dma_cont *d, int ichan) |
134 | 27503323 | bellard | { |
135 | 27503323 | bellard | struct dma_regs *r;
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136 | 27503323 | bellard | |
137 | 9eb153f1 | bellard | r = d->regs + ichan; |
138 | 85571bc7 | bellard | r->now[ADDR] = r->base[ADDR] << d->dshift; |
139 | 27503323 | bellard | r->now[COUNT] = 0;
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140 | 27503323 | bellard | } |
141 | 27503323 | bellard | |
142 | 9eb153f1 | bellard | static inline int getff (struct dma_cont *d) |
143 | 27503323 | bellard | { |
144 | 27503323 | bellard | int ff;
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145 | 27503323 | bellard | |
146 | 9eb153f1 | bellard | ff = d->flip_flop; |
147 | 9eb153f1 | bellard | d->flip_flop = !ff; |
148 | 27503323 | bellard | return ff;
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149 | 27503323 | bellard | } |
150 | 27503323 | bellard | |
151 | 7d977de7 | bellard | static uint32_t read_chan (void *opaque, uint32_t nport) |
152 | 27503323 | bellard | { |
153 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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154 | 85571bc7 | bellard | int ichan, nreg, iport, ff, val, dir;
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155 | 27503323 | bellard | struct dma_regs *r;
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156 | 27503323 | bellard | |
157 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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158 | 9eb153f1 | bellard | ichan = iport >> 1;
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159 | 9eb153f1 | bellard | nreg = iport & 1;
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160 | 9eb153f1 | bellard | r = d->regs + ichan; |
161 | 27503323 | bellard | |
162 | 85571bc7 | bellard | dir = ((r->mode >> 5) & 1) ? -1 : 1; |
163 | 9eb153f1 | bellard | ff = getff (d); |
164 | 27503323 | bellard | if (nreg)
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165 | 9eb153f1 | bellard | val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
166 | 27503323 | bellard | else
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167 | 85571bc7 | bellard | val = r->now[ADDR] + r->now[COUNT] * dir; |
168 | 27503323 | bellard | |
169 | 85571bc7 | bellard | ldebug ("read_chan %#x -> %d\n", iport, val);
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170 | 9eb153f1 | bellard | return (val >> (d->dshift + (ff << 3))) & 0xff; |
171 | 27503323 | bellard | } |
172 | 27503323 | bellard | |
173 | 7d977de7 | bellard | static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
174 | 27503323 | bellard | { |
175 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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176 | 9eb153f1 | bellard | int iport, ichan, nreg;
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177 | 27503323 | bellard | struct dma_regs *r;
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178 | 27503323 | bellard | |
179 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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180 | 9eb153f1 | bellard | ichan = iport >> 1;
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181 | 9eb153f1 | bellard | nreg = iport & 1;
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182 | 9eb153f1 | bellard | r = d->regs + ichan; |
183 | 9eb153f1 | bellard | if (getff (d)) {
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184 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
185 | 9eb153f1 | bellard | init_chan (d, ichan); |
186 | 3504fe17 | bellard | } else {
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187 | 3504fe17 | bellard | r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
188 | 27503323 | bellard | } |
189 | 27503323 | bellard | } |
190 | 27503323 | bellard | |
191 | 7d977de7 | bellard | static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
192 | 27503323 | bellard | { |
193 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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194 | 85571bc7 | bellard | int iport, ichan = 0; |
195 | 27503323 | bellard | |
196 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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197 | 27503323 | bellard | switch (iport) {
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198 | 85571bc7 | bellard | case 0x08: /* command */ |
199 | df475d18 | bellard | if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
200 | 85571bc7 | bellard | dolog ("command %#x not supported\n", data);
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201 | df475d18 | bellard | return;
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202 | 27503323 | bellard | } |
203 | 27503323 | bellard | d->command = data; |
204 | 27503323 | bellard | break;
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205 | 27503323 | bellard | |
206 | 85571bc7 | bellard | case 0x09: |
207 | 27503323 | bellard | ichan = data & 3;
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208 | 27503323 | bellard | if (data & 4) { |
209 | 27503323 | bellard | d->status |= 1 << (ichan + 4); |
210 | 27503323 | bellard | } |
211 | 27503323 | bellard | else {
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212 | 27503323 | bellard | d->status &= ~(1 << (ichan + 4)); |
213 | 27503323 | bellard | } |
214 | 27503323 | bellard | d->status &= ~(1 << ichan);
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215 | 492c30af | aliguori | DMA_run(); |
216 | 27503323 | bellard | break;
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217 | 27503323 | bellard | |
218 | 85571bc7 | bellard | case 0x0a: /* single mask */ |
219 | 27503323 | bellard | if (data & 4) |
220 | 27503323 | bellard | d->mask |= 1 << (data & 3); |
221 | 27503323 | bellard | else
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222 | 27503323 | bellard | d->mask &= ~(1 << (data & 3)); |
223 | 492c30af | aliguori | DMA_run(); |
224 | 27503323 | bellard | break;
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225 | 27503323 | bellard | |
226 | 85571bc7 | bellard | case 0x0b: /* mode */ |
227 | 27503323 | bellard | { |
228 | 16d17fdb | bellard | ichan = data & 3;
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229 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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230 | 85571bc7 | bellard | { |
231 | 85571bc7 | bellard | int op, ai, dir, opmode;
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232 | e875c40a | bellard | op = (data >> 2) & 3; |
233 | e875c40a | bellard | ai = (data >> 4) & 1; |
234 | e875c40a | bellard | dir = (data >> 5) & 1; |
235 | e875c40a | bellard | opmode = (data >> 6) & 3; |
236 | 27503323 | bellard | |
237 | e875c40a | bellard | linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
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238 | e875c40a | bellard | ichan, op, ai, dir, opmode); |
239 | 85571bc7 | bellard | } |
240 | 27503323 | bellard | #endif
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241 | 27503323 | bellard | d->regs[ichan].mode = data; |
242 | 27503323 | bellard | break;
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243 | 27503323 | bellard | } |
244 | 27503323 | bellard | |
245 | 85571bc7 | bellard | case 0x0c: /* clear flip flop */ |
246 | 27503323 | bellard | d->flip_flop = 0;
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247 | 27503323 | bellard | break;
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248 | 27503323 | bellard | |
249 | 85571bc7 | bellard | case 0x0d: /* reset */ |
250 | 27503323 | bellard | d->flip_flop = 0;
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251 | 27503323 | bellard | d->mask = ~0;
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252 | 27503323 | bellard | d->status = 0;
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253 | 27503323 | bellard | d->command = 0;
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254 | 27503323 | bellard | break;
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255 | 27503323 | bellard | |
256 | 85571bc7 | bellard | case 0x0e: /* clear mask for all channels */ |
257 | 27503323 | bellard | d->mask = 0;
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258 | 492c30af | aliguori | DMA_run(); |
259 | 27503323 | bellard | break;
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260 | 27503323 | bellard | |
261 | 85571bc7 | bellard | case 0x0f: /* write mask for all channels */ |
262 | 27503323 | bellard | d->mask = data; |
263 | 492c30af | aliguori | DMA_run(); |
264 | 27503323 | bellard | break;
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265 | 27503323 | bellard | |
266 | 27503323 | bellard | default:
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267 | 85571bc7 | bellard | dolog ("unknown iport %#x\n", iport);
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268 | df475d18 | bellard | break;
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269 | 27503323 | bellard | } |
270 | 27503323 | bellard | |
271 | 16d17fdb | bellard | #ifdef DEBUG_DMA
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272 | 27503323 | bellard | if (0xc != iport) { |
273 | 85571bc7 | bellard | linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
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274 | 9eb153f1 | bellard | nport, ichan, data); |
275 | 27503323 | bellard | } |
276 | 27503323 | bellard | #endif
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277 | 27503323 | bellard | } |
278 | 27503323 | bellard | |
279 | 9eb153f1 | bellard | static uint32_t read_cont (void *opaque, uint32_t nport) |
280 | 9eb153f1 | bellard | { |
281 | 9eb153f1 | bellard | struct dma_cont *d = opaque;
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282 | 9eb153f1 | bellard | int iport, val;
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283 | 85571bc7 | bellard | |
284 | 9eb153f1 | bellard | iport = (nport >> d->dshift) & 0x0f;
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285 | 9eb153f1 | bellard | switch (iport) {
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286 | 85571bc7 | bellard | case 0x08: /* status */ |
287 | 9eb153f1 | bellard | val = d->status; |
288 | 9eb153f1 | bellard | d->status &= 0xf0;
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289 | 9eb153f1 | bellard | break;
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290 | 85571bc7 | bellard | case 0x0f: /* mask */ |
291 | 9eb153f1 | bellard | val = d->mask; |
292 | 9eb153f1 | bellard | break;
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293 | 9eb153f1 | bellard | default:
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294 | 9eb153f1 | bellard | val = 0;
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295 | 9eb153f1 | bellard | break;
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296 | 9eb153f1 | bellard | } |
297 | 85571bc7 | bellard | |
298 | 85571bc7 | bellard | ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
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299 | 9eb153f1 | bellard | return val;
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300 | 9eb153f1 | bellard | } |
301 | 9eb153f1 | bellard | |
302 | 27503323 | bellard | int DMA_get_channel_mode (int nchan) |
303 | 27503323 | bellard | { |
304 | 27503323 | bellard | return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
305 | 27503323 | bellard | } |
306 | 27503323 | bellard | |
307 | 27503323 | bellard | void DMA_hold_DREQ (int nchan) |
308 | 27503323 | bellard | { |
309 | 27503323 | bellard | int ncont, ichan;
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310 | 27503323 | bellard | |
311 | 27503323 | bellard | ncont = nchan > 3;
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312 | 27503323 | bellard | ichan = nchan & 3;
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313 | 27503323 | bellard | linfo ("held cont=%d chan=%d\n", ncont, ichan);
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314 | 27503323 | bellard | dma_controllers[ncont].status |= 1 << (ichan + 4); |
315 | 492c30af | aliguori | DMA_run(); |
316 | 27503323 | bellard | } |
317 | 27503323 | bellard | |
318 | 27503323 | bellard | void DMA_release_DREQ (int nchan) |
319 | 27503323 | bellard | { |
320 | 27503323 | bellard | int ncont, ichan;
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321 | 27503323 | bellard | |
322 | 27503323 | bellard | ncont = nchan > 3;
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323 | 27503323 | bellard | ichan = nchan & 3;
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324 | 27503323 | bellard | linfo ("released cont=%d chan=%d\n", ncont, ichan);
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325 | 27503323 | bellard | dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
326 | 492c30af | aliguori | DMA_run(); |
327 | 27503323 | bellard | } |
328 | 27503323 | bellard | |
329 | 27503323 | bellard | static void channel_run (int ncont, int ichan) |
330 | 27503323 | bellard | { |
331 | 27503323 | bellard | int n;
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332 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
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333 | 85571bc7 | bellard | #ifdef DEBUG_DMA
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334 | 85571bc7 | bellard | int dir, opmode;
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335 | 27503323 | bellard | |
336 | 85571bc7 | bellard | dir = (r->mode >> 5) & 1; |
337 | 85571bc7 | bellard | opmode = (r->mode >> 6) & 3; |
338 | 27503323 | bellard | |
339 | 85571bc7 | bellard | if (dir) {
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340 | 85571bc7 | bellard | dolog ("DMA in address decrement mode\n");
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341 | 85571bc7 | bellard | } |
342 | 85571bc7 | bellard | if (opmode != 1) { |
343 | 85571bc7 | bellard | dolog ("DMA not in single mode select %#x\n", opmode);
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344 | 85571bc7 | bellard | } |
345 | 85571bc7 | bellard | #endif
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346 | 27503323 | bellard | |
347 | 85571bc7 | bellard | r = dma_controllers[ncont].regs + ichan; |
348 | 85571bc7 | bellard | n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
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349 | 85571bc7 | bellard | r->now[COUNT], (r->base[COUNT] + 1) << ncont);
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350 | 85571bc7 | bellard | r->now[COUNT] = n; |
351 | 85571bc7 | bellard | ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); |
352 | 27503323 | bellard | } |
353 | 27503323 | bellard | |
354 | 492c30af | aliguori | static QEMUBH *dma_bh;
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355 | 492c30af | aliguori | |
356 | 492c30af | aliguori | static void DMA_run (void) |
357 | 27503323 | bellard | { |
358 | 27503323 | bellard | struct dma_cont *d;
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359 | 27503323 | bellard | int icont, ichan;
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360 | 492c30af | aliguori | int rearm = 0; |
361 | 27503323 | bellard | |
362 | 27503323 | bellard | d = dma_controllers; |
363 | 27503323 | bellard | |
364 | 27503323 | bellard | for (icont = 0; icont < 2; icont++, d++) { |
365 | 27503323 | bellard | for (ichan = 0; ichan < 4; ichan++) { |
366 | 27503323 | bellard | int mask;
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367 | 27503323 | bellard | |
368 | 27503323 | bellard | mask = 1 << ichan;
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369 | 27503323 | bellard | |
370 | 492c30af | aliguori | if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) { |
371 | 27503323 | bellard | channel_run (icont, ichan); |
372 | 492c30af | aliguori | rearm = 1;
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373 | 492c30af | aliguori | } |
374 | 27503323 | bellard | } |
375 | 27503323 | bellard | } |
376 | 492c30af | aliguori | |
377 | 492c30af | aliguori | if (rearm)
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378 | 492c30af | aliguori | qemu_bh_schedule_idle(dma_bh); |
379 | 492c30af | aliguori | } |
380 | 492c30af | aliguori | |
381 | 492c30af | aliguori | static void DMA_run_bh(void *unused) |
382 | 492c30af | aliguori | { |
383 | 492c30af | aliguori | DMA_run(); |
384 | 27503323 | bellard | } |
385 | 27503323 | bellard | |
386 | 27503323 | bellard | void DMA_register_channel (int nchan, |
387 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
388 | 16f62432 | bellard | void *opaque)
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389 | 27503323 | bellard | { |
390 | 27503323 | bellard | struct dma_regs *r;
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391 | 27503323 | bellard | int ichan, ncont;
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392 | 27503323 | bellard | |
393 | 27503323 | bellard | ncont = nchan > 3;
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394 | 27503323 | bellard | ichan = nchan & 3;
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395 | 27503323 | bellard | |
396 | 27503323 | bellard | r = dma_controllers[ncont].regs + ichan; |
397 | 16f62432 | bellard | r->transfer_handler = transfer_handler; |
398 | 16f62432 | bellard | r->opaque = opaque; |
399 | 16f62432 | bellard | } |
400 | 16f62432 | bellard | |
401 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int len) |
402 | 85571bc7 | bellard | { |
403 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
404 | 71db710f | blueswir1 | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
405 | 85571bc7 | bellard | |
406 | 85571bc7 | bellard | if (r->mode & 0x20) { |
407 | 85571bc7 | bellard | int i;
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408 | 85571bc7 | bellard | uint8_t *p = buf; |
409 | 85571bc7 | bellard | |
410 | 85571bc7 | bellard | cpu_physical_memory_read (addr - pos - len, buf, len); |
411 | 85571bc7 | bellard | /* What about 16bit transfers? */
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412 | 85571bc7 | bellard | for (i = 0; i < len >> 1; i++) { |
413 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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414 | 85571bc7 | bellard | p[i] = b; |
415 | 85571bc7 | bellard | } |
416 | 85571bc7 | bellard | } |
417 | 85571bc7 | bellard | else
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418 | 85571bc7 | bellard | cpu_physical_memory_read (addr + pos, buf, len); |
419 | 85571bc7 | bellard | |
420 | 85571bc7 | bellard | return len;
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421 | 85571bc7 | bellard | } |
422 | 85571bc7 | bellard | |
423 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int len) |
424 | 85571bc7 | bellard | { |
425 | 85571bc7 | bellard | struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3]; |
426 | 71db710f | blueswir1 | target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR]; |
427 | 85571bc7 | bellard | |
428 | 85571bc7 | bellard | if (r->mode & 0x20) { |
429 | 85571bc7 | bellard | int i;
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430 | 85571bc7 | bellard | uint8_t *p = buf; |
431 | 85571bc7 | bellard | |
432 | 85571bc7 | bellard | cpu_physical_memory_write (addr - pos - len, buf, len); |
433 | 85571bc7 | bellard | /* What about 16bit transfers? */
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434 | 85571bc7 | bellard | for (i = 0; i < len; i++) { |
435 | 85571bc7 | bellard | uint8_t b = p[len - i - 1];
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436 | 85571bc7 | bellard | p[i] = b; |
437 | 85571bc7 | bellard | } |
438 | 85571bc7 | bellard | } |
439 | 85571bc7 | bellard | else
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440 | 85571bc7 | bellard | cpu_physical_memory_write (addr + pos, buf, len); |
441 | 85571bc7 | bellard | |
442 | 85571bc7 | bellard | return len;
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443 | 85571bc7 | bellard | } |
444 | 85571bc7 | bellard | |
445 | 16f62432 | bellard | /* request the emulator to transfer a new DMA memory block ASAP */
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446 | 16f62432 | bellard | void DMA_schedule(int nchan) |
447 | 16f62432 | bellard | { |
448 | c68ea704 | bellard | CPUState *env = cpu_single_env; |
449 | c68ea704 | bellard | if (env)
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450 | 3098dba0 | aurel32 | cpu_exit(env); |
451 | 27503323 | bellard | } |
452 | 27503323 | bellard | |
453 | d7d02e3c | bellard | static void dma_reset(void *opaque) |
454 | d7d02e3c | bellard | { |
455 | d7d02e3c | bellard | struct dma_cont *d = opaque;
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456 | d7d02e3c | bellard | write_cont (d, (0x0d << d->dshift), 0); |
457 | d7d02e3c | bellard | } |
458 | d7d02e3c | bellard | |
459 | ca9cc28c | balrog | static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) |
460 | ca9cc28c | balrog | { |
461 | ca9cc28c | balrog | dolog ("unregistered DMA channel used nchan=%d dma_pos=%d dma_len=%d\n",
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462 | ca9cc28c | balrog | nchan, dma_pos, dma_len); |
463 | ca9cc28c | balrog | return dma_pos;
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464 | ca9cc28c | balrog | } |
465 | ca9cc28c | balrog | |
466 | 9eb153f1 | bellard | /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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467 | 85571bc7 | bellard | static void dma_init2(struct dma_cont *d, int base, int dshift, |
468 | b0bda528 | bellard | int page_base, int pageh_base) |
469 | 27503323 | bellard | { |
470 | d70040bc | pbrook | static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
471 | 27503323 | bellard | int i;
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472 | 27503323 | bellard | |
473 | 9eb153f1 | bellard | d->dshift = dshift; |
474 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
475 | 9eb153f1 | bellard | register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
476 | 9eb153f1 | bellard | register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
477 | 27503323 | bellard | } |
478 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE (page_port_list); i++) { |
479 | 85571bc7 | bellard | register_ioport_write (page_base + page_port_list[i], 1, 1, |
480 | 9eb153f1 | bellard | write_page, d); |
481 | 85571bc7 | bellard | register_ioport_read (page_base + page_port_list[i], 1, 1, |
482 | 9eb153f1 | bellard | read_page, d); |
483 | b0bda528 | bellard | if (pageh_base >= 0) { |
484 | 85571bc7 | bellard | register_ioport_write (pageh_base + page_port_list[i], 1, 1, |
485 | b0bda528 | bellard | write_pageh, d); |
486 | 85571bc7 | bellard | register_ioport_read (pageh_base + page_port_list[i], 1, 1, |
487 | b0bda528 | bellard | read_pageh, d); |
488 | b0bda528 | bellard | } |
489 | 27503323 | bellard | } |
490 | 27503323 | bellard | for (i = 0; i < 8; i++) { |
491 | 85571bc7 | bellard | register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
492 | 9eb153f1 | bellard | write_cont, d); |
493 | 85571bc7 | bellard | register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
494 | 9eb153f1 | bellard | read_cont, d); |
495 | 27503323 | bellard | } |
496 | 8217606e | Jan Kiszka | qemu_register_reset(dma_reset, 0, d);
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497 | d7d02e3c | bellard | dma_reset(d); |
498 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { |
499 | ca9cc28c | balrog | d->regs[i].transfer_handler = dma_phony_handler; |
500 | ca9cc28c | balrog | } |
501 | 9eb153f1 | bellard | } |
502 | 27503323 | bellard | |
503 | 85571bc7 | bellard | static void dma_save (QEMUFile *f, void *opaque) |
504 | 85571bc7 | bellard | { |
505 | 85571bc7 | bellard | struct dma_cont *d = opaque;
|
506 | 85571bc7 | bellard | int i;
|
507 | 85571bc7 | bellard | |
508 | 85571bc7 | bellard | /* qemu_put_8s (f, &d->status); */
|
509 | 85571bc7 | bellard | qemu_put_8s (f, &d->command); |
510 | 85571bc7 | bellard | qemu_put_8s (f, &d->mask); |
511 | 85571bc7 | bellard | qemu_put_8s (f, &d->flip_flop); |
512 | bee8d684 | ths | qemu_put_be32 (f, d->dshift); |
513 | 85571bc7 | bellard | |
514 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
515 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
|
516 | bee8d684 | ths | qemu_put_be32 (f, r->now[0]);
|
517 | bee8d684 | ths | qemu_put_be32 (f, r->now[1]);
|
518 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[0]);
|
519 | 85571bc7 | bellard | qemu_put_be16s (f, &r->base[1]);
|
520 | 85571bc7 | bellard | qemu_put_8s (f, &r->mode); |
521 | 85571bc7 | bellard | qemu_put_8s (f, &r->page); |
522 | 85571bc7 | bellard | qemu_put_8s (f, &r->pageh); |
523 | 85571bc7 | bellard | qemu_put_8s (f, &r->dack); |
524 | 85571bc7 | bellard | qemu_put_8s (f, &r->eop); |
525 | 85571bc7 | bellard | } |
526 | 85571bc7 | bellard | } |
527 | 85571bc7 | bellard | |
528 | 85571bc7 | bellard | static int dma_load (QEMUFile *f, void *opaque, int version_id) |
529 | 85571bc7 | bellard | { |
530 | 85571bc7 | bellard | struct dma_cont *d = opaque;
|
531 | 85571bc7 | bellard | int i;
|
532 | 85571bc7 | bellard | |
533 | 85571bc7 | bellard | if (version_id != 1) |
534 | 85571bc7 | bellard | return -EINVAL;
|
535 | 85571bc7 | bellard | |
536 | 85571bc7 | bellard | /* qemu_get_8s (f, &d->status); */
|
537 | 85571bc7 | bellard | qemu_get_8s (f, &d->command); |
538 | 85571bc7 | bellard | qemu_get_8s (f, &d->mask); |
539 | 85571bc7 | bellard | qemu_get_8s (f, &d->flip_flop); |
540 | bee8d684 | ths | d->dshift=qemu_get_be32 (f); |
541 | 85571bc7 | bellard | |
542 | 85571bc7 | bellard | for (i = 0; i < 4; ++i) { |
543 | 85571bc7 | bellard | struct dma_regs *r = &d->regs[i];
|
544 | bee8d684 | ths | r->now[0]=qemu_get_be32 (f);
|
545 | bee8d684 | ths | r->now[1]=qemu_get_be32 (f);
|
546 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[0]);
|
547 | 85571bc7 | bellard | qemu_get_be16s (f, &r->base[1]);
|
548 | 85571bc7 | bellard | qemu_get_8s (f, &r->mode); |
549 | 85571bc7 | bellard | qemu_get_8s (f, &r->page); |
550 | 85571bc7 | bellard | qemu_get_8s (f, &r->pageh); |
551 | 85571bc7 | bellard | qemu_get_8s (f, &r->dack); |
552 | 85571bc7 | bellard | qemu_get_8s (f, &r->eop); |
553 | 85571bc7 | bellard | } |
554 | 492c30af | aliguori | |
555 | 492c30af | aliguori | DMA_run(); |
556 | 492c30af | aliguori | |
557 | 85571bc7 | bellard | return 0; |
558 | 85571bc7 | bellard | } |
559 | 85571bc7 | bellard | |
560 | b0bda528 | bellard | void DMA_init (int high_page_enable) |
561 | 9eb153f1 | bellard | { |
562 | 85571bc7 | bellard | dma_init2(&dma_controllers[0], 0x00, 0, 0x80, |
563 | b0bda528 | bellard | high_page_enable ? 0x480 : -1); |
564 | b0bda528 | bellard | dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, |
565 | b0bda528 | bellard | high_page_enable ? 0x488 : -1); |
566 | 85571bc7 | bellard | register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]); |
567 | 85571bc7 | bellard | register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]); |
568 | 492c30af | aliguori | |
569 | 492c30af | aliguori | dma_bh = qemu_bh_new(DMA_run_bh, NULL);
|
570 | 27503323 | bellard | } |