tcg-arm: Tidy variable naming convention in qemu_ld/st
s/addr_reg2/addrhi/s/addr_reg/addrlo/s/data_reg2/datahi/s/data_reg/datalo/
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Convert to new ldst opcodes
tcg: Use TCGMemOp for TCGLabelQemuLdst.opc
tcg-i386: Use TCGMemOp within qemu_ldst routines
Step one in the transition, with constants passed down from tcg_out_op.
tcg-i386: Tidy softmmu routines
Pass two TCGReg to tcg_out_tlb_load, rather than idx+args.
Move ldst_optimization routines just below tcg_out_tlb_load to avoidthe need for forward declarations.
Use TCGReg enum in preference to int where apprpriate.
tcg-i386: Remove "cb" output restriction from qemu_st8 for i386
Once we form a combined qemu_st_i32 opcode, we won't be able tohave separate constraints based on size. This one is fairly easyto work around, since eax is available as a scratch register....
tcg-i386: Support new ldst opcodes
No support for helpers with non-default endianness yet,but good enough to test the opcodes.
tcg-arm: Use TCGMemOp within qemu_ldst routines
tcg-arm: Convert to le/be ldst helpers
tcg: Add qemu_ld_st_i32/64
Step two in the transition, adding the new ldst opcodes. Keep the oldopcodes around until all backends support the new opcodes.
exec: Add both big- and little-endian memory helpers
Step three in the transition: helpers not tied to the target"default" endianness. To be used when the guest uses a memoryoperation with non-default endianness.
tcg: Add TCGMemOp
tcg: Add tcg-be-null.h
This is a no-op backend data implementation, for those targets thatare not currently using the load/store optimization path.
This is prepatory to always requiring these functions in all backends.
tcg: Add tcg-be-ldst.h
Move TCGLabelQemuLdst and related stuff out of tcg.h.
tcg: Put target helper data into an array.
One call inside of a loop to tcg_register_helper instead of hundredsof sequential calls.
Presumably more icache and branch prediction friendly; resulting binarysize mostly unchanged on x86_64, as we're trading 32-bit rip-relative...
tcg: Add tcg-runtime.c helpers to all_helpers
For the few targets that actually use these, we'd not reportthem symbolicly in the tcg opcode logs.
tcg: Merge tcg_register_helper into tcg_context_init
Eliminates the repeated checks for having createdthe s->helpers hash table.
tcg-aarch64: Update to helper_ret_*_mmu routines
A minimal update to use the new helpers with the return address argument.
Tested-by: Claudio Fontana <claudio.fontana@linaro.org>Reviewed-by: Claudio Fontana <claudio.fontana@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
tcg: Use a GHashTable for tcg_find_helper
Slightly changes the interface, in that we now return nameinstead of a TCGHelperInfo structure, which goes away.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Delete tcg_helper_get_name declaration
The function was deleted in 4dc81f2822187f4503d4bdb76785cafa5b28db0b.
tcg-hppa: Remove tcg backend
Merge remote-tracking branch 'rth/tcg-arm-pull' into staging
Merge remote-tracking branch 'sweil/tci' into staging
Message-id: 1380137693-3729-1-git-send-email-sw@weilnetz.de...
tcg-arm: Use ldrd/strd for appropriate qemu_ld/st64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Rearrange slow-path qemu_ld/st
Use the new helper_ret_*_mmu routines. Use a conditional callto arrange for a tail-call from the store path, and to load thereturn address for the helper for the load path.
tcg-arm: Use strd for tcg_out_arg_reg64
tcg-arm: Use QEMU_BUILD_BUG_ON to verify constraints on tlb
One of the two constraints we already checked via #if, butthe tlb offset distance was only checked at runtime.
tcg-arm: Move load of tlb addend into tcg_out_tlb_read
This allows us to make more intelligent decisions about the relativeoffsets of the tlb comparator and the addend, avoiding any need ofwriteback addressing.
tcg-arm: Return register containing tlb addend
Preparatory to rescheduling the tlb load, and changing said register.Continues to use R1 for now.
tcg-arm: Remove restriction on qemu_ld output register
The main intent of the patch is to allow the tlb addend registerto be changed, without tying that change to the constraint. Butthe most common side-effect seems to be to enable usage of ldrdwith the r0,r1 pair....
tcg-arm: Move the tlb addend load earlier
There are free scheduling slots between the sequence ofcomparison instructions. This requires changing theregister in use to avoid conflict with those compares.
misc: Use new rotate functions
Signed-off-by: Stefan Weil <sw@weilnetz.de>
tci: Add implementation of rotl_i64, rotr_i64
It is used by qemu-ppc64 when running Debian's busybox-static.
Cc: qemu-stable <qemu-stable@nongnu.org>Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Richard Henderson <rth@twiddle.net>
tcg-ppc64: Implement CONFIG_QEMU_LDST_OPTIMIZATION
tcg-ppc64: More use of TAI and SAI helper macros
Finish conversion of all memory operations.
tcg-ppc64: Use TCG_REG_Rn constants
Instead of bare N, for clarity. The only (intentional) exception madeis for insns that encode R|0, i.e. when R0 encoded into the insn isinterpreted as zero not the contents of the register.
tcg-ppc64: Use tcg_out64
tcg-ppc64: Avoid code for nop move
While these are rare from code that's been through the optimizer,it's not uncommon within the tcg backend.
tcg-ppc64: Don't load the static chain from TCG
There are no helpers that require the static chain.
tcg-ppc64: Fold constant call address into descriptor load
Eliminates one insn per call:
: lis r2,4165: ori r2,r2,59616: ld r0,0(r2): ld r0,-5920(r2) : mtctr r0-: ld r2,8(r2): ld r2,-5912(r2) : bctrl
tcg-ppc64: Look through a constant function descriptor
Especially in the user-only configurations, a direct branch intothe executable may be in range.
tcg-ppc64: Tidy register allocation order
Remove conditionalization from tcg_target_reg_alloc_order, relying onreserved_regs to prevent register allocation that shouldn't happen.So R11 is now present in reg_alloc_order for APPLE, but also nowreserved....
tcg-ppc64: Handle long offsets better
Previously we'd only handle 16-bit offsets from memory operand without fallingback to indexed, but it's easy to use ADDIS to handle full 32-bit offsets.
This also lets us unify code that existed inline in tcg_out_op for handling...
tcg-ppc64: Implement tcg_register_jit
tcg-ppc64: Streamline tcg_out_tlb_read
Less conditional compilation. Merge an add insn with the indexedmemory load insn. Load the tlb addend earlier. Avoid the addressupdate memory form.
Fix a bug in not allowing large enough tlb offsets for some guests....
tcg-ppc64: Add _noaddr functions for emitting forward branches
... rather than open-coding this stuff through the file.
tcg-ppc: Avoid code for nop move
tcg-ppc: Cleanup tcg_out_qemu_ld/st_slow_path
Coding style fixes. Use TCGReg enumeration values instead of rawnumbers. Don't needlessly pull the whole TCGLabelQemuLdst structinto local variables. Less conditional compilation.
No functional changes....
tcg-ppc: Use conditional branch and link to slow path
Saves one insn per slow path. Note that we can no longer usea tail call into the store helper.
tcg-ppc: Fix and cleanup tcg_out_tlb_check
The fix is that sparc has so many mmu modes that the last one overflowedthe 16-bit signed offset we assumed would fit. Handle this, and checkthe new assumption at compile time.
Load the tlb addend earlier for the fast path....
tcg-ppc64: Reformat tcg-target.c
Whitespace and brace changes only.
tcg-ppc: use new return-argument ld/st helpers
These use a 32-bit load-of-immediate to save a mflr+addi+mtlr sequence.Tested with a Windows 98 guest (pretty much the most recent thing Icould run on my PPC machine) and kvm-unit-tests's sieve.flat. Thespeed up for sieve.flat is as high as 10% for qemu-system-i386, 25%...
tcg-ppc: fix qemu_ld/qemu_st for AIX ABI
For the AIX ABI, the function pointer and small area pointer needto be loaded in the trampoline. The trampoline instead is calledwith a normal BL instruction.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>...
tcg-sparc: Fix parenthesis warning
error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses]
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Merge remote-tracking branch 'mjt/trivial-patches' into staging
Merge branch 'tcg-next' of git://github.com/rth7680/qemu
tcg/mips: detect available host instructions at runtime
Now that TCG supports enabling and disabling ops at runtime, it'spossible to detect the available host instructions at runtime, andenable the corresponding ops accordingly.
Unfortunately it's not easy to probe for available instructions on...
tcg/mips: inline bswap16/bswap32 ops
Use an inline version for the bswap16 and bswap32 ops to avoidtesting for MIPS32R2 instructions availability, as these ops areonly available in that case.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/mips: only enable ext8s/ext16s ops on MIPS32R2
On MIPS ext8s and ext16s ops are implemented with a dedicatedinstruction only on MIPS32R2, otherwise the same kind of implementationthan at TCG level (shift left followed by shift right) is used.
Change that by only implementing the ext8s and ext16s ops on MIPS32R2 so...
tcg: Introduce zero and sign-extended versions of load helpers
tcg-i386: Make use of zero-extended memory helper routines
For 8 and 16-bit unsigned loads, rely on the zero-extensionfrom the helper and use a smaller 32-bit move insn.
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
tcg: Change tcg_out_ld/st offset to intptr_t
tcg: Use appropriate types in tcg_reg_alloc_call
tcg: Fix jit debug for x32
tcg-i386: Use intptr_t appropriately
tcg-i386: Adjust tcg_out_tlb_load for x32
tcg-i386: Don't perform GETPC adjustment in TCG code
Since we now perform it inside the helper, no need to do it here.This also lets us perform a tail-call from the store slow path tothe helper.
exec: Split softmmu_defs.h
The _cmmu helpers can be moved to exec-all.h. The helpers that areused from TCG will shortly need access to tcg_target_long so movetheir declarations into tcg.h.
This requires minor include adjustments to all TCG backends....
tcg: Add muluh and mulsh opcodes
Use them in places where mulu2 and muls2 are used.Optimize mulx2 with dead low part to mulxh.
tcg-mips: Implement mulsh, muluh
With the optimization in tcg_liveness_analysis,we can avoid the MFLO when it is unused.
tcg-ppc64: Implement muluh, mulsh
Using these instead of mulu2 and muls2 lets us avoid having to argumentoverlap analysis in the backend. Normal register allocation will DTRT.
tcg: Constant fold div, rem
tcg: Change flush_icache_range arguments to uintptr_t
tcg: Change tcg_qemu_tb_exec return to uintptr_t
tcg: Allow TCG_TARGET_REG_BITS to be specified independantly
There are several hosts for which it would be useful to use theavailable 64-bit registers in a 32-bit pointer environment.
tcg: Define TCG_TYPE_PTR properly
tcg: Define TCG_ptr properly
tcg: Change frame pointer offsets to intptr_t
tcg: Change memory offsets to intptr_t
tcg: Change relocation offsets to intptr_t
tcg: Use uintptr_t in TCGHelperInfo
tci: Remove function tcg_out64 (fix broken build)
Commit ac26eb69a311396668809eadbf7ff4e623447d4c added tcg_out64 to tcg/tcg.c.tcg/tci/tcg-target.c already had a nearly identical implementation which isnow removed to fix a compiler error.
Signed-off-by: Stefan Weil <sw@weilnetz.de>...
tcg-i386: Use new return-argument ld/st helpers
Discontinue the jump-around-jump-to-jump scheme, trading it for a singleimmediate move instruction. The two extra jumps always consume 7 bytes,whereas the immediate move is either 5 or 7 bytes depending on where the...
tcg: Tidy generated code for tcg_outN
Aliasing was forcing s->code_ptr to be re-read after the store.Keep the pointer in a local variable to help the compiler.
tcg-i386: Add and use tcg_out64
No point in splitting the write into 32-bit pieces.
tcg-i386: Try pc-relative lea for constant formation
Use a 7 byte lea before the ultimate 10 byte movq.
tcg-i386: Tidy qemu_ld/st slow path
Use existing stack space for arguments; don't push/pop.Use less ifdefs and more C ifs.
tcg/mips: fix invalid op definition errors
tcg/mips/tcg-target.h defines various operations conditionally dependingupon the isa revision, however these operations are included inmips_op_defs[] unconditionally resulting in the following runtime errorsif CONFIG_DEBUG_TCG is defined:...
tci: Fix broken build (compiler warning caused by redefined macro BIT)
The definition of macro BIT in tci/tcg-target.c now conflicts with thedefinition of the same macro in includes qemu/bitops.h.
This conflict was triggered by a recent change in the include chain of...
Merge git://github.com/hw-claudio/qemu-aarch64-queue into tcg-next
tcg/aarch64: Implement tlb lookup fast path
Supports CONFIG_QEMU_LDST_OPTIMIZATION
Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size
We can check the condition at compile time, rather than run time.
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-arm: Implement tcg_register_jit
Allows unwinding past the code_gen_buffer.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Fix high_pc fields in .debug_info
I don't think the debugger actually looks at this for anything,using the correct .debug_frame contents, but might as well getit all correct.
tcg: Move the CIE and FDE header definitions to common code
These will necessarily be the same layout for all hosts. This limitsthe amount of boilerplate required to implement jit debug for a host.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
tcg-arm: Use AT_PLATFORM to detect the host ISA
With this we can generate armv7 insns even when the OS compiles for alower common denominator. The macros are arranged so that when we docompile for a given ISA, all of the runtime checks for that ISA are...
tcg-arm: Simplify logic in detecting the ARM ISA in use
GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, whichwill make us nicely forward compatible with ARMv8 AArch32.
tcg-arm: Rename use_armv5_instructions to use_armvt5_instructions
As it really controls the availability of a thumb interworkinginstruction on armv5t.