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/*
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* Toshiba TC6393XB I/O Controller.
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* Found in Sharp Zaurus SL-6000 (tosa) or some
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* Toshiba e-Series PDAs.
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*
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* Most features are currently unsupported!!!
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h" |
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#include "pxa.h" |
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#include "devices.h" |
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#include "flash.h" |
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#include "console.h" |
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#include "pixel_ops.h" |
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|
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#define IRQ_TC6393_NAND 0 |
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#define IRQ_TC6393_MMC 1 |
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#define IRQ_TC6393_OHCI 2 |
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#define IRQ_TC6393_SERIAL 3 |
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#define IRQ_TC6393_FB 4 |
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|
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#define TC6393XB_NR_IRQS 8 |
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|
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#define TC6393XB_GPIOS 16 |
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|
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#define SCR_REVID 0x08 /* b Revision ID */ |
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#define SCR_ISR 0x50 /* b Interrupt Status */ |
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#define SCR_IMR 0x52 /* b Interrupt Mask */ |
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#define SCR_IRR 0x54 /* b Interrupt Routing */ |
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#define SCR_GPER 0x60 /* w GP Enable */ |
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#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ |
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#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ |
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#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ |
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#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ |
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#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ |
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#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ |
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#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ |
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#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ |
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#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ |
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#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ |
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#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ |
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#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ |
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#define SCR_CCR 0x98 /* w Clock Control */ |
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#define SCR_PLL2CR 0x9a /* w PLL2 Control */ |
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#define SCR_PLL1CR 0x9c /* l PLL1 Control */ |
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#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ |
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#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ |
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#define SCR_FER 0xe0 /* b Function Enable */ |
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#define SCR_MCR 0xe4 /* w Mode Control */ |
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#define SCR_CONFIG 0xfc /* b Configuration Control */ |
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#define SCR_DEBUG 0xff /* b Debug */ |
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|
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#define NAND_CFG_COMMAND 0x04 /* w Command */ |
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#define NAND_CFG_BASE 0x10 /* l Control Base Address */ |
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#define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ |
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#define NAND_CFG_INTE 0x48 /* b Int Enable */ |
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#define NAND_CFG_EC 0x4a /* b Event Control */ |
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#define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ |
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#define NAND_CFG_ECCC 0x5b /* b ECC Control */ |
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#define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ |
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#define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ |
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#define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ |
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#define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ |
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|
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#define NAND_DATA 0x00 /* l Data */ |
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#define NAND_MODE 0x04 /* b Mode */ |
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#define NAND_STATUS 0x05 /* b Status */ |
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#define NAND_ISR 0x06 /* b Interrupt Status */ |
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#define NAND_IMR 0x07 /* b Interrupt Mask */ |
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|
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#define NAND_MODE_WP 0x80 |
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#define NAND_MODE_CE 0x10 |
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#define NAND_MODE_ALE 0x02 |
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#define NAND_MODE_CLE 0x01 |
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#define NAND_MODE_ECC_MASK 0x60 |
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#define NAND_MODE_ECC_EN 0x20 |
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#define NAND_MODE_ECC_READ 0x40 |
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#define NAND_MODE_ECC_RST 0x60 |
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struct TC6393xbState {
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qemu_irq irq; |
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qemu_irq *sub_irqs; |
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struct {
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uint8_t ISR; |
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uint8_t IMR; |
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uint8_t IRR; |
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uint16_t GPER; |
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uint8_t GPI_SR[3];
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uint8_t GPI_IMR[3];
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uint8_t GPI_EDER[3];
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uint8_t GPI_LIR[3];
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uint8_t GP_IARCR[3];
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uint8_t GP_IARLCR[3];
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uint8_t GPI_BCR[3];
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uint16_t GPA_IARCR; |
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uint16_t GPA_IARLCR; |
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uint16_t CCR; |
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uint16_t PLL2CR; |
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uint32_t PLL1CR; |
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uint8_t DIARCR; |
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uint8_t DBOCR; |
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uint8_t FER; |
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uint16_t MCR; |
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uint8_t CONFIG; |
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uint8_t DEBUG; |
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} scr; |
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uint32_t gpio_dir; |
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uint32_t gpio_level; |
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uint32_t prev_level; |
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qemu_irq handler[TC6393XB_GPIOS]; |
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qemu_irq *gpio_in; |
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struct {
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uint8_t mode; |
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uint8_t isr; |
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uint8_t imr; |
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} nand; |
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int nand_enable;
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uint32_t nand_phys; |
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NANDFlashState *flash; |
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ECCState ecc; |
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DisplayState *ds; |
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ram_addr_t vram_addr; |
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uint16_t *vram_ptr; |
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uint32_t scr_width, scr_height; /* in pixels */
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qemu_irq l3v; |
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unsigned blank : 1, |
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blanked : 1;
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}; |
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qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) |
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{ |
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return s->gpio_in;
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} |
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static void tc6393xb_gpio_set(void *opaque, int line, int level) |
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{ |
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// TC6393xbState *s = opaque;
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if (line > TC6393XB_GPIOS) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return;
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} |
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// FIXME: how does the chip reflect the GPIO input level change?
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} |
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void tc6393xb_gpio_out_set(TC6393xbState *s, int line, |
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qemu_irq handler) |
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{ |
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if (line >= TC6393XB_GPIOS) {
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fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
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return;
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} |
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s->handler[line] = handler; |
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} |
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static void tc6393xb_gpio_handler_update(TC6393xbState *s) |
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{ |
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uint32_t level, diff; |
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int bit;
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level = s->gpio_level & s->gpio_dir; |
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { |
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bit = ffs(diff) - 1;
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qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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} |
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s->prev_level = level; |
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} |
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qemu_irq tc6393xb_l3v_get(TC6393xbState *s) |
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{ |
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return s->l3v;
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} |
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static void tc6393xb_l3v(void *opaque, int line, int level) |
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{ |
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TC6393xbState *s = opaque; |
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s->blank = !level; |
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fprintf(stderr, "L3V: %d\n", level);
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} |
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static void tc6393xb_sub_irq(void *opaque, int line, int level) { |
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TC6393xbState *s = opaque; |
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uint8_t isr = s->scr.ISR; |
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if (level)
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isr |= 1 << line;
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else
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isr &= ~(1 << line);
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s->scr.ISR = isr; |
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qemu_set_irq(s->irq, isr & s->scr.IMR); |
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} |
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#define SCR_REG_B(N) \
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case SCR_ ##N: return s->scr.N |
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#define SCR_REG_W(N) \
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case SCR_ ##N: return s->scr.N; \ |
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case SCR_ ##N + 1: return s->scr.N >> 8; |
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#define SCR_REG_L(N) \
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case SCR_ ##N: return s->scr.N; \ |
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case SCR_ ##N + 1: return s->scr.N >> 8; \ |
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case SCR_ ##N + 2: return s->scr.N >> 16; \ |
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case SCR_ ##N + 3: return s->scr.N >> 24; |
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): return s->scr.N[0]; \ |
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case SCR_ ##N(1): return s->scr.N[1]; \ |
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case SCR_ ##N(2): return s->scr.N[2] |
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static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
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{ |
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switch (addr) {
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case SCR_REVID:
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return 3; |
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case SCR_REVID+1: |
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return 0; |
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SCR_REG_B(ISR); |
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SCR_REG_B(IMR); |
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SCR_REG_B(IRR); |
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SCR_REG_W(GPER); |
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SCR_REG_A(GPI_SR); |
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SCR_REG_A(GPI_IMR); |
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SCR_REG_A(GPI_EDER); |
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SCR_REG_A(GPI_LIR); |
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case SCR_GPO_DSR(0): |
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case SCR_GPO_DSR(1): |
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case SCR_GPO_DSR(2): |
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return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; |
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case SCR_GPO_DOECR(0): |
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case SCR_GPO_DOECR(1): |
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case SCR_GPO_DOECR(2): |
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return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; |
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SCR_REG_A(GP_IARCR); |
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SCR_REG_A(GP_IARLCR); |
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SCR_REG_A(GPI_BCR); |
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SCR_REG_W(GPA_IARCR); |
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SCR_REG_W(GPA_IARLCR); |
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SCR_REG_W(CCR); |
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SCR_REG_W(PLL2CR); |
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SCR_REG_L(PLL1CR); |
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SCR_REG_B(DIARCR); |
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SCR_REG_B(DBOCR); |
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SCR_REG_B(FER); |
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SCR_REG_W(MCR); |
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SCR_REG_B(CONFIG); |
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SCR_REG_B(DEBUG); |
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} |
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fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr);
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return 0; |
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} |
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#undef SCR_REG_B
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#undef SCR_REG_W
|
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#undef SCR_REG_L
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#undef SCR_REG_A
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|
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#define SCR_REG_B(N) \
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case SCR_ ##N: s->scr.N = value; return; |
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#define SCR_REG_W(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return |
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#define SCR_REG_L(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ |
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case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ |
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case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; |
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): s->scr.N[0] = value; return; \ |
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case SCR_ ##N(1): s->scr.N[1] = value; return; \ |
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case SCR_ ##N(2): s->scr.N[2] = value; return |
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|
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static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) |
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{ |
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switch (addr) {
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SCR_REG_B(ISR); |
279 |
SCR_REG_B(IMR); |
280 |
SCR_REG_B(IRR); |
281 |
SCR_REG_W(GPER); |
282 |
SCR_REG_A(GPI_SR); |
283 |
SCR_REG_A(GPI_IMR); |
284 |
SCR_REG_A(GPI_EDER); |
285 |
SCR_REG_A(GPI_LIR); |
286 |
case SCR_GPO_DSR(0): |
287 |
case SCR_GPO_DSR(1): |
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case SCR_GPO_DSR(2): |
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s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); |
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tc6393xb_gpio_handler_update(s); |
291 |
return;
|
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case SCR_GPO_DOECR(0): |
293 |
case SCR_GPO_DOECR(1): |
294 |
case SCR_GPO_DOECR(2): |
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s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); |
296 |
tc6393xb_gpio_handler_update(s); |
297 |
return;
|
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SCR_REG_A(GP_IARCR); |
299 |
SCR_REG_A(GP_IARLCR); |
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SCR_REG_A(GPI_BCR); |
301 |
SCR_REG_W(GPA_IARCR); |
302 |
SCR_REG_W(GPA_IARLCR); |
303 |
SCR_REG_W(CCR); |
304 |
SCR_REG_W(PLL2CR); |
305 |
SCR_REG_L(PLL1CR); |
306 |
SCR_REG_B(DIARCR); |
307 |
SCR_REG_B(DBOCR); |
308 |
SCR_REG_B(FER); |
309 |
SCR_REG_W(MCR); |
310 |
SCR_REG_B(CONFIG); |
311 |
SCR_REG_B(DEBUG); |
312 |
} |
313 |
fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n",
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(uint32_t) addr, value & 0xff);
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} |
316 |
#undef SCR_REG_B
|
317 |
#undef SCR_REG_W
|
318 |
#undef SCR_REG_L
|
319 |
#undef SCR_REG_A
|
320 |
|
321 |
static void tc6393xb_nand_irq(TC6393xbState *s) { |
322 |
qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], |
323 |
(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
|
324 |
} |
325 |
|
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static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
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327 |
switch (addr) {
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case NAND_CFG_COMMAND:
|
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return s->nand_enable ? 2 : 0; |
330 |
case NAND_CFG_BASE:
|
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case NAND_CFG_BASE + 1: |
332 |
case NAND_CFG_BASE + 2: |
333 |
case NAND_CFG_BASE + 3: |
334 |
return s->nand_phys >> (addr - NAND_CFG_BASE);
|
335 |
} |
336 |
fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
|
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return 0; |
338 |
} |
339 |
static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { |
340 |
switch (addr) {
|
341 |
case NAND_CFG_COMMAND:
|
342 |
s->nand_enable = (value & 0x2);
|
343 |
return;
|
344 |
case NAND_CFG_BASE:
|
345 |
case NAND_CFG_BASE + 1: |
346 |
case NAND_CFG_BASE + 2: |
347 |
case NAND_CFG_BASE + 3: |
348 |
s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); |
349 |
s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); |
350 |
return;
|
351 |
} |
352 |
fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n",
|
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(uint32_t) addr, value & 0xff);
|
354 |
} |
355 |
|
356 |
static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
|
357 |
switch (addr) {
|
358 |
case NAND_DATA + 0: |
359 |
case NAND_DATA + 1: |
360 |
case NAND_DATA + 2: |
361 |
case NAND_DATA + 3: |
362 |
return nand_getio(s->flash);
|
363 |
case NAND_MODE:
|
364 |
return s->nand.mode;
|
365 |
case NAND_STATUS:
|
366 |
return 0x14; |
367 |
case NAND_ISR:
|
368 |
return s->nand.isr;
|
369 |
case NAND_IMR:
|
370 |
return s->nand.imr;
|
371 |
} |
372 |
fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
|
373 |
return 0; |
374 |
} |
375 |
static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) { |
376 |
// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
|
377 |
// (uint32_t) addr, value & 0xff);
|
378 |
switch (addr) {
|
379 |
case NAND_DATA + 0: |
380 |
case NAND_DATA + 1: |
381 |
case NAND_DATA + 2: |
382 |
case NAND_DATA + 3: |
383 |
nand_setio(s->flash, value); |
384 |
s->nand.isr &= 1;
|
385 |
tc6393xb_nand_irq(s); |
386 |
return;
|
387 |
case NAND_MODE:
|
388 |
s->nand.mode = value; |
389 |
nand_setpins(s->flash, |
390 |
value & NAND_MODE_CLE, |
391 |
value & NAND_MODE_ALE, |
392 |
!(value & NAND_MODE_CE), |
393 |
value & NAND_MODE_WP, |
394 |
0); // FIXME: gnd |
395 |
switch (value & NAND_MODE_ECC_MASK) {
|
396 |
case NAND_MODE_ECC_RST:
|
397 |
ecc_reset(&s->ecc); |
398 |
break;
|
399 |
case NAND_MODE_ECC_READ:
|
400 |
// FIXME
|
401 |
break;
|
402 |
case NAND_MODE_ECC_EN:
|
403 |
ecc_reset(&s->ecc); |
404 |
} |
405 |
return;
|
406 |
case NAND_ISR:
|
407 |
s->nand.isr = value; |
408 |
tc6393xb_nand_irq(s); |
409 |
return;
|
410 |
case NAND_IMR:
|
411 |
s->nand.imr = value; |
412 |
tc6393xb_nand_irq(s); |
413 |
return;
|
414 |
} |
415 |
fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n",
|
416 |
(uint32_t) addr, value & 0xff);
|
417 |
} |
418 |
|
419 |
#define BITS 8 |
420 |
#include "tc6393xb_template.h" |
421 |
#define BITS 15 |
422 |
#include "tc6393xb_template.h" |
423 |
#define BITS 16 |
424 |
#include "tc6393xb_template.h" |
425 |
#define BITS 24 |
426 |
#include "tc6393xb_template.h" |
427 |
#define BITS 32 |
428 |
#include "tc6393xb_template.h" |
429 |
|
430 |
static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) |
431 |
{ |
432 |
switch (ds_get_bits_per_pixel(s->ds)) {
|
433 |
case 8: |
434 |
tc6393xb_draw_graphic8(s); |
435 |
break;
|
436 |
case 15: |
437 |
tc6393xb_draw_graphic15(s); |
438 |
break;
|
439 |
case 16: |
440 |
tc6393xb_draw_graphic16(s); |
441 |
break;
|
442 |
case 24: |
443 |
tc6393xb_draw_graphic24(s); |
444 |
break;
|
445 |
case 32: |
446 |
tc6393xb_draw_graphic32(s); |
447 |
break;
|
448 |
default:
|
449 |
printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
|
450 |
return;
|
451 |
} |
452 |
|
453 |
dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
454 |
} |
455 |
|
456 |
static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) |
457 |
{ |
458 |
int i, w;
|
459 |
uint8_t *d; |
460 |
|
461 |
if (!full_update)
|
462 |
return;
|
463 |
|
464 |
w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); |
465 |
d = ds_get_data(s->ds); |
466 |
for(i = 0; i < s->scr_height; i++) { |
467 |
memset(d, 0, w);
|
468 |
d += ds_get_linesize(s->ds); |
469 |
} |
470 |
|
471 |
dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
472 |
} |
473 |
|
474 |
static void tc6393xb_update_display(void *opaque) |
475 |
{ |
476 |
TC6393xbState *s = opaque; |
477 |
int full_update;
|
478 |
|
479 |
if (s->scr_width == 0 || s->scr_height == 0) |
480 |
return;
|
481 |
|
482 |
full_update = 0;
|
483 |
if (s->blanked != s->blank) {
|
484 |
s->blanked = s->blank; |
485 |
full_update = 1;
|
486 |
} |
487 |
if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
|
488 |
qemu_console_resize(s->ds, s->scr_width, s->scr_height); |
489 |
full_update = 1;
|
490 |
} |
491 |
if (s->blanked)
|
492 |
tc6393xb_draw_blank(s, full_update); |
493 |
else
|
494 |
tc6393xb_draw_graphic(s, full_update); |
495 |
} |
496 |
|
497 |
|
498 |
static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { |
499 |
TC6393xbState *s = opaque; |
500 |
|
501 |
switch (addr >> 8) { |
502 |
case 0: |
503 |
return tc6393xb_scr_readb(s, addr & 0xff); |
504 |
case 1: |
505 |
return tc6393xb_nand_cfg_readb(s, addr & 0xff); |
506 |
}; |
507 |
|
508 |
if ((addr &~0xff) == s->nand_phys && s->nand_enable) { |
509 |
// return tc6393xb_nand_readb(s, addr & 0xff);
|
510 |
uint8_t d = tc6393xb_nand_readb(s, addr & 0xff);
|
511 |
// fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d);
|
512 |
return d;
|
513 |
} |
514 |
|
515 |
// fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
|
516 |
return 0; |
517 |
} |
518 |
|
519 |
static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { |
520 |
TC6393xbState *s = opaque; |
521 |
|
522 |
switch (addr >> 8) { |
523 |
case 0: |
524 |
tc6393xb_scr_writeb(s, addr & 0xff, value);
|
525 |
return;
|
526 |
case 1: |
527 |
tc6393xb_nand_cfg_writeb(s, addr & 0xff, value);
|
528 |
return;
|
529 |
}; |
530 |
|
531 |
if ((addr &~0xff) == s->nand_phys && s->nand_enable) |
532 |
tc6393xb_nand_writeb(s, addr & 0xff, value);
|
533 |
else
|
534 |
fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
|
535 |
(uint32_t) addr, value & 0xff);
|
536 |
} |
537 |
|
538 |
static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr) |
539 |
{ |
540 |
return (tc6393xb_readb(opaque, addr) & 0xff) | |
541 |
(tc6393xb_readb(opaque, addr + 1) << 8); |
542 |
} |
543 |
|
544 |
static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) |
545 |
{ |
546 |
return (tc6393xb_readb(opaque, addr) & 0xff) | |
547 |
((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) | |
548 |
((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) | |
549 |
((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24); |
550 |
} |
551 |
|
552 |
static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
553 |
{ |
554 |
tc6393xb_writeb(opaque, addr, value); |
555 |
tc6393xb_writeb(opaque, addr + 1, value >> 8); |
556 |
} |
557 |
|
558 |
static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value) |
559 |
{ |
560 |
tc6393xb_writeb(opaque, addr, value); |
561 |
tc6393xb_writeb(opaque, addr + 1, value >> 8); |
562 |
tc6393xb_writeb(opaque, addr + 2, value >> 16); |
563 |
tc6393xb_writeb(opaque, addr + 3, value >> 24); |
564 |
} |
565 |
|
566 |
TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) |
567 |
{ |
568 |
int iomemtype;
|
569 |
TC6393xbState *s; |
570 |
CPUReadMemoryFunc * const tc6393xb_readfn[] = {
|
571 |
tc6393xb_readb, |
572 |
tc6393xb_readw, |
573 |
tc6393xb_readl, |
574 |
}; |
575 |
CPUWriteMemoryFunc * const tc6393xb_writefn[] = {
|
576 |
tc6393xb_writeb, |
577 |
tc6393xb_writew, |
578 |
tc6393xb_writel, |
579 |
}; |
580 |
|
581 |
s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState));
|
582 |
s->irq = irq; |
583 |
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); |
584 |
|
585 |
s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
|
586 |
s->blanked = 1;
|
587 |
|
588 |
s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); |
589 |
|
590 |
s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
|
591 |
|
592 |
iomemtype = cpu_register_io_memory(tc6393xb_readfn, |
593 |
tc6393xb_writefn, s); |
594 |
cpu_register_physical_memory(base, 0x10000, iomemtype);
|
595 |
|
596 |
s->vram_addr = qemu_ram_alloc(0x100000);
|
597 |
s->vram_ptr = qemu_get_ram_ptr(s->vram_addr); |
598 |
cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr); |
599 |
s->scr_width = 480;
|
600 |
s->scr_height = 640;
|
601 |
s->ds = graphic_console_init(tc6393xb_update_display, |
602 |
NULL, /* invalidate */ |
603 |
NULL, /* screen_dump */ |
604 |
NULL, /* text_update */ |
605 |
s); |
606 |
|
607 |
return s;
|
608 |
} |