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1 | 81fdc5f8 | ths | /*
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2 | 81fdc5f8 | ths | * CRIS helper routines.
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3 | 81fdc5f8 | ths | *
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4 | 81fdc5f8 | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 81fdc5f8 | ths | * Written by Edgar E. Iglesias.
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6 | 81fdc5f8 | ths | *
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7 | 81fdc5f8 | ths | * This library is free software; you can redistribute it and/or
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8 | 81fdc5f8 | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 81fdc5f8 | ths | * License as published by the Free Software Foundation; either
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10 | 81fdc5f8 | ths | * version 2 of the License, or (at your option) any later version.
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11 | 81fdc5f8 | ths | *
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12 | 81fdc5f8 | ths | * This library is distributed in the hope that it will be useful,
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13 | 81fdc5f8 | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 81fdc5f8 | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 81fdc5f8 | ths | * Lesser General Public License for more details.
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16 | 81fdc5f8 | ths | *
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17 | 81fdc5f8 | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 81fdc5f8 | ths | */
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20 | 81fdc5f8 | ths | |
21 | 81fdc5f8 | ths | #include <stdio.h> |
22 | 81fdc5f8 | ths | #include <string.h> |
23 | 81fdc5f8 | ths | |
24 | 81fdc5f8 | ths | #include "config.h" |
25 | 81fdc5f8 | ths | #include "cpu.h" |
26 | 81fdc5f8 | ths | #include "mmu.h" |
27 | 81fdc5f8 | ths | #include "exec-all.h" |
28 | 941db528 | ths | #include "host-utils.h" |
29 | 81fdc5f8 | ths | |
30 | d12d51d5 | aliguori | |
31 | d12d51d5 | aliguori | //#define CRIS_HELPER_DEBUG
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32 | d12d51d5 | aliguori | |
33 | d12d51d5 | aliguori | |
34 | d12d51d5 | aliguori | #ifdef CRIS_HELPER_DEBUG
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35 | d12d51d5 | aliguori | #define D(x) x
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36 | 93fcfe39 | aliguori | #define D_LOG(...) qemu_log(__VA__ARGS__)
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37 | d12d51d5 | aliguori | #else
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38 | e62b5b13 | edgar_igl | #define D(x)
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39 | d12d51d5 | aliguori | #define D_LOG(...) do { } while (0) |
40 | d12d51d5 | aliguori | #endif
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41 | e62b5b13 | edgar_igl | |
42 | 81fdc5f8 | ths | #if defined(CONFIG_USER_ONLY)
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43 | 81fdc5f8 | ths | |
44 | 81fdc5f8 | ths | void do_interrupt (CPUState *env)
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45 | 81fdc5f8 | ths | { |
46 | bbaf29c7 | edgar_igl | env->exception_index = -1;
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47 | bbaf29c7 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
48 | 81fdc5f8 | ths | } |
49 | 81fdc5f8 | ths | |
50 | 81fdc5f8 | ths | int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
51 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
52 | 81fdc5f8 | ths | { |
53 | bbaf29c7 | edgar_igl | env->exception_index = 0xaa;
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54 | 30abcfc7 | edgar_igl | env->pregs[PR_EDA] = address; |
55 | bbaf29c7 | edgar_igl | cpu_dump_state(env, stderr, fprintf, 0);
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56 | bbaf29c7 | edgar_igl | return 1; |
57 | 81fdc5f8 | ths | } |
58 | 81fdc5f8 | ths | |
59 | 81fdc5f8 | ths | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
60 | 81fdc5f8 | ths | { |
61 | bbaf29c7 | edgar_igl | return addr;
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62 | 81fdc5f8 | ths | } |
63 | 81fdc5f8 | ths | |
64 | 81fdc5f8 | ths | #else /* !CONFIG_USER_ONLY */ |
65 | 81fdc5f8 | ths | |
66 | e62b5b13 | edgar_igl | |
67 | e62b5b13 | edgar_igl | static void cris_shift_ccs(CPUState *env) |
68 | e62b5b13 | edgar_igl | { |
69 | e62b5b13 | edgar_igl | uint32_t ccs; |
70 | e62b5b13 | edgar_igl | /* Apply the ccs shift. */
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71 | e62b5b13 | edgar_igl | ccs = env->pregs[PR_CCS]; |
72 | b41f7df0 | edgar_igl | ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff; |
73 | e62b5b13 | edgar_igl | env->pregs[PR_CCS] = ccs; |
74 | e62b5b13 | edgar_igl | } |
75 | e62b5b13 | edgar_igl | |
76 | 81fdc5f8 | ths | int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
77 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
78 | 81fdc5f8 | ths | { |
79 | 2fa73ec8 | Edgar E. Iglesias | struct cris_mmu_result res;
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80 | 81fdc5f8 | ths | int prot, miss;
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81 | e62b5b13 | edgar_igl | int r = -1; |
82 | 81fdc5f8 | ths | target_ulong phy; |
83 | 81fdc5f8 | ths | |
84 | b41f7df0 | edgar_igl | D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
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85 | 81fdc5f8 | ths | address &= TARGET_PAGE_MASK; |
86 | 6ebbf390 | j_mayer | miss = cris_mmu_translate(&res, env, address, rw, mmu_idx); |
87 | 81fdc5f8 | ths | if (miss)
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88 | 81fdc5f8 | ths | { |
89 | 1b1a38b0 | edgar_igl | if (env->exception_index == EXCP_BUSFAULT)
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90 | ef29a70d | edgar_igl | cpu_abort(env, |
91 | ef29a70d | edgar_igl | "CRIS: Illegal recursive bus fault."
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92 | ef29a70d | edgar_igl | "addr=%x rw=%d\n",
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93 | ef29a70d | edgar_igl | address, rw); |
94 | ef29a70d | edgar_igl | |
95 | 1b1a38b0 | edgar_igl | env->exception_index = EXCP_BUSFAULT; |
96 | e62b5b13 | edgar_igl | env->fault_vector = res.bf_vec; |
97 | e62b5b13 | edgar_igl | r = 1;
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98 | 81fdc5f8 | ths | } |
99 | 81fdc5f8 | ths | else
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100 | 81fdc5f8 | ths | { |
101 | 980f8a0b | edgar_igl | /*
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102 | 980f8a0b | edgar_igl | * Mask off the cache selection bit. The ETRAX busses do not
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103 | 980f8a0b | edgar_igl | * see the top bit.
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104 | 980f8a0b | edgar_igl | */
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105 | 980f8a0b | edgar_igl | phy = res.phy & ~0x80000000;
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106 | b41f7df0 | edgar_igl | prot = res.prot; |
107 | e62b5b13 | edgar_igl | r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); |
108 | 81fdc5f8 | ths | } |
109 | b41f7df0 | edgar_igl | if (r > 0) |
110 | d12d51d5 | aliguori | D_LOG("%s returns %d irqreq=%x addr=%x"
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111 | cf1d97f0 | edgar_igl | " phy=%x ismmu=%d vec=%x pc=%x\n",
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112 | cf1d97f0 | edgar_igl | __func__, r, env->interrupt_request, |
113 | d12d51d5 | aliguori | address, res.phy, is_softmmu, res.bf_vec, env->pc); |
114 | e62b5b13 | edgar_igl | return r;
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115 | 81fdc5f8 | ths | } |
116 | 81fdc5f8 | ths | |
117 | 81fdc5f8 | ths | void do_interrupt(CPUState *env)
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118 | 81fdc5f8 | ths | { |
119 | e62b5b13 | edgar_igl | int ex_vec = -1; |
120 | 81fdc5f8 | ths | |
121 | d12d51d5 | aliguori | D_LOG( "exception index=%d interrupt_req=%d\n",
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122 | b41f7df0 | edgar_igl | env->exception_index, |
123 | d12d51d5 | aliguori | env->interrupt_request); |
124 | 81fdc5f8 | ths | |
125 | 81fdc5f8 | ths | switch (env->exception_index)
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126 | 81fdc5f8 | ths | { |
127 | 81fdc5f8 | ths | case EXCP_BREAK:
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128 | e62b5b13 | edgar_igl | /* These exceptions are genereated by the core itself.
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129 | e62b5b13 | edgar_igl | ERP should point to the insn following the brk. */
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130 | e62b5b13 | edgar_igl | ex_vec = env->trap_vector; |
131 | a1aebcb8 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
132 | 81fdc5f8 | ths | break;
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133 | e62b5b13 | edgar_igl | |
134 | 1b1a38b0 | edgar_igl | case EXCP_NMI:
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135 | 1b1a38b0 | edgar_igl | /* NMI is hardwired to vector zero. */
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136 | 1b1a38b0 | edgar_igl | ex_vec = 0;
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137 | 1b1a38b0 | edgar_igl | env->pregs[PR_CCS] &= ~M_FLAG; |
138 | 1b1a38b0 | edgar_igl | env->pregs[PR_NRP] = env->pc; |
139 | 1b1a38b0 | edgar_igl | break;
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140 | 1b1a38b0 | edgar_igl | |
141 | 1b1a38b0 | edgar_igl | case EXCP_BUSFAULT:
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142 | e62b5b13 | edgar_igl | ex_vec = env->fault_vector; |
143 | b41f7df0 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
144 | 81fdc5f8 | ths | break;
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145 | 81fdc5f8 | ths | |
146 | 81fdc5f8 | ths | default:
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147 | 1b1a38b0 | edgar_igl | /* The interrupt controller gives us the vector. */
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148 | b41f7df0 | edgar_igl | ex_vec = env->interrupt_vector; |
149 | b41f7df0 | edgar_igl | /* Normal interrupts are taken between
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150 | b41f7df0 | edgar_igl | TB's. env->pc is valid here. */
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151 | b41f7df0 | edgar_igl | env->pregs[PR_ERP] = env->pc; |
152 | b41f7df0 | edgar_igl | break;
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153 | b41f7df0 | edgar_igl | } |
154 | b41f7df0 | edgar_igl | |
155 | cddffe37 | edgar_igl | /* Fill in the IDX field. */
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156 | cddffe37 | edgar_igl | env->pregs[PR_EXS] = (ex_vec & 0xff) << 8; |
157 | cddffe37 | edgar_igl | |
158 | cf1d97f0 | edgar_igl | if (env->dslot) {
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159 | d12d51d5 | aliguori | D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
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160 | cf1d97f0 | edgar_igl | " ERP=%x pid=%x ccs=%x cc=%d %x\n",
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161 | cf1d97f0 | edgar_igl | ex_vec, env->pc, env->dslot, |
162 | ef29a70d | edgar_igl | env->regs[R_SP], |
163 | b41f7df0 | edgar_igl | env->pregs[PR_ERP], env->pregs[PR_PID], |
164 | b41f7df0 | edgar_igl | env->pregs[PR_CCS], |
165 | d12d51d5 | aliguori | env->cc_op, env->cc_mask); |
166 | cf1d97f0 | edgar_igl | /* We loose the btarget, btaken state here so rexec the
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167 | cf1d97f0 | edgar_igl | branch. */
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168 | cf1d97f0 | edgar_igl | env->pregs[PR_ERP] -= env->dslot; |
169 | cf1d97f0 | edgar_igl | /* Exception starts with dslot cleared. */
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170 | cf1d97f0 | edgar_igl | env->dslot = 0;
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171 | 81fdc5f8 | ths | } |
172 | b41f7df0 | edgar_igl | |
173 | e62b5b13 | edgar_igl | env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
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174 | b41f7df0 | edgar_igl | |
175 | b41f7df0 | edgar_igl | if (env->pregs[PR_CCS] & U_FLAG) {
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176 | b41f7df0 | edgar_igl | /* Swap stack pointers. */
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177 | b41f7df0 | edgar_igl | env->pregs[PR_USP] = env->regs[R_SP]; |
178 | b41f7df0 | edgar_igl | env->regs[R_SP] = env->ksp; |
179 | b41f7df0 | edgar_igl | } |
180 | b41f7df0 | edgar_igl | |
181 | b41f7df0 | edgar_igl | /* Apply the CRIS CCS shift. Clears U if set. */
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182 | e62b5b13 | edgar_igl | cris_shift_ccs(env); |
183 | d12d51d5 | aliguori | D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
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184 | b41f7df0 | edgar_igl | __func__, env->pc, ex_vec, |
185 | b41f7df0 | edgar_igl | env->pregs[PR_CCS], |
186 | b41f7df0 | edgar_igl | env->pregs[PR_PID], |
187 | d12d51d5 | aliguori | env->pregs[PR_ERP]); |
188 | 81fdc5f8 | ths | } |
189 | 81fdc5f8 | ths | |
190 | 81fdc5f8 | ths | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
191 | 81fdc5f8 | ths | { |
192 | 81fdc5f8 | ths | uint32_t phy = addr; |
193 | 2fa73ec8 | Edgar E. Iglesias | struct cris_mmu_result res;
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194 | 81fdc5f8 | ths | int miss;
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195 | 81fdc5f8 | ths | miss = cris_mmu_translate(&res, env, addr, 0, 0); |
196 | 81fdc5f8 | ths | if (!miss)
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197 | 81fdc5f8 | ths | phy = res.phy; |
198 | e62b5b13 | edgar_igl | D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
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199 | 81fdc5f8 | ths | return phy;
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200 | 81fdc5f8 | ths | } |
201 | 81fdc5f8 | ths | #endif |