root / hw / mainstone.c @ 1654b2d6
History | View | Annotate | Download (4.5 kB)
1 | ef056e43 | balrog | /*
|
---|---|---|---|
2 | ef056e43 | balrog | * PXA270-based Intel Mainstone platforms.
|
3 | ef056e43 | balrog | *
|
4 | ef056e43 | balrog | * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
|
5 | ef056e43 | balrog | * <akuster@mvista.com>
|
6 | ef056e43 | balrog | *
|
7 | ef056e43 | balrog | * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
|
8 | ef056e43 | balrog | *
|
9 | ef056e43 | balrog | * This code is licensed under the GNU GPL v2.
|
10 | ef056e43 | balrog | */
|
11 | ef056e43 | balrog | #include "hw.h" |
12 | ef056e43 | balrog | #include "pxa.h" |
13 | ef056e43 | balrog | #include "arm-misc.h" |
14 | ef056e43 | balrog | #include "net.h" |
15 | ef056e43 | balrog | #include "devices.h" |
16 | ef056e43 | balrog | #include "boards.h" |
17 | 7233b355 | ths | #include "mainstone.h" |
18 | 7233b355 | ths | #include "sysemu.h" |
19 | 7233b355 | ths | #include "flash.h" |
20 | ef056e43 | balrog | |
21 | bd464c2e | balrog | static struct keymap map[0xE0] = { |
22 | bd464c2e | balrog | [0 ... 0xDF] = { -1, -1 }, |
23 | bd464c2e | balrog | [0x1e] = {0,0}, /* a */ |
24 | bd464c2e | balrog | [0x30] = {0,1}, /* b */ |
25 | bd464c2e | balrog | [0x2e] = {0,2}, /* c */ |
26 | bd464c2e | balrog | [0x20] = {0,3}, /* d */ |
27 | bd464c2e | balrog | [0x12] = {0,4}, /* e */ |
28 | bd464c2e | balrog | [0x21] = {0,5}, /* f */ |
29 | bd464c2e | balrog | [0x22] = {1,0}, /* g */ |
30 | bd464c2e | balrog | [0x23] = {1,1}, /* h */ |
31 | bd464c2e | balrog | [0x17] = {1,2}, /* i */ |
32 | bd464c2e | balrog | [0x24] = {1,3}, /* j */ |
33 | bd464c2e | balrog | [0x25] = {1,4}, /* k */ |
34 | bd464c2e | balrog | [0x26] = {1,5}, /* l */ |
35 | bd464c2e | balrog | [0x32] = {2,0}, /* m */ |
36 | bd464c2e | balrog | [0x31] = {2,1}, /* n */ |
37 | bd464c2e | balrog | [0x18] = {2,2}, /* o */ |
38 | bd464c2e | balrog | [0x19] = {2,3}, /* p */ |
39 | bd464c2e | balrog | [0x10] = {2,4}, /* q */ |
40 | bd464c2e | balrog | [0x13] = {2,5}, /* r */ |
41 | bd464c2e | balrog | [0x1f] = {3,0}, /* s */ |
42 | bd464c2e | balrog | [0x14] = {3,1}, /* t */ |
43 | bd464c2e | balrog | [0x16] = {3,2}, /* u */ |
44 | bd464c2e | balrog | [0x2f] = {3,3}, /* v */ |
45 | bd464c2e | balrog | [0x11] = {3,4}, /* w */ |
46 | bd464c2e | balrog | [0x2d] = {3,5}, /* x */ |
47 | bd464c2e | balrog | [0x15] = {4,2}, /* y */ |
48 | bd464c2e | balrog | [0x2c] = {4,3}, /* z */ |
49 | bd464c2e | balrog | [0xc7] = {5,0}, /* Home */ |
50 | bd464c2e | balrog | [0x2a] = {5,1}, /* shift */ |
51 | bd464c2e | balrog | [0x39] = {5,2}, /* space */ |
52 | bd464c2e | balrog | [0x39] = {5,3}, /* space */ |
53 | bd464c2e | balrog | [0x1c] = {5,5}, /* enter */ |
54 | bd464c2e | balrog | [0xc8] = {6,0}, /* up */ |
55 | bd464c2e | balrog | [0xd0] = {6,1}, /* down */ |
56 | bd464c2e | balrog | [0xcb] = {6,2}, /* left */ |
57 | bd464c2e | balrog | [0xcd] = {6,3}, /* right */ |
58 | bd464c2e | balrog | }; |
59 | bd464c2e | balrog | |
60 | ef056e43 | balrog | enum mainstone_model_e { mainstone };
|
61 | ef056e43 | balrog | |
62 | ef056e43 | balrog | static void mainstone_common_init(int ram_size, int vga_ram_size, |
63 | ef056e43 | balrog | DisplayState *ds, const char *kernel_filename, |
64 | ef056e43 | balrog | const char *kernel_cmdline, const char *initrd_filename, |
65 | ef056e43 | balrog | const char *cpu_model, enum mainstone_model_e model, int arm_id) |
66 | ef056e43 | balrog | { |
67 | 6d1f1778 | balrog | uint32_t mainstone_ram = 0x04000000;
|
68 | 6d1f1778 | balrog | uint32_t mainstone_rom = 0x00800000;
|
69 | 6d1f1778 | balrog | uint32_t mainstone_flash = 0x02000000;
|
70 | 6d1f1778 | balrog | uint32_t sector_len = 256 * 1024; |
71 | 6d1f1778 | balrog | target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; |
72 | ef056e43 | balrog | struct pxa2xx_state_s *cpu;
|
73 | ef056e43 | balrog | qemu_irq *mst_irq; |
74 | 6d1f1778 | balrog | int i, index;
|
75 | ef056e43 | balrog | |
76 | ef056e43 | balrog | if (!cpu_model)
|
77 | ef056e43 | balrog | cpu_model = "pxa270-c5";
|
78 | ef056e43 | balrog | |
79 | ef056e43 | balrog | /* Setup CPU & memory */
|
80 | 6d1f1778 | balrog | if (ram_size < mainstone_ram + mainstone_rom + 2 * mainstone_flash + |
81 | 6d1f1778 | balrog | PXA2XX_INTERNAL_SIZE) { |
82 | ef056e43 | balrog | fprintf(stderr, "This platform requires %i bytes of memory\n",
|
83 | 6d1f1778 | balrog | mainstone_ram + mainstone_rom + 2 * mainstone_flash +
|
84 | 6d1f1778 | balrog | PXA2XX_INTERNAL_SIZE); |
85 | ef056e43 | balrog | exit(1);
|
86 | ef056e43 | balrog | } |
87 | ef056e43 | balrog | |
88 | ef056e43 | balrog | cpu = pxa270_init(mainstone_ram, ds, cpu_model); |
89 | ef056e43 | balrog | cpu_register_physical_memory(0, mainstone_rom,
|
90 | ef056e43 | balrog | qemu_ram_alloc(mainstone_rom) | IO_MEM_ROM); |
91 | ef056e43 | balrog | |
92 | ef056e43 | balrog | /* Setup initial (reset) machine state */
|
93 | ef056e43 | balrog | cpu->env->regs[15] = PXA2XX_SDRAM_BASE;
|
94 | ef056e43 | balrog | |
95 | e4bcb14c | ths | /* There are two 32MiB flash devices on the board */
|
96 | 6d1f1778 | balrog | for (i = 0; i < 2; i ++) { |
97 | 6d1f1778 | balrog | index = drive_get_index(IF_PFLASH, 0, i);
|
98 | 6d1f1778 | balrog | if (index == -1) { |
99 | 6d1f1778 | balrog | fprintf(stderr, "Two flash images must be given with the "
|
100 | 6d1f1778 | balrog | "'pflash' parameter\n");
|
101 | 6d1f1778 | balrog | exit(1);
|
102 | 6d1f1778 | balrog | } |
103 | 6d1f1778 | balrog | |
104 | 6d1f1778 | balrog | if (!pflash_cfi01_register(mainstone_flash_base[i],
|
105 | 6d1f1778 | balrog | qemu_ram_alloc(mainstone_flash), |
106 | 6d1f1778 | balrog | drives_table[index].bdrv, sector_len, |
107 | 6d1f1778 | balrog | mainstone_flash / sector_len, 4, 0, 0, 0, 0)) { |
108 | 6d1f1778 | balrog | fprintf(stderr, "qemu: Error registering flash memory.\n");
|
109 | 6d1f1778 | balrog | exit(1);
|
110 | 6d1f1778 | balrog | } |
111 | e4bcb14c | ths | } |
112 | 7233b355 | ths | |
113 | 7233b355 | ths | mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0); |
114 | f1de1334 | ths | |
115 | bd464c2e | balrog | /* setup keypad */
|
116 | bd464c2e | balrog | printf("map addr %p\n", &map);
|
117 | bd464c2e | balrog | pxa27x_register_keypad(cpu->kp, map, 0xe0);
|
118 | bd464c2e | balrog | |
119 | f1de1334 | ths | /* MMC/SD host */
|
120 | 8543243c | balrog | pxa2xx_mmci_handlers(cpu->mmc, NULL, mst_irq[MMC_IRQ]);
|
121 | f1de1334 | ths | |
122 | ef056e43 | balrog | smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
|
123 | ef056e43 | balrog | |
124 | ef056e43 | balrog | arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline, |
125 | ef056e43 | balrog | initrd_filename, arm_id, PXA2XX_SDRAM_BASE); |
126 | ef056e43 | balrog | } |
127 | ef056e43 | balrog | |
128 | ef056e43 | balrog | static void mainstone_init(int ram_size, int vga_ram_size, |
129 | ef056e43 | balrog | const char *boot_device, DisplayState *ds, |
130 | ef056e43 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
131 | ef056e43 | balrog | const char *initrd_filename, const char *cpu_model) |
132 | ef056e43 | balrog | { |
133 | ef056e43 | balrog | mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename, |
134 | ef056e43 | balrog | kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
|
135 | ef056e43 | balrog | } |
136 | ef056e43 | balrog | |
137 | ef056e43 | balrog | QEMUMachine mainstone2_machine = { |
138 | ef056e43 | balrog | "mainstone",
|
139 | ef056e43 | balrog | "Mainstone II (PXA27x)",
|
140 | ef056e43 | balrog | mainstone_init, |
141 | ef056e43 | balrog | }; |