root / hw / ich9.h @ 16665b94
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1 | e516572f | Jason Baron | #ifndef HW_ICH9_H
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2 | e516572f | Jason Baron | #define HW_ICH9_H
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3 | e516572f | Jason Baron | |
4 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
5 | 1de7afc9 | Paolo Bonzini | #include "qemu/range.h" |
6 | 83c9f4ca | Paolo Bonzini | #include "hw/isa.h" |
7 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
8 | 83c9f4ca | Paolo Bonzini | #include "hw/pc.h" |
9 | 83c9f4ca | Paolo Bonzini | #include "hw/apm.h" |
10 | 83c9f4ca | Paolo Bonzini | #include "hw/ioapic.h" |
11 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci.h" |
12 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pcie_host.h" |
13 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci_bridge.h" |
14 | 83c9f4ca | Paolo Bonzini | #include "hw/acpi.h" |
15 | 83c9f4ca | Paolo Bonzini | #include "hw/acpi_ich9.h" |
16 | 83c9f4ca | Paolo Bonzini | #include "hw/pam.h" |
17 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci_bus.h" |
18 | e516572f | Jason Baron | |
19 | e516572f | Jason Baron | void ich9_lpc_set_irq(void *opaque, int irq_num, int level); |
20 | e516572f | Jason Baron | int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx); |
21 | 91c3f2f0 | Jason Baron | PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin); |
22 | e516572f | Jason Baron | void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
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23 | e516572f | Jason Baron | PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus); |
24 | e516572f | Jason Baron | i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
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25 | e516572f | Jason Baron | |
26 | e516572f | Jason Baron | #define ICH9_CC_SIZE (16 * 1024) /* 16KB */ |
27 | e516572f | Jason Baron | |
28 | e516572f | Jason Baron | #define TYPE_ICH9_LPC_DEVICE "ICH9 LPC" |
29 | e516572f | Jason Baron | #define ICH9_LPC_DEVICE(obj) \
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30 | e516572f | Jason Baron | OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE) |
31 | e516572f | Jason Baron | |
32 | e516572f | Jason Baron | typedef struct ICH9LPCState { |
33 | e516572f | Jason Baron | /* ICH9 LPC PCI to ISA bridge */
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34 | e516572f | Jason Baron | PCIDevice d; |
35 | e516572f | Jason Baron | |
36 | e516572f | Jason Baron | /* (pci device, intx) -> pirq
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37 | e516572f | Jason Baron | * In real chipset case, the unused slots are never used
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38 | e516572f | Jason Baron | * as ICH9 supports only D25-D32 irq routing.
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39 | e516572f | Jason Baron | * On the other hand in qemu case, any slot/function can be populated
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40 | e516572f | Jason Baron | * via command line option.
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41 | e516572f | Jason Baron | * So fallback interrupt routing for any devices in any slots is necessary.
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42 | e516572f | Jason Baron | */
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43 | e516572f | Jason Baron | uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS]; |
44 | e516572f | Jason Baron | |
45 | e516572f | Jason Baron | APMState apm; |
46 | e516572f | Jason Baron | ICH9LPCPMRegs pm; |
47 | e516572f | Jason Baron | uint32_t sci_level; /* track sci level */
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48 | e516572f | Jason Baron | |
49 | e516572f | Jason Baron | /* 10.1 Chipset Configuration registers(Memory Space)
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50 | e516572f | Jason Baron | which is pointed by RCBA */
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51 | e516572f | Jason Baron | uint8_t chip_config[ICH9_CC_SIZE]; |
52 | 0e98b436 | Laszlo Ersek | |
53 | 0e98b436 | Laszlo Ersek | /*
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54 | 0e98b436 | Laszlo Ersek | * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
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55 | 0e98b436 | Laszlo Ersek | *
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56 | 0e98b436 | Laszlo Ersek | * register contents and IO memory region
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57 | 0e98b436 | Laszlo Ersek | */
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58 | 0e98b436 | Laszlo Ersek | uint8_t rst_cnt; |
59 | 0e98b436 | Laszlo Ersek | MemoryRegion rst_cnt_mem; |
60 | 0e98b436 | Laszlo Ersek | |
61 | e516572f | Jason Baron | /* isa bus */
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62 | e516572f | Jason Baron | ISABus *isa_bus; |
63 | e516572f | Jason Baron | MemoryRegion rbca_mem; |
64 | 3f5bc9e8 | Gerd Hoffmann | Notifier machine_ready; |
65 | e516572f | Jason Baron | |
66 | e516572f | Jason Baron | qemu_irq *pic; |
67 | e516572f | Jason Baron | qemu_irq *ioapic; |
68 | e516572f | Jason Baron | } ICH9LPCState; |
69 | e516572f | Jason Baron | |
70 | e516572f | Jason Baron | #define Q35_MASK(bit, ms_bit, ls_bit) \
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71 | e516572f | Jason Baron | ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) |
72 | e516572f | Jason Baron | |
73 | e516572f | Jason Baron | /* ICH9: Chipset Configuration Registers */
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74 | e516572f | Jason Baron | #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) |
75 | e516572f | Jason Baron | |
76 | e516572f | Jason Baron | #define ICH9_CC
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77 | e516572f | Jason Baron | #define ICH9_CC_D28IP 0x310C |
78 | e516572f | Jason Baron | #define ICH9_CC_D28IP_SHIFT 4 |
79 | e516572f | Jason Baron | #define ICH9_CC_D28IP_MASK 0xf |
80 | e516572f | Jason Baron | #define ICH9_CC_D28IP_DEFAULT 0x00214321 |
81 | e516572f | Jason Baron | #define ICH9_CC_D31IR 0x3140 |
82 | e516572f | Jason Baron | #define ICH9_CC_D30IR 0x3142 |
83 | e516572f | Jason Baron | #define ICH9_CC_D29IR 0x3144 |
84 | e516572f | Jason Baron | #define ICH9_CC_D28IR 0x3146 |
85 | e516572f | Jason Baron | #define ICH9_CC_D27IR 0x3148 |
86 | e516572f | Jason Baron | #define ICH9_CC_D26IR 0x314C |
87 | e516572f | Jason Baron | #define ICH9_CC_D25IR 0x3150 |
88 | e516572f | Jason Baron | #define ICH9_CC_DIR_DEFAULT 0x3210 |
89 | e516572f | Jason Baron | #define ICH9_CC_D30IR_DEFAULT 0x0 |
90 | e516572f | Jason Baron | #define ICH9_CC_DIR_SHIFT 4 |
91 | e516572f | Jason Baron | #define ICH9_CC_DIR_MASK 0x7 |
92 | e516572f | Jason Baron | #define ICH9_CC_OIC 0x31FF |
93 | e516572f | Jason Baron | #define ICH9_CC_OIC_AEN 0x1 |
94 | e516572f | Jason Baron | |
95 | e516572f | Jason Baron | /* D28:F[0-5] */
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96 | e516572f | Jason Baron | #define ICH9_PCIE_DEV 28 |
97 | e516572f | Jason Baron | #define ICH9_PCIE_FUNC_MAX 6 |
98 | e516572f | Jason Baron | |
99 | e516572f | Jason Baron | |
100 | e516572f | Jason Baron | /* D29:F0 USB UHCI Controller #1 */
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101 | e516572f | Jason Baron | #define ICH9_USB_UHCI1_DEV 29 |
102 | e516572f | Jason Baron | #define ICH9_USB_UHCI1_FUNC 0 |
103 | e516572f | Jason Baron | |
104 | e516572f | Jason Baron | /* D30:F0 DMI-to-PCI brdige */
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105 | e516572f | Jason Baron | #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" |
106 | e516572f | Jason Baron | #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 |
107 | e516572f | Jason Baron | |
108 | e516572f | Jason Baron | #define ICH9_D2P_BRIDGE_DEV 30 |
109 | e516572f | Jason Baron | #define ICH9_D2P_BRIDGE_FUNC 0 |
110 | e516572f | Jason Baron | |
111 | e516572f | Jason Baron | #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) |
112 | e516572f | Jason Baron | |
113 | e516572f | Jason Baron | #define ICH9_D2P_A2_REVISION 0x92 |
114 | e516572f | Jason Baron | |
115 | 0e98b436 | Laszlo Ersek | /* D31:F0 LPC Processor Interface */
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116 | 0e98b436 | Laszlo Ersek | #define ICH9_RST_CNT_IOPORT 0xCF9 |
117 | e516572f | Jason Baron | |
118 | e516572f | Jason Baron | /* D31:F1 LPC controller */
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119 | e516572f | Jason Baron | #define ICH9_A2_LPC "ICH9 A2 LPC" |
120 | e516572f | Jason Baron | #define ICH9_A2_LPC_SAVEVM_VERSION 0 |
121 | e516572f | Jason Baron | |
122 | e516572f | Jason Baron | #define ICH9_LPC_DEV 31 |
123 | e516572f | Jason Baron | #define ICH9_LPC_FUNC 0 |
124 | e516572f | Jason Baron | |
125 | e516572f | Jason Baron | #define ICH9_A2_LPC_REVISION 0x2 |
126 | e516572f | Jason Baron | #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */ |
127 | e516572f | Jason Baron | |
128 | e516572f | Jason Baron | #define ICH9_LPC_PMBASE 0x40 |
129 | e516572f | Jason Baron | #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7) |
130 | e516572f | Jason Baron | #define ICH9_LPC_PMBASE_RTE 0x1 |
131 | e516572f | Jason Baron | #define ICH9_LPC_PMBASE_DEFAULT 0x1 |
132 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL 0x44 |
133 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 |
134 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0) |
135 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_9 0x0 |
136 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_10 0x1 |
137 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_11 0x2 |
138 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_20 0x4 |
139 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_21 0x5 |
140 | e516572f | Jason Baron | #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 |
141 | e516572f | Jason Baron | |
142 | e516572f | Jason Baron | #define ICH9_LPC_PIRQA_ROUT 0x60 |
143 | e516572f | Jason Baron | #define ICH9_LPC_PIRQB_ROUT 0x61 |
144 | e516572f | Jason Baron | #define ICH9_LPC_PIRQC_ROUT 0x62 |
145 | e516572f | Jason Baron | #define ICH9_LPC_PIRQD_ROUT 0x63 |
146 | e516572f | Jason Baron | |
147 | e516572f | Jason Baron | #define ICH9_LPC_PIRQE_ROUT 0x68 |
148 | e516572f | Jason Baron | #define ICH9_LPC_PIRQF_ROUT 0x69 |
149 | e516572f | Jason Baron | #define ICH9_LPC_PIRQG_ROUT 0x6a |
150 | e516572f | Jason Baron | #define ICH9_LPC_PIRQH_ROUT 0x6b |
151 | e516572f | Jason Baron | |
152 | e516572f | Jason Baron | #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 |
153 | e516572f | Jason Baron | #define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) |
154 | e516572f | Jason Baron | #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 |
155 | e516572f | Jason Baron | |
156 | e516572f | Jason Baron | #define ICH9_LPC_RCBA 0xf0 |
157 | e516572f | Jason Baron | #define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) |
158 | e516572f | Jason Baron | #define ICH9_LPC_RCBA_EN 0x1 |
159 | e516572f | Jason Baron | #define ICH9_LPC_RCBA_DEFAULT 0x0 |
160 | e516572f | Jason Baron | |
161 | e516572f | Jason Baron | #define ICH9_LPC_PIC_NUM_PINS 16 |
162 | e516572f | Jason Baron | #define ICH9_LPC_IOAPIC_NUM_PINS 24 |
163 | e516572f | Jason Baron | |
164 | e516572f | Jason Baron | /* D31:F2 SATA Controller #1 */
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165 | e516572f | Jason Baron | #define ICH9_SATA1_DEV 31 |
166 | e516572f | Jason Baron | #define ICH9_SATA1_FUNC 2 |
167 | e516572f | Jason Baron | |
168 | e516572f | Jason Baron | /* D30:F1 power management I/O registers
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169 | e516572f | Jason Baron | offset from the address ICH9_LPC_PMBASE */
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170 | e516572f | Jason Baron | |
171 | e516572f | Jason Baron | /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
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172 | e516572f | Jason Baron | #define ICH9_PMIO_SIZE 128 |
173 | e516572f | Jason Baron | #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) |
174 | e516572f | Jason Baron | |
175 | e516572f | Jason Baron | #define ICH9_PMIO_PM1_STS 0x00 |
176 | e516572f | Jason Baron | #define ICH9_PMIO_PM1_EN 0x02 |
177 | e516572f | Jason Baron | #define ICH9_PMIO_PM1_CNT 0x04 |
178 | e516572f | Jason Baron | #define ICH9_PMIO_PM1_TMR 0x08 |
179 | e516572f | Jason Baron | #define ICH9_PMIO_GPE0_STS 0x20 |
180 | e516572f | Jason Baron | #define ICH9_PMIO_GPE0_EN 0x28 |
181 | e516572f | Jason Baron | #define ICH9_PMIO_GPE0_LEN 16 |
182 | e516572f | Jason Baron | #define ICH9_PMIO_SMI_EN 0x30 |
183 | e516572f | Jason Baron | #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) |
184 | e516572f | Jason Baron | #define ICH9_PMIO_SMI_STS 0x34 |
185 | e516572f | Jason Baron | |
186 | e516572f | Jason Baron | /* FADT ACPI_ENABLE/ACPI_DISABLE */
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187 | e516572f | Jason Baron | #define ICH9_APM_ACPI_ENABLE 0x2 |
188 | e516572f | Jason Baron | #define ICH9_APM_ACPI_DISABLE 0x3 |
189 | e516572f | Jason Baron | |
190 | e516572f | Jason Baron | |
191 | e516572f | Jason Baron | /* D31:F3 SMBus controller */
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192 | e516572f | Jason Baron | #define ICH9_A2_SMB_REVISION 0x02 |
193 | e516572f | Jason Baron | #define ICH9_SMB_PI 0x00 |
194 | e516572f | Jason Baron | |
195 | e516572f | Jason Baron | #define ICH9_SMB_SMBMBAR0 0x10 |
196 | e516572f | Jason Baron | #define ICH9_SMB_SMBMBAR1 0x14 |
197 | e516572f | Jason Baron | #define ICH9_SMB_SMBM_BAR 0 |
198 | e516572f | Jason Baron | #define ICH9_SMB_SMBM_SIZE (1 << 8) |
199 | e516572f | Jason Baron | #define ICH9_SMB_SMB_BASE 0x20 |
200 | e516572f | Jason Baron | #define ICH9_SMB_SMB_BASE_BAR 4 |
201 | e516572f | Jason Baron | #define ICH9_SMB_SMB_BASE_SIZE (1 << 5) |
202 | e516572f | Jason Baron | #define ICH9_SMB_HOSTC 0x40 |
203 | e516572f | Jason Baron | #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) |
204 | e516572f | Jason Baron | #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) |
205 | e516572f | Jason Baron | #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) |
206 | e516572f | Jason Baron | #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) |
207 | e516572f | Jason Baron | |
208 | e516572f | Jason Baron | /* D31:F3 SMBus I/O and memory mapped I/O registers */
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209 | e516572f | Jason Baron | #define ICH9_SMB_DEV 31 |
210 | e516572f | Jason Baron | #define ICH9_SMB_FUNC 3 |
211 | e516572f | Jason Baron | |
212 | e516572f | Jason Baron | #define ICH9_SMB_HST_STS 0x00 |
213 | e516572f | Jason Baron | #define ICH9_SMB_HST_CNT 0x02 |
214 | e516572f | Jason Baron | #define ICH9_SMB_HST_CMD 0x03 |
215 | e516572f | Jason Baron | #define ICH9_SMB_XMIT_SLVA 0x04 |
216 | e516572f | Jason Baron | #define ICH9_SMB_HST_D0 0x05 |
217 | e516572f | Jason Baron | #define ICH9_SMB_HST_D1 0x06 |
218 | e516572f | Jason Baron | #define ICH9_SMB_HOST_BLOCK_DB 0x07 |
219 | e516572f | Jason Baron | |
220 | e516572f | Jason Baron | #endif /* HW_ICH9_H */ |