Revision 168aa23b target-arm/helper.c
| b/target-arm/helper.c | ||
|---|---|---|
| 1525 | 1525 |
return CP_ACCESS_OK; |
| 1526 | 1526 |
} |
| 1527 | 1527 |
|
| 1528 |
static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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| 1529 |
uint64_t value) |
|
| 1530 |
{
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| 1531 |
/* Invalidate by VA (AArch64 version) */ |
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| 1532 |
uint64_t pageaddr = value << 12; |
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| 1533 |
tlb_flush_page(env, pageaddr); |
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| 1534 |
} |
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| 1535 |
|
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| 1536 |
static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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| 1537 |
uint64_t value) |
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| 1538 |
{
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| 1539 |
/* Invalidate by VA, all ASIDs (AArch64 version) */ |
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| 1540 |
uint64_t pageaddr = value << 12; |
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| 1541 |
tlb_flush_page(env, pageaddr); |
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| 1542 |
} |
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| 1543 |
|
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| 1544 |
static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
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| 1545 |
uint64_t value) |
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| 1546 |
{
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| 1547 |
/* Invalidate by ASID (AArch64 version) */ |
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| 1548 |
int asid = extract64(value, 48, 16); |
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| 1549 |
tlb_flush(env, asid == 0); |
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| 1550 |
} |
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| 1551 |
|
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| 1528 | 1552 |
static const ARMCPRegInfo v8_cp_reginfo[] = {
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| 1529 | 1553 |
/* Minimal set of EL0-visible registers. This will need to be expanded |
| 1530 | 1554 |
* significantly for system emulation of AArch64 CPUs. |
| ... | ... | |
| 1583 | 1607 |
{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
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| 1584 | 1608 |
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
| 1585 | 1609 |
.access = PL1_W, .type = ARM_CP_NOP }, |
| 1610 |
/* TLBI operations */ |
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| 1611 |
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
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| 1612 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
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| 1613 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1614 |
.writefn = tlbiall_write }, |
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| 1615 |
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
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| 1616 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
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| 1617 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1618 |
.writefn = tlbi_aa64_va_write }, |
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| 1619 |
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
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| 1620 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
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| 1621 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1622 |
.writefn = tlbi_aa64_asid_write }, |
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| 1623 |
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
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| 1624 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
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| 1625 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1626 |
.writefn = tlbi_aa64_vaa_write }, |
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| 1627 |
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
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| 1628 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
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| 1629 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1630 |
.writefn = tlbi_aa64_va_write }, |
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| 1631 |
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
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| 1632 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
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| 1633 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1634 |
.writefn = tlbi_aa64_vaa_write }, |
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| 1635 |
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
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| 1636 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
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| 1637 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1638 |
.writefn = tlbiall_write }, |
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| 1639 |
{ .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
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| 1640 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
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| 1641 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1642 |
.writefn = tlbi_aa64_va_write }, |
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| 1643 |
{ .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
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| 1644 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
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| 1645 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1646 |
.writefn = tlbi_aa64_asid_write }, |
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| 1647 |
{ .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
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| 1648 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
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| 1649 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1650 |
.writefn = tlbi_aa64_vaa_write }, |
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| 1651 |
{ .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
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| 1652 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
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| 1653 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1654 |
.writefn = tlbi_aa64_va_write }, |
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| 1655 |
{ .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
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| 1656 |
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
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| 1657 |
.access = PL1_W, .type = ARM_CP_NO_MIGRATE, |
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| 1658 |
.writefn = tlbi_aa64_vaa_write }, |
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| 1586 | 1659 |
REGINFO_SENTINEL |
| 1587 | 1660 |
}; |
| 1588 | 1661 |
|
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