Revision 16f62432 hw/dma.c
| b/hw/dma.c | ||
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| 39 | 39 |
#define ldebug(...) |
| 40 | 40 |
#endif |
| 41 | 41 |
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| 42 |
#define MEM_REAL(addr) ((addr)+(uint32_t)(phys_ram_base)) |
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| 43 | 42 |
#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
| 44 | 43 |
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| 45 | 44 |
struct dma_regs {
|
| ... | ... | |
| 49 | 48 |
uint8_t page; |
| 50 | 49 |
uint8_t dack; |
| 51 | 50 |
uint8_t eop; |
| 52 |
DMA_read_handler read_handler;
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DMA_misc_handler misc_handler;
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DMA_transfer_handler transfer_handler;
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void *opaque;
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| 54 | 53 |
}; |
| 55 | 54 |
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| 56 | 55 |
#define ADDR 0 |
| ... | ... | |
| 284 | 283 |
{
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struct dma_regs *r; |
| 286 | 285 |
int n; |
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int irq; |
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uint32_t addr; |
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target_ulong addr; |
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| 289 | 287 |
/* int ai, dir; */ |
| 290 | 288 |
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| 291 | 289 |
r = dma_controllers[ncont].regs + ichan; |
| 292 | 290 |
/* ai = r->mode & 16; */ |
| 293 | 291 |
/* dir = r->mode & 32 ? -1 : 1; */ |
| 294 | 292 |
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addr = MEM_REAL ((r->page << 16) | r->now[ADDR]); |
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irq = -1; |
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n = r->read_handler (addr, (r->base[COUNT] << ncont) + (1 << ncont), &irq); |
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addr = (r->page << 16) | r->now[ADDR]; |
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n = r->transfer_handler (r->opaque, addr, |
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(r->base[COUNT] << ncont) + (1 << ncont)); |
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r->now[COUNT] = n; |
| 300 | 297 |
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ldebug ("dma_pos %d irq %d size %d\n",
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n, irq, (r->base[1] << ncont) + (1 << ncont)); |
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if (-1 != irq) {
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pic_set_irq (irq, 1); |
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} |
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ldebug ("dma_pos %d size %d\n",
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n, (r->base[1] << ncont) + (1 << ncont)); |
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| 307 | 300 |
} |
| 308 | 301 |
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| 309 | 302 |
void DMA_run (void) |
| 310 | 303 |
{
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static int in_dma; |
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| 312 | 304 |
struct dma_cont *d; |
| 313 | 305 |
int icont, ichan; |
| 314 | 306 |
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if (in_dma) {
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log ("attempt to re-enter dma\n");
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return; |
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} |
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in_dma = 1; |
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d = dma_controllers; |
| 322 | 308 |
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for (icont = 0; icont < 2; icont++, d++) {
|
| ... | ... | |
| 330 | 316 |
channel_run (icont, ichan); |
| 331 | 317 |
} |
| 332 | 318 |
} |
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in_dma = 0; |
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| 334 | 319 |
} |
| 335 | 320 |
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| 336 | 321 |
void DMA_register_channel (int nchan, |
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DMA_read_handler read_handler,
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DMA_misc_handler misc_handler)
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DMA_transfer_handler transfer_handler,
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void *opaque)
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| 339 | 324 |
{
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struct dma_regs *r; |
| 341 | 326 |
int ichan, ncont; |
| ... | ... | |
| 344 | 329 |
ichan = nchan & 3; |
| 345 | 330 |
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r = dma_controllers[ncont].regs + ichan; |
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r->read_handler = read_handler; |
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r->misc_handler = misc_handler; |
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r->transfer_handler = transfer_handler; |
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r->opaque = opaque; |
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} |
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|
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/* request the emulator to transfer a new DMA memory block ASAP */ |
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void DMA_schedule(int nchan) |
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{
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); |
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| 349 | 340 |
} |
| 350 | 341 |
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| 351 | 342 |
void DMA_init (void) |
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